| Commit message (Expand) | Author | Age | Files | Lines |
* | treewide: replace '---help---' in Kconfig files with 'help' | Masahiro Yamada | 2020-06-13 | 6 | -60/+60 |
* | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl... | Linus Torvalds | 2020-06-10 | 130 | -612/+13263 |
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| * | clk: mediatek: Remove ifr{0,1}_cfg_regs structures | Stephen Boyd | 2020-06-09 | 1 | -30/+0 |
| * | clk: baikal-t1: remove redundant assignment to variable 'divider' | Colin Ian King | 2020-06-09 | 1 | -1/+1 |
| * | clk: baikal-t1: fix spelling mistake "Uncompatible" -> "Incompatible" | Colin Ian King | 2020-06-09 | 1 | -1/+1 |
| *-----. | Merge branches 'clk-vc5', 'clk-hsdk', 'clk-mediatek' and 'clk-baikal' into cl... | Stephen Boyd | 2020-06-01 | 22 | -32/+3644 |
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| | | | | * | clk: Add Baikal-T1 CCU Dividers driver | Serge Semin | 2020-05-30 | 5 | -0/+1210 |
| | | | | * | clk: Add Baikal-T1 CCU PLLs driver | Serge Semin | 2020-05-30 | 7 | -0/+860 |
| | | | * | | clk: mediatek: assign the initial value to clk_init_data of mtk_mux | Weiyi Lu | 2020-05-29 | 1 | -1/+1 |
| | | | * | | clk: mediatek: Add MT6765 clock support | Owen Chen | 2020-05-29 | 9 | -0/+1523 |
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| | | * | | CLK: HSDK: CGU: add support for 148.5MHz clock | Eugeniy Paltsev | 2020-05-29 | 1 | -0/+1 |
| | | * | | CLK: HSDK: CGU: support PLL bypassing | Eugeniy Paltsev | 2020-05-29 | 1 | -27/+34 |
| | | * | | CLK: HSDK: CGU: check if PLL is bypassed first | Eugeniy Paltsev | 2020-05-29 | 1 | -4/+4 |
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| | * / | clk: vc5: Add support for IDT VersaClock 5P49V6965 | Adam Ford | 2020-05-30 | 1 | -0/+11 |
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| *-------. \ | Merge branches 'clk-mmp', 'clk-intel', 'clk-ingenic', 'clk-qcom' and 'clk-sil... | Stephen Boyd | 2020-06-01 | 35 | -82/+7246 |
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| | | | | | * | | clk: clk-si5341: Add support for the Si5345 series | Mike Looijmans | 2020-05-29 | 1 | -5/+64 |
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| | | | | * | | clk: qcom: Add missing msm8998 ufs_unipro_core_clk_src | Jeffrey Hugo | 2020-05-29 | 1 | -0/+27 |
| | | | | * | | clk: qcom: gcc-msm8939: Add MSM8939 Generic Clock Controller | Bryan O'Donoghue | 2020-05-27 | 3 | -0/+3997 |
| | | | | * | | clk: qcom: gcc: Add support for Secure control source clock | Taniya Das | 2020-05-27 | 1 | -0/+21 |
| | | | | * | | clk: qcom: gcc: Add support for a new frequency for SC7180 | Taniya Das | 2020-05-27 | 1 | -36/+37 |
| | | | | * | | clk: qcom: gcc: Add missing UFS clocks for SM8150 | Vinod Koul | 2020-05-14 | 1 | -0/+84 |
| | | | | * | | clk: qcom: gcc: Add GPU and NPU clocks for SM8150 | Vinod Koul | 2020-05-14 | 1 | -0/+64 |
| | | | | * | | clk: qcom: mmcc-msm8996: Properly describe GPU_GX gdsc | Bjorn Andersson | 2020-05-14 | 1 | -0/+2 |
| | | | | * | | clk: qcom: gdsc: Handle GDSC regulator supplies | Bjorn Andersson | 2020-05-14 | 2 | -0/+27 |
| | | | | * | | clk: qcom: msm8916: Fix the address location of pll->config_reg | Bryan O'Donoghue | 2020-04-22 | 1 | -4/+4 |
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| | | | * | | clk: ingenic: Mark ingenic_tcu_of_match as __maybe_unused | Stephen Boyd | 2020-05-29 | 1 | -1/+1 |
| | | | * | | clk: X1000: Add FIXDIV for SSI clock of X1000. | 周琰杰 (Zhou Yanjie) | 2020-05-29 | 1 | -6/+111 |
| | | | * | | clk: Ingenic: Add CGU driver for X1830. | 周琰杰 (Zhou Yanjie) | 2020-05-29 | 3 | -0/+459 |
| | | | * | | clk: Ingenic: Adjust cgu code to make it compatible with X1830. | 周琰杰 (Zhou Yanjie) | 2020-05-29 | 7 | -4/+41 |
| | | | * | | clk: Ingenic: Remove unnecessary spinlock when reading registers. | 周琰杰 (Zhou Yanjie) | 2020-05-29 | 1 | -11/+1 |
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| | | * | | clk: intel: remove redundant initialization of variable rate64 | Colin Ian King | 2020-05-29 | 1 | -1/+1 |
| | | * | | clk: intel: Add CGU clock driver for a new SoC | Rahul Tanwar | 2020-05-27 | 7 | -0/+1612 |
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| | * | | clk: mmp2: Add audio clock controller driver | Lubomir Rintel | 2020-05-28 | 3 | -0/+450 |
| | * | | clk: mmp2: Add support for power islands | Lubomir Rintel | 2020-05-28 | 4 | -1/+168 |
| | * | | clk: mmp2: Add the audio clock | Lubomir Rintel | 2020-05-28 | 1 | -0/+4 |
| | * | | clk: mmp2: Add the I2S clocks | Lubomir Rintel | 2020-05-28 | 1 | -0/+46 |
| | * | | clk: mmp2: Rename mmp2_pll_init() to mmp2_main_clk_init() | Lubomir Rintel | 2020-05-28 | 1 | -2/+2 |
| | * | | clk: mmp2: Move thermal register defines up a bit | Lubomir Rintel | 2020-05-28 | 1 | -4/+4 |
| | * | | clk: mmp: frac: Allow setting bits other than the numerator/denominator | Lubomir Rintel | 2020-05-28 | 2 | -0/+4 |
| | * | | clk: mmp: frac: Do not lose last 4 digits of precision | Lubomir Rintel | 2020-05-28 | 1 | -8/+16 |
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| *-------. \ | Merge branches 'clk-unisoc', 'clk-trivial', 'clk-bcm', 'clk-st' and 'clk-ast2... | Stephen Boyd | 2020-06-01 | 10 | -66/+136 |
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| | | | | | * | | clk: ast2600: Fix AHB clock divider for A1 | Eddie James | 2020-05-27 | 1 | -6/+25 |
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| | | | | * / | clk: clk-flexgen: fix clock-critical handling | Alain Volmat | 2020-05-27 | 1 | -0/+1 |
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| | | | * | | clk: bcm2835: Constify struct debugfs_reg32 | Rikard Falkeborn | 2020-05-27 | 1 | -3/+3 |
| | | | * | | clk: bcm2835: Remove casting to bcm2835_clk_register | Nathan Chancellor | 2020-05-27 | 1 | -31/+37 |
| | | | * | | clk: bcm2835: Fix return type of bcm2835_register_gate | Nathan Chancellor | 2020-05-27 | 1 | -5/+5 |
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| | | * | | clk: versatile: remove redundant assignment to pointer clk | Colin Ian King | 2020-05-27 | 1 | -1/+1 |
| | | * | | clk: clk-xgene: Fix a typo in Kconfig | Christophe JAILLET | 2020-05-05 | 1 | -1/+1 |
| | | * | | clk: Remove unused inline function clk_debug_reparent | YueHaibing | 2020-05-05 | 1 | -4/+0 |
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| | * | | clk: sprd: add mipi_csi_xx gate clocks | Chunyan Zhang | 2020-05-27 | 1 | -0/+32 |