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* clk: socfpga: stratix10: fix the divider for the emac_ptp_free_clkDinh Nguyen2020-09-221-1/+1
* clk: samsung: exynos4: mark 'chipid' clock as CLK_IGNORE_UNUSEDMarek Szyprowski2020-09-221-2/+2
* Merge tag 'for-5.10-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/teg...Stephen Boyd2020-09-222-5/+4
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| * clk: tegra: Fix missing prototype for tegra210_clk_register_emc()Thierry Reding2020-09-211-0/+2
| * clk: tegra: Always program PLL_E when enabledThierry Reding2020-09-211-3/+0
| * clk: tegra: Capitalization fixesThierry Reding2020-09-211-2/+2
* | Merge tag 'v5.9-clk-samsung-fixes' of https://git.kernel.org/pub/scm/linux/ke...Stephen Boyd2020-09-151-0/+5
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| * | clk: samsung: Keep top BPLL mux on Exynos542x enabledMarek Szyprowski2020-09-151-0/+5
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* | clk: qcom: lpass: Correct goto target in lpass_core_sc7180_probe()Jing Xiangfeng2020-09-101-3/+4
* | clk: versatile: Add of_node_put() before return statementSumera Priyadarsini2020-09-101-1/+3
* | clk: bcm: dvp: Select the reset frameworkMaxime Ripard2020-09-101-0/+1
* | clk: rockchip: Fix initialization of mux_pll_src_4plls_pNathan Chancellor2020-08-191-1/+1
* | clk: davinci: Use the correct size when allocating memoryChristophe JAILLET2020-08-191-1/+1
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* Merge tag 'acpi-5.9-rc1-2' of git://git.kernel.org/pub/scm/linux/kernel/git/r...Linus Torvalds2020-08-153-79/+102
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| * clk: x86: Support RV architectureAkshu Agrawal2020-08-071-15/+38
| * clk: x86: Change name from ST to FCHAkshu Agrawal2020-08-072-13/+13
| * ACPI: APD: Change name from ST to FCHAkshu Agrawal2020-08-071-2/+2
* | Merge tag 'pwm/for-5.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/...Linus Torvalds2020-08-151-1/+6
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| * | clk: pwm: Use 64-bit division functionGuru Das Srinagesh2020-06-171-1/+6
* | | Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds2020-08-1261-588/+4230
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| *-----. \ \ Merge branches 'clk-microchip', 'clk-mmp', 'clk-unused' and 'clk-at91' into c...Stephen Boyd2020-08-0428-285/+2438
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| | | | | * | | clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea2020-07-242-0/+1060
| | | | | * | | clk: at91: clk-utmi: add utmi support for sama7g5Claudiu Beznea2020-07-242-5/+102
| | | | | * | | clk: at91: clk-sam9x60-pll: re-factor to support plls with multiple outputsClaudiu Beznea2020-07-243-186/+433
| | | | | * | | clk: at91: clk-programmable: add mux_table optionClaudiu Beznea2020-07-2413-17/+38
| | | | | * | | clk: at91: clk-peripheral: add support for changeable parent rateClaudiu Beznea2020-07-249-16/+119
| | | | | * | | clk: at91: clk-master: add master clock support for SAMA7G5Claudiu Beznea2020-07-242-5/+312
| | | | | * | | clk: at91: clk-generated: add mux_table optionClaudiu Beznea2020-07-245-8/+16
| | | | | * | | clk: at91: clk-generated: pass the id of changeable parent at registrationClaudiu Beznea2020-07-245-35/+37
| | | | | * | | clk: at91: replace conditional operator with double logical notClaudiu Beznea2020-07-245-8/+8
| | | | | * | | clk: at91: sckc: register slow_rc with accuracy optionClaudiu Beznea2020-07-241-2/+3
| | | | | * | | clk: at91: sam9x60: fix main rc oscillator frequencyClaudiu Beznea2020-07-241-1/+1
| | | | | * | | clk: at91: sam9x60-pll: use frac when setting frequencyClaudiu Beznea2020-07-241-4/+8
| | | | | * | | clk: at91: sam9x60-pll: check fcore against rangesClaudiu Beznea2020-07-242-2/+12
| | | | | * | | clk: at91: sam9x60-pll: use logical or for range checkClaudiu Beznea2020-07-241-1/+1
| | | | | * | | clk: at91: clk-sam9x60-pll: fix mul maskClaudiu Beznea2020-07-241-1/+1
| | | | | * | | clk: at91: clk-generated: check best_rate against rangesClaudiu Beznea2020-07-241-2/+2
| | | | | * | | clk: at91: clk-generated: continue if __clk_determine_rate() returns errorClaudiu Beznea2020-07-241-1/+2
| | | | | * | | clk: at91: fix possible dead lock in new driversAhmad Fatoum2020-07-244-4/+4
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| | | | * / / clk: drop unused function __clk_get_flagsJulia Lawall2020-08-031-6/+0
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| | | * / / clk: mmp: avoid missing prototype warningArnd Bergmann2020-07-292-0/+2
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| | * / / clk: sparx5: Add Sparx5 SoC DPLL clock driverLars Povlsen2020-07-292-0/+296
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| *-------. \ \ Merge branches 'clk-fallthru', 'clk-ingenic', 'clk-tegra', 'clk-sirf' and 'cl...Stephen Boyd2020-08-048-85/+228
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| | | | | | * | | clk: qoriq: add LS1021A core pll mux optionsMichael Krummsdorf2020-07-281-1/+9
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| | | | | * / / clk: clk-atlas6: fix return value check in atlas6_clk_init()Xu Wang2020-07-281-1/+1
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| | | | * / / clk: tegra: pll: Improve PLLM enable-state detectionDmitry Osipenko2020-07-281-5/+15
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| | | * | | clk: X1000: Add support for calculat REFCLK of USB PHY.周琰杰 (Zhou Yanjie)2020-07-281-1/+83
| | | * | | clk: JZ4780: Reformat the code to align it.周琰杰 (Zhou Yanjie)2020-07-281-45/+45
| | | * | | clk: JZ4780: Add functions for enable and disable USB PHY.周琰杰 (Zhou Yanjie)2020-07-281-30/+35
| | | * | | clk: Ingenic: Add RTC related clocks for Ingenic SoCs.周琰杰 (Zhou Yanjie)2020-07-283-0/+38
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