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* Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-05-073-12/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk fixes from Stephen Boyd: "A couple more patches that would be good to get into -rc1: - Revert an i.MX patch that's causing video failures because division math goes sideways - Fix a clang + W=1 build isue where FIELD_PREP() is taking a 32-bit variable instead of the usual u64 type - Fix a Kconfig bug in the StarFive JH7110 clk config that selects a reset controller when it can't be selected" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified case clk: sp7021: Adjust width of _m in HWM_FIELD_PREP() Revert "clk: imx: composite-8m: Add support to determine_rate"
| * clk: starfive: Fix RESET_STARFIVE_JH7110 can't be selected in a specified caseHal Feng2023-05-031-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When (ARCH_STARFIVE [=n] && COMPILE_TEST [=y] && RESET_CONTROLLER [=n]), RESET_STARFIVE_JH7110 can't be selected by CLK_STARFIVE_JH7110_SYS and CLK_STARFIVE_JH7110_AON. Add a condition `if RESET_CONTROLLER` to fix it. Also, delete redundant selected options of CLK_STARFIVE_JH7110_AON because these options are already selected by the dependency. Fixes: edab7204afe5 ("clk: starfive: Add StarFive JH7110 system clock driver") Fixes: b2ab3c94f41f ("clk: starfive: Add StarFive JH7110 always-on clock driver") Signed-off-by: Hal Feng <hal.feng@starfivetech.com> Link: https://lore.kernel.org/r/20230418123756.62495-2-hal.feng@starfivetech.com Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * clk: sp7021: Adjust width of _m in HWM_FIELD_PREP()Nathan Chancellor2023-05-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building with clang + W=1, there is a warning around an internal comparison check within the FIELD_PREP() macro, due to a 32-bit variable comparison against ~0ull: drivers/clk/clk-sp7021.c:316:8: error: result of comparison of constant 18446744073709551615 with expression of type 'typeof (_Generic((_m), ...' (aka 'unsigned int') is always false [-Werror,-Wtautological-constant-out-of-range-compare] r0 |= HWM_FIELD_PREP(MASK_SEL_FRA, clk->p[SEL_FRA]); ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ drivers/clk/clk-sp7021.c:45:15: note: expanded from macro 'HWM_FIELD_PREP' (_m << 16) | FIELD_PREP(_m, value); \ ^~~~~~~~~~~~~~~~~~~~~ include/linux/bitfield.h:114:3: note: expanded from macro 'FIELD_PREP' __BF_FIELD_CHECK(_mask, 0ULL, _val, "FIELD_PREP: "); \ ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/bitfield.h:71:53: note: expanded from macro '__BF_FIELD_CHECK' BUILD_BUG_ON_MSG(__bf_cast_unsigned(_mask, _mask) > \ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~^~~~~~~ note: (skipping 1 expansions in backtrace; use -fmacro-backtrace-limit=0 to see all) include/linux/compiler_types.h:397:22: note: expanded from macro 'compiletime_assert' _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__) ~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/compiler_types.h:385:23: note: expanded from macro '_compiletime_assert' __compiletime_assert(condition, msg, prefix, suffix) ~~~~~~~~~~~~~~~~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ include/linux/compiler_types.h:377:9: note: expanded from macro '__compiletime_assert' if (!(condition)) \ ^~~~~~~~~ This is expected given the types of the input. Increase the size of the temporary variable in HWM_FIELD_PREP() to eliminate the warning, which follows the logic of commit cfd6fb45cfaf ("crypto: ccree - avoid out-of-range warnings from clang") for the same reasons. Signed-off-by: Nathan Chancellor <nathan@kernel.org> Link: https://lore.kernel.org/r/20230501-sp7021-field_prep-warning-v1-1-5b36d71feefe@kernel.org Reported-by: kernel test robot <lkp@intel.com> Link: https://lore.kernel.org/202303221947.pXP2v4xJ-lkp@intel.com/ Reviewed-by: Nick Desaulniers <ndesaulniers@google.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
| * Revert "clk: imx: composite-8m: Add support to determine_rate"Adam Ford2023-05-031-7/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 156e96ff2172518b6f83e97d8f11f677bc668e22. This patch was found to cause some division issues on the i.MX8MP which causes the video clocks to not properly divide when division was greate than 8. This causes video failures on disp1_pix and disp2_pix clocks. Until a better solution is found, we'll have to revert this. Signed-off-by: Adam Ford <aford173@gmail.com> Link: https://lore.kernel.org/r/20230423123828.1346511-1-aford173@gmail.com Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
* | Merge tag 'clk-for-linus' of ↵Linus Torvalds2023-04-30334-7084/+29827
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux Pull clk updates from Stephen Boyd: "Nothing looks out of the ordinary in this batch of clk driver updates. There are a couple patches to the core clk framework, but they're all basically cleanups or debugging aids. The driver updates and new additions are dominated in the diffstat by Qualcomm and MediaTek drivers. Qualcomm gained a handful of new drivers for various SoCs, and MediaTek gained a bunch of drivers for MT8188. The MediaTek drivers are being modernized as well, so there are updates all over that vendor's clk drivers. There's also a couple other new clk drivers in here, for example the Starfive JH7110 SoC support is added. Outside of the two major SoC vendors though, we have the usual collection of non-critical fixes and cleanups to various clk drivers. It's good to see that we're getting more cleanups and modernization patches. Maybe one day we'll be able to properly split clk providers from clk consumers. Core: - Print an informational message before disabling unused clks New Drivers: - BCM63268 timer clock and reset controller - Frequency Hopping (FHCTL) on MediaTek MT6795, MT8173, MT8192 and MT8195 SoCs - Mediatek MT8188 SoC clk drivers - Clock driver for Sunplus SP7021 SoC - Clk driver support for Loongson-2 SoCs - Clock driver for Skyworks Si521xx I2C PCIe clock generators - Initial Starfive JH7110 clk/reset support - Global clock controller drivers for Qualcomm SM7150, IPQ9574, MSM8917 and IPQ5332 SoCs - GPU clock controller drivers for SM6115, SM6125, SM6375 and SA8775P SoCs Updates: - Shrink size of clk_fractional_divider a little - Convert various clk drivers to devm_of_clk_add_hw_provider() - Convert platform clk drivers to remove_new() - Converted most Mediatek clock drivers to struct platform_driver - MediaTek clock drivers can be built as modules - Reimplement Loongson-1 clk driver with DT support - Migrate socfpga clk driver to of_clk_add_hw_provider() - Support for i3c clks on Aspeed ast2600 SoCs - Add clock generic devm_clk_hw_register_gate_parent_data - Add audiomix block control for i.MX8MP - Add support for determine_rate to i.MX composite-8m - Let the LCDIF Pixel clock of i.MX8MM and i.MX8MN set parent rate - Provide clock name in error message for clk-gpr-mux on get parent failure - Drop duplicate imx_clk_mux_flags macro - Register the i.MX8MP Media Disp2 Pix clock as bus clock - Add Media LDB root clock to i.MX8MP - Make i.MX8MP nand_usdhc_bus clock as non-critical - Fix the rate table for i.MX fracn-gppll - Disable HW control for the fracn-gppll in order to be controlled by register write - Add support for interger PLL in fracn-gppll - Add mcore_booted module parameter to i.MX93 provider - Add NIC, A55 and ARM PLL clocks to i.MX93 - Fix i.MX8ULP XBAR_DIVBUS and AD_SLOW clock parents - Use "divider closest" clock type for PLL4_PFD dividers on i.MX8ULP to get more accurate clock rates - Mark the MU0_Bi and TPM5 clocks on i.MX8ULP as critical - Update some of the i.MX critical clocks flags to allow glitchless on-the-fly rate change. - Add I2C5 clock on Renesas R-Car V3H - Exynos850: Add CMU_G3D clock controller for the Mali GPU - Extract Exynos5433 (ARM64) clock controller power management code to common driver parts - Exynos850: make PMU_ALIVE_PCLK clock critical - Add Audio, thermal, camera (CSI-2), Image Signal Processor/Channel Selector (ISPCS), and video capture (VIN) clocks on Renesas R-Car V4H - Add video capture (VIN) clocks on Renesas R-Car V3H - Add Cortex-A53 System CPU (Z2) clocks on Renesas R-Car V3M and V3H - Support for Stromer Plus PLL on Qualcomm IPQ5332 - Add a missing reset to Qualcomm QCM2290 - Migrate Qualcomm IPQ4019 to clk_parent_data - Make USB GDSCs enter retention state when disabled on Qualcomm SM6375, MSM8996 and MSM8998 SoCs - Set floor rounding clk_ops for Qualcomm QCM2290 SDCC2 clk - Add two EMAC GDSCs on Qualcomm SC8280XP - Use shared rcg clk ops in Qualcomm SM6115 GCC - Park Qualcomm SM8350 PCIe PIPE clks when disabled - Add GDSCs to Qualcomm SC7280 LPASS audio clock controller - Add missing XO clocks to Qualcomm MSM8226 and MSM8974 - Convert some Qualcomm clk DT bindings to YAML - Reparenting fix for the clock supplying camera modules on Rockchip rk3399 - Mark more critical (bus-)clocks on Rockchip rk3588" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (290 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: starfive: Delete the redundant dev_set_drvdata() in JH7110 clock drivers clk: rockchip: rk3588: make gate linked clocks critical clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: starfive: Avoid casting iomem pointers clk: microchip: fix potential UAF in auxdev release callback clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: mediatek: fhctl: Mark local variables static clk: sifive: make SiFive clk drivers depend on ARCH_ symbols clk: uniphier: Use managed `of_clk_add_hw_provider()` clk: si5351: Use managed `of_clk_add_hw_provider()` clk: si570: Use managed `of_clk_add_hw_provider()` clk: si514: Use managed `of_clk_add_hw_provider()` clk: lmk04832: Use managed `of_clk_add_hw_provider()` ...
| * Merge branch 'clk-imx' into clk-nextStephen Boyd2023-04-2512-43/+430
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * clk-imx: (25 commits) clk: imx: imx8ulp: update clk flag for system critical clock clk: imx: imx8ulp: Add tpm5 clock as critical gate clock clk: imx: imx8ulp: keep MU0_B clock enabled always clk: imx: imx8ulp: Add divider closest support to get more accurate clock rate clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parents clk: imx: imx93: Add nic and A55 clk dt-bindings: clock: imx93: add NIC, A55 and ARM PLL CLK clk: imx: imx93: add mcore_booted module paratemter clk: imx: fracn-gppll: Add 300MHz freq support for imx9 clk: imx: fracn-gppll: support integer pll clk: imx: fracn-gppll: disable hardware select control clk: imx: fracn-gppll: fix the rate table clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-critical clk: imx: imx8mp: Add LDB root clock dt-bindings: clock: imx8mp: Add LDB clock entry clk: imx: imx8mp: correct DISP2 pixel clock type clk: imx: drop duplicated macro clk: imx: clk-gpr-mux: Provide clock name in error message clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rate clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rate ...
| | * clk: imx: imx8ulp: update clk flag for system critical clockJacky Bai2023-04-091-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to support bus fabric clock frequency changed on the fly, need to update some bus clocks'flags to make sure these clocks'frequency and parent can be changed on the fly. For these clocks, HW can make sure no glitch will be introduced when changing on the fly. In order to support DDR DFS, the HW register bit for DDR_SEL and DDR_DIV clock will be modified by TF-A. So need to update these two clock's flag to make sure that the linux kernel side can correct these clocks' SW state to reflect the actual HW state. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Add tpm5 clock as critical gate clockJacky Bai2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The TPM5 is used for broadcast timer purpose and registered with TIMER_OF_DECLARE. As the clock driver is not ready at that stage, so the TPM5 clock is configured in bootloader(TF-A). if we just remove the TPM5 clock from linux will introduce a risk that the TPM5's parent clock will be gated, then lead to TPM's channel control config can NOT be written into register successfully. Due to the above reason, we still need to add the TPM5 clock into linux clock but register it as a simple critical gate clock to make sure its parent is always on. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: keep MU0_B clock enabled alwaysJacky Bai2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Keep the A35<->M33 MU0_B clock enabled always for low power communication. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Add divider closest support to get more accurate clock rateJacky Bai2023-04-092-8/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If a divider's parent clock has fractional part, it will hard to round out a more accurate clock rate for this divider, add the 'CLK_DIVIDER_ROUND_CLOSEST' flags for such divider to get a more accurate clock rate. Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8ulp: Fix XBAR_DIVBUS and AD_SLOW clock parentsPeng Fan2023-04-091-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | XBAR_DIVBUS and AD_SLOW should set parent to XBAR_AD_DIVPLAT and XBAR_DIVBUS respectively, not the NIC_AD. otherwise we will get wrong clock rate. Fixes: c43a801a5789 ("clk: imx: Add clock driver for imx8ulp") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230331063814.2462059-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx93: Add nic and A55 clkPeng Fan2023-04-091-2/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The A55 clock logic as below: A55_PLL ----------------->\ A55_SEL-->A55_CORE A55_CCM_ROOT--->A55_GATE->/ Add A55 CPU clk to support freq change. Add NIC CLK to reflect the clk status Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-8-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx93: add mcore_booted module paratemterPeng Fan2023-04-092-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add mcore_booted boot parameter which could simplify AMP clock management. To i.MX93, there is CCM(clock control Module) to generate clock root clock, anatop(analog PLL module) to generate PLL, and LPCG (clock gating) to gate clocks to peripherals. As below: anatop->ccm->lpcg->peripheral Linux handles the clock management and the auxiliary core is under control of Linux. Although there is per hardware domain control for LPCG and CCM, auxiliary core normally only use LPCG hardware domain control to avoid linux gate off the clk to peripherals and leave CCM ana anatop to Linux. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-6-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: Add 300MHz freq support for imx9Jacky Bai2023-04-091-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add 300MHz frequency config support on i.MX93 PLL. Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-5-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: support integer pllPeng Fan2023-04-092-7/+68
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The fracn gppll could be configured in FRAC or INTEGER mode during hardware design. The current driver only support FRAC mode, while this patch introduces INTEGER support. When the PLL is INTEGER pll, there is no mfn, mfd, the calculation is as below: Fvco_clk = (Fref / DIV[RDIV] ) * DIV[MFI] Fclko_odiv = Fvco_clk / DIV[ODIV] In this patch, we reuse the FRAC pll logic with some condition check to simplify the driver Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: disable hardware select controlPeng Fan2023-04-091-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When programming PLL, should disable Hardware control select to make PLL controlled by register, not hardware inputs through OSCPLL. Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: fracn-gppll: fix the rate tablePeng Fan2023-04-091-7/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Fvco should be range 2.4GHz to 5GHz, the original table voilate the spec, so update the table to fix it. Fixes: c196175acdd3 ("clk: imx: clk-fracn-gppll: Add more freq config for video pll") Fixes: 044034efbeea ("clk: imx: clk-fracn-gppll: fix mfd value") Fixes: 1b26cb8a77a4 ("clk: imx: support fracn gppll") Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403095300.3386988-2-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: change the 'nand_usdhc_bus' clock to non-criticalHaibo Chen2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'nand_usdhc_bus' clock is only need to be enabled when usdhc or nand module is active, so change it to non-critical clock type. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-4-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: Add LDB root clockLiu Ying2023-04-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds "media_ldb_root_clk" clock for the LDB in the MEDIAMIX subsystem. Reviewed-by: Sandor Yu <Sandor.yu@nxp.com> Signed-off-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20230403094633.3366446-3-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: imx8mp: correct DISP2 pixel clock typePeng Fan2023-04-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The MEDIA_DISP2_CLK_ROOT use ccm_ahb_channel, it is bus type. Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403094633.3366446-1-peng.fan@oss.nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
| | * clk: imx: drop duplicated macroPeng Fan2023-04-031-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Drop duplicated macro definition Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Ahmad Fatoum <a.fatoum@pengutronix.de> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230403082728.3199849-1-peng.fan@oss.nxp.com
| | * clk: imx: clk-gpr-mux: Provide clock name in error messageStefan Wahren2023-03-311-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In error case the error message doesn't provide much context: imx:clk-gpr-mux: failed to get parent (-EINVAL) So additionally provide the clock name in the message, in order to simplify the further analyze. Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230308184603.10049-1-stefan.wahren@i2se.com
| | * clk: imx: Let IMX8MN_CLK_DISP_PIXEL set parent rateAdam Ford2023-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the display pixel clock needs to be evenly divide down from the video_pll_out clock which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll 594000000 video_pll_bypass 594000000 video_pll_out 594000000 disp_pixel 148500000 disp_pixel_clk 148500000 Now that composite-8m supports determine_rate, we can allow disp_pixel to set the parent rate which then switches every clock in the chain to a new frequency when disp_pixel cannot evenly divide from video_pll_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-5-aford173@gmail.com
| | * clk: imx8mm: Let IMX8MM_CLK_LCDIF_PIXEL set parent rateAdam Ford2023-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default the display pixel clock needs to be evenly divide down from 594MHz which rules out a significant number of resolution and refresh rates. The current clock tree looks something like: video_pll1 594000000 video_pll1_bypass 594000000 video_pll1_out 594000000 lcdif_pixel 148500000 Now that composite-8m supports determine_rate, we can allow lcdif_pixel to set the parent rate which then switches every clock in the chain to a new frequency when lcdif_pixel cannot evenly divide from video_pll1_out. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-4-aford173@gmail.com
| | * clk: imx: Add imx8m_clk_hw_composite_flags macroAdam Ford2023-03-311-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to set custom flags to imx8m_clk_hw_composite, split it off into a separate macro which can accept additional flags. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-3-aford173@gmail.com
| | * clk: imx: composite-8m: Add support to determine_rateAdam Ford2023-03-311-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Similar to imx/clk-composite-93 and imx/clk-divider-gate, the imx8m_clk_composite_divider_ops can support determine_rate. Without this the parent clocks are set to a fixed value, and if a consumer needs a slower reate, the clock is divided, but the division is only as good as the parent clock rate. With this added, the system can attempt to adjust the parent rate if the proper flags are set which can lead to a more precise clock value. Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230323230127.120883-2-aford173@gmail.com
| | * clk: imx: imx8mp: Add audiomix block controlMarek Vasut2023-03-312-1/+278
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the other block control IPs in i.MX8M, the audiomix is mostly a series of clock gates and muxes. Model it as a large static table of gates and muxes with one exception, which is the PLL14xx . The PLL14xx SAI PLL has to be registered separately. Reviewed-by: Marco Felsch <m.felsch@pengutronix.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Fabio Estevam <festevam@gmail.com> Tested-by: Adam Ford <aford173@gmail.com> #imx8mp-beacon-kit Tested-by: Alexander Stein <alexander.stein@ew.tq-group.com> Tested-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Marek Vasut <marex@denx.de> Tested-by: Richard Leitner <richard.leitner@skidata.com> Signed-off-by: Abel Vesa <abel.vesa@linaro.org> Link: https://lore.kernel.org/r/20230301163257.49005-2-marex@denx.de
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| *-----. \ Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into ↵Stephen Boyd2023-04-2552-980/+17993
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | clk-next * clk-of: clk: add missing of_node_put() in "assigned-clocks" property parsing * clk-samsung: clk: samsung: exynos850: Make PMU_ALIVE_PCLK critical clk: samsung: Convert to platform remove callback returning void clk: samsung: exynos5433: Extract PM support to common ARM64 layer clk: samsung: Extract parent clock enabling to common function clk: samsung: Extract clocks registration to common function clk: samsung: exynos850: Add AUD and HSI main gate clocks clk: samsung: exynos850: Implement CMU_G3D domain clk: samsung: clk-pll: Implement pll0818x PLL type clk: samsung: Set dev in samsung_clk_init() clk: samsung: Don't pass reg_base to samsung_clk_register_pll() clk: samsung: Remove np argument from samsung_clk_init() dt-bindings: clock: exynos850: Add AUD and HSI main gate clocks dt-bindings: clock: exynos850: Add Exynos850 CMU_G3D * clk-rockchip: clk: rockchip: rk3588: make gate linked clocks critical clk: rockchip: rk3399: allow clk_cifout to force clk_cifout_src to reparent * clk-qcom: (57 commits) clk: qcom: gcc-sc8280xp: Add EMAC GDSCs clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clk clk: qcom: add the GPUCC driver for sa8775p dt-bindings: clock: qcom: describe the GPUCC clock for SA8775P clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handling clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in lpass_cc_sc7280_desc clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registration dt-bindings: clock: qcom,sc7280-lpasscc: Add qcom,adsp-pil-mode property clk: qcom: rpm: Use managed `of_clk_add_hw_provider()` clk: qcom: Add Global Clock Controller driver for IPQ9574 dt-bindings: clock: Add ipq9574 clock and reset definitions clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait value clk: qcom: gcc-sm6115: Mark RCGs shared where applicable clk: qcom: dispcc-qcm2290: Add MDSS_CORE reset dt-bindings: clock: dispcc-qcm2290: Add MDSS_CORE reset clk: qcom: apss-ipq-pll: add support for IPQ5332 dt-bindings: clock: qcom,a53pll: add IPQ5332 compatible clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL types dt-bindings: mailbox: qcom,apcs-kpss-global: fix SDX55 'if' match dt-bindings: mailbox: qcom,apcs-kpss-global: correct SDX55 clocks ...
| | | | | * | clk: qcom: gcc-sc8280xp: Add EMAC GDSCsAndrew Halaney2023-04-241-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the EMAC GDSCs to allow the EMAC hardware to be enabled. Acked-by: Stephen Boyd <sboyd@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Tested-by: Brian Masney <bmasney@redhat.com> Signed-off-by: Andrew Halaney <ahalaney@redhat.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230413191541.1073027-2-ahalaney@redhat.com
| | | | | * | clk: qcom: dispcc-qcm2290: Remove inexistent DSI1PHY clkKonrad Dybcio2023-04-141-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's only one DSI PHY on this SoC. Remove the ghost entry for the clock produced by a secondary one. Fixes: cc517ea3333f ("clk: qcom: Add display clock controller driver for QCM2290") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412-topic-qcm_dispcc-v1-2-bf2989a75ae4@linaro.org
| | | | | * | clk: qcom: add the GPUCC driver for sa8775pShazad Hussain2023-04-143-0/+635
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the clock driver for the Qualcomm Graphics Clock control module. Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com> [Bartosz: make ready for upstream] Co-developed-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230411125910.401075-3-brgl@bgdev.pl
| | | | | * | clk: qcom: gcc-sm8350: fix PCIe PIPE clocks handlingDmitry Baryshkov2023-04-141-34/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On SM8350 platform the PCIe PIPE clocks require additional handling to function correctly. They are to be switched to the tcxo source before turning PCIe GDSCs off and should be switched to PHY PIPE source once they are working. Switch PCIe PHY clocks to use clk_regmap_phy_mux_ops, which provide support for this dance. Fixes: 44c20c9ed37f ("clk: qcom: gcc: Add clock driver for SM8350") Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230412134829.3686467-1-dmitry.baryshkov@linaro.org
| | | | | * | clk: qcom: lpassaudiocc-sc7280: Add required gdsc power domain clks in ↵Mohammad Rafi Shaik2023-04-141-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | lpass_cc_sc7280_desc Add GDSCs in lpass_cc_sc7280_desc struct. When qcom,adsp-pil-mode is enabled, GDSCs required to solve dependencies in lpass_audiocc probe(). Fixes: 0cbcfbe50cbf ("clk: qcom: lpass: Handle the regmap overlap of lpasscc and lpass_aon") Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-4-quic_mohs@quicinc.com
| | | | | * | clk: qcom: lpasscc-sc7280: Skip qdsp6ss clock registrationSrinivasa Rao Mandadapu2023-04-141-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The qdsp6ss memory region is being shared by ADSP remoteproc device and lpasscc clock device, hence causing memory conflict. To avoid this, when qdsp6ss clocks are being enabled in remoteproc driver, skip qdsp6ss clock registration if "qcom,adsp-pil-mode" is enabled and also assign max_register value. Fixes: 4ab43d171181 ("clk: qcom: Add lpass clock controller driver for SC7280") Signed-off-by: Srinivasa Rao Mandadapu <quic_srivasam@quicinc.com> Signed-off-by: Mohammad Rafi Shaik <quic_mohs@quicinc.com> Reviewed-by: Stephen Boyd <swboyd@chromium.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230407092255.119690-3-quic_mohs@quicinc.com
| | | | | * | clk: qcom: rpm: Use managed `of_clk_add_hw_provider()`Lars-Peter Clausen2023-04-121-8/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the managed `devm_of_clk_add_hw_provider()` instead of `of_clk_add_hw_provider()`. This makes sure the provider gets automatically removed on unbind and allows to completely eliminate the drivers `remove()` callback. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230410014502.27929-7-lars@metafoo.de
| | | | | * | clk: qcom: Add Global Clock Controller driver for IPQ9574Devi Priya2023-04-073-0/+4257
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Global Clock Controller (GCC) driver for ipq9574 based devices Co-developed-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Anusha Rao <quic_anusha@quicinc.com> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316072940.29137-3-quic_devipriy@quicinc.com
| | | | | * | clk: qcom: gpucc-sm6375: Configure CX_GDSC disable wait valueKonrad Dybcio2023-04-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Configure the disable wait value on the CX GDSC to ensure we don't get any undefined behavior. This was omitted when first adding the driver. Fixes: 8397e24278b3 ("clk: qcom: Add GPU clock controller driver for SM6375") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230329140135.2178957-1-konrad.dybcio@linaro.org
| | | | | * | clk: qcom: gcc-sm6115: Mark RCGs shared where applicableKonrad Dybcio2023-04-071-25/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vast majority of shared RCGs were not marked as such. Fix it. Fixes: cbe63bfdc54f ("clk: qcom: Add Global Clock controller (GCC) driver for SM6115") Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230404224719.909746-1-konrad.dybcio@linaro.org
| | | | | * | clk: qcom: dispcc-qcm2290: Add MDSS_CORE resetKonrad Dybcio2023-04-051-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the MDSS_CORE reset which can be asserted to reset the state of the entire MDSS. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230316-topic-qcm_dispcc_reset-v1-2-dd3708853014@linaro.org
| | | | | * | clk: qcom: apss-ipq-pll: add support for IPQ5332Kathiravan T2023-03-231-1/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ5332 APSS PLL is of type Stromer Plus. Add support for the same. To configure the stromer plus PLL separate API (clock_stromer_pll_configure) to be used. To achieve this, introduce the new member pll_type in device data structure and call the appropriate function based on this. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230217083308.12017-4-quic_kathirav@quicinc.com
| | | | | * | clk: qcom: apss-ipq-pll: refactor the driver to accommodate different PLL typesKathiravan T2023-03-231-19/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | APSS PLL found on the IPQ8074 and IPQ6018 are of type Huayra PLL. But, IPQ5332 APSS PLL is of type Stromer Plus. To accommodate both these PLLs, refactor the driver to take the clk_alpha_pll, alpha_pll_config via driver data. Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230217083308.12017-2-quic_kathirav@quicinc.com
| | | | | * | clk: qcom: gcc-msm8998: Update the .pwrsts for usb gdscKonrad Dybcio2023-03-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller on msm8998 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307123159.3797551-3-konrad.dybcio@linaro.org
| | | | | * | clk: qcom: gcc-msm8996: Update the .pwrsts for usb gdscKonrad Dybcio2023-03-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller on MSM8996 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307123159.3797551-2-konrad.dybcio@linaro.org
| | | | | * | clk: qcom: gcc-sm6375: Update the .pwrsts for usb gdscKonrad Dybcio2023-03-221-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The USB controller on sm6375 doesn't retain its state when the system goes into low power state and the GDSCs are turned off. This can be observed by the USB connection not coming back alive after putting the device into suspend, essentially breaking USB. Work around this by updating the .pwrsts for the USB GDSCs so they only transition to retention state in low power. This change should be reverted when a proper suspend sequence is implemented in the USB drivers. Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307123159.3797551-1-konrad.dybcio@linaro.org
| | | | | * | clk: qcom: smd-rpm: Add clocks for MSM8917Otto Pflüger2023-03-161-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MSM8917 has mostly the same rpm clocks as MSM8953, but lacks RF_CLK3 and IPA_CLK and additionally has the BIMC_GPU clock. Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230223180935.60546-5-otto.pflueger@abscue.de
| | | | | * | clk: qcom: Add global clock controller driver for MSM8917Otto Pflüger2023-03-163-0/+3314
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This driver provides clocks, resets and power domains needed for various components of the MSM8917 SoC and the very similar QM215 SoC. According to [1] in the downstream kernel, the GPU clock has a different source mapping on QM215 (gcc_gfx3d_map vs gcc_gfx3d_map_qm215). [1]: https://git.codelinaro.org/clo/la/kernel/msm-4.9/-/blob/LF.UM.8.6.2-28000-89xx.0/include/dt-bindings/clock/msm-clocks-hwio-8952.h#L298 Signed-off-by: Otto Pflüger <otto.pflueger@abscue.de> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230223180935.60546-3-otto.pflueger@abscue.de
| | | | | * | clk: qcom: smd: Add XO RPM clocks for MSM8226/MSM8974Rayyan Ansari2023-03-161-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the XO and XO_A clocks to the MSM8974 clock list, which is also used on MSM8226. Signed-off-by: Rayyan Ansari <rayyan@ansari.sh> Tested-by: Luca Weiss <luca@z3ntu.xyz> Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230121192540.9177-2-rayyan@ansari.sh
| | | | | * | clk: qcom: ipq5332: mark GPLL4 as ignore unused temporarilyKathiravan T2023-03-161-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clock framework disables the GPLL4 source since there are no active users for this source currently. Some of the clocks initialized by the bootloaders uses the GPLL4 as the source. Due to this, when the GPLL4 is disabled by the clock framework, system is going for the reboot. To avoid this, mark the GPLL4 as ignore unused so that clock framework doesn't disable it. Once the users of this source is enabled, we can get rid of this flag. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-6-quic_kathirav@quicinc.com
| | | | | * | clk: qcom: add Global Clock controller (GCC) driver for IPQ5332 SoCKathiravan T2023-03-163-0/+3822
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for the global clock controller found on IPQ5332 SoC. PLL used on IPQ5332 is of type Stromer Plus PLL, however the programming sequence is same as Stromer PLL, so lets re-use the Stromer PLL ops. Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-5-quic_kathirav@quicinc.com
| | | | | * | clk: qcom: Add STROMER PLUS PLL type for IPQ5332Kathiravan T2023-03-162-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the support for stromer plus pll, which is found on the IPQ5332 SoCs. Programming sequence is same as the stromer pll, so we can re-use the same. Reviewed-by: Stephen Boyd <sboyd@kernel.org> Signed-off-by: Kathiravan T <quic_kathirav@quicinc.com> Signed-off-by: Bjorn Andersson <andersson@kernel.org> Link: https://lore.kernel.org/r/20230307062232.4889-3-quic_kathirav@quicinc.com
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-26 12:11:05 +0100