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path:
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/
drivers
/
clocksource
/
timer-riscv.c
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Commit message (
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Author
Age
Files
Lines
*
clocksource/drivers/riscv: Patch riscv_clock_next_event() jump before first use
Matt Evans
2023-02-13
1
-5
/
+5
*
clocksource/drivers/riscv: Get rid of clocksource_arch_init() callback
Lad Prabhakar
2023-02-13
1
-0
/
+5
*
clocksource/drivers/riscv: Increase the clock source rating
Samuel Holland
2023-02-13
1
-1
/
+1
*
clocksource/drivers/timer-riscv: Set CLOCK_EVT_FEAT_C3STOP based on DT
Anup Patel
2023-02-13
1
-0
/
+10
*
Revert "clocksource/drivers/riscv: Events are stopped during CPU suspend"
Conor Dooley
2022-12-01
1
-1
/
+1
*
RISC-V: Add Sstc extension support
Palmer Dabbelt
2022-08-11
1
-1
/
+24
|
\
|
*
RISC-V: Prefer sstc extension if available
Atish Patra
2022-08-11
1
-1
/
+24
*
|
riscv: cpu: Add 64bit hartid support on RV64
Sunil V L
2022-07-20
1
-7
/
+8
|
/
*
clocksource/drivers/riscv: Events are stopped during CPU suspend
Samuel Holland
2022-05-18
1
-1
/
+1
*
RISC-V: KVM: Add timer functionality
Atish Patra
2021-10-04
1
-0
/
+9
*
RISC-V: Remove CLINT related code from timer and arch
Anup Patel
2020-08-20
1
-15
/
+2
*
clocksource/drivers/timer-riscv: Use per-CPU timer interrupt
Anup Patel
2020-06-10
1
-3
/
+40
*
clocksource: riscv: add notrace to riscv_sched_clock
Zong Li
2020-01-05
1
-1
/
+1
*
riscv: add support for MMIO access to the timer registers
Christoph Hellwig
2019-11-13
1
-4
/
+19
*
riscv: abstract out CSR names for supervisor vs machine mode
Christoph Hellwig
2019-11-05
1
-4
/
+4
*
riscv: don't use the rdtime(h) pseudo-instructions
Christoph Hellwig
2019-09-05
1
-13
/
+4
*
RISC-V: Remove per cpu clocksource
Atish Patra
2019-08-06
1
-4
/
+2
*
clocksource/drivers/riscv: Fix clocksource mask
Atish Patra
2019-03-23
1
-3
/
+2
*
clocksource/drivers/riscv: Add required checks during clock source init
Atish Patra
2019-02-23
1
-3
/
+20
*
clocksource/drivers/riscv: Change name riscv_timer to timer-riscv
Daniel Lezcano
2018-12-18
1
-0
/
+118