linux - linux

	Commit message (Collapse)	Author	Age	Files	Lines
*	crypto: inside-secure - align the cipher and hash send functions	Ofer Heifetz	2017-06-20	1	-1/+1
\| \| \| \| \| \| \| \| \|	The cipher and hash send functions both set the results variable, to be used later by the caller. Align the way they're setting this variable. Signed-off-by: Ofer Heifetz <oferh@marvell.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - optimize DSE bufferability control	Igal Liberman	2017-06-20	2	-0/+2
\| \| \| \| \| \| \| \| \|	Configure the data write bufferability to always buffer packets in the DSE. This change slightly improves performance. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - enable single WR in DSE configuration	Igal Liberman	2017-06-20	2	-0/+2
\| \| \| \| \| \| \| \| \| \| \| \|	When enable_single_wr is not enabled, the DSE will only write those parts of a result descriptor that need updating, which means a final result descriptor will be written in 2 or 3 smaller transfers. When enable_single_wr is enabled the DSE will combine these 2-3 updates into one large write transfer, generally improving performance. Signed-off-by: Igal Liberman <igall@marvell.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - fix incorrect DSE data cache setting	Antoine Ténart	2017-06-20	1	-1/+1
\| \| \| \| \| \| \| \| \| \|	Set the correct value to the DSE data cache, using WR_CACHE_3BITS instead of RD_CACHE_3BITS. This fixes an incorrect setting and helps improving performances. Reported-by: Igal Liberman <igall@marvell.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - fix the ring wr_cache offset	Antoine Ténart	2017-06-20	1	-1/+1
\| \| \| \| \| \| \| \| \|	The EIP197_HIA_xDR_CFG_WR_CACHE macro was defined to use an offset of 23, which is wrong as it's actually 25. Fix this. Reported-by: Igal Liberman <igall@marvell.com> Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - use hmac ipad/opad constants	Antoine Ténart	2017-06-20	1	-2/+3
\| \| \| \| \| \| \|	Replace the hmac ipad/opad values by their defined constants. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
*	crypto: inside-secure - add SafeXcel EIP197 crypto engine driver	Antoine Ténart	2017-06-10	6	-0/+3262
	Add support for Inside Secure SafeXcel EIP197 cryptographic engine, which can be found on Marvell Armada 7k and 8k boards. This driver currently implements: ecb(aes), cbc(aes), sha1, sha224, sha256 and hmac(sah1) algorithms. Two firmwares are needed for this engine to work. Their are mostly used for more advanced operations than the ones supported (as of now), but we still need them to pass the data to the internal cryptographic engine. Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>