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path: root/drivers/cxl/cxl.h (follow)
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* cxl/region: Fix 'distance' calculation with passthrough portsDan Williams2022-11-051-0/+2
* cxl/pmem: Fix cxl_pmem_region and cxl_memdev leakDan Williams2022-11-041-1/+1
* cxl/region: describe targets and nr_targets members of cxl_region_paramsBagas Sanjaya2022-08-051-0/+2
* cxl/acpi: Minimize granularity for x1 interleavesDan Williams2022-08-021-0/+2
* cxl/region: prevent underflow in ways_to_cxl()Dan Carpenter2022-08-011-1/+1
* cxl/region: Introduce cxl_pmem_region objectsDan Williams2022-07-261-1/+35
* cxl/pmem: Fix offline_nvdimm_bus() to offline by bridgeDan Williams2022-07-261-0/+1
* cxl/region: Add region driver boiler plateDan Williams2022-07-261-0/+1
* cxl/hdm: Commit decoder state to hardwareDan Williams2022-07-251-1/+12
* cxl/region: Program target listsDan Williams2022-07-251-0/+2
* cxl/region: Attach endpoint decodersDan Williams2022-07-251-0/+20
* cxl/acpi: Add a host-bridge index lookup mechanismDan Williams2022-07-251-0/+2
* cxl/region: Enable the assignment of endpoint decoders to regionsDan Williams2022-07-251-0/+11
* cxl/region: Allocate HPA capacity to regionsDan Williams2022-07-251-0/+2
* cxl/region: Add interleave geometry attributesBen Widawsky2022-07-251-0/+33
* cxl/region: Add a 'uuid' attributeBen Widawsky2022-07-251-0/+25
* cxl/region: Add region creation supportBen Widawsky2022-07-221-0/+18
* cxl/mem: Enumerate port targets before adding endpointsDan Williams2022-07-221-0/+5
* cxl/port: Move dport tracking to an xarrayDan Williams2022-07-221-5/+7
* cxl/port: Move 'cxl_ep' references to an xarray per portDan Williams2022-07-221-3/+1
* cxl/port: Record parent dport when adding portsDan Williams2022-07-221-2/+5
* cxl/port: Record dport in endpoint referencesDan Williams2022-07-221-0/+2
* cxl/hdm: Track next decoder to allocateDan Williams2022-07-221-0/+2
* cxl/hdm: Add 'mode' attribute to decoder objectsDan Williams2022-07-221-0/+9
* cxl/hdm: Enumerate allocated DPADan Williams2022-07-221-0/+2
* cxl/core: Define a 'struct cxl_endpoint_decoder'Dan Williams2022-07-211-1/+14
* cxl/core: Define a 'struct cxl_root_decoder'Dan Williams2022-07-211-2/+13
* cxl/core: Define a 'struct cxl_switch_decoder'Dan Williams2022-07-211-8/+22
* cxl/port: Read CDAT tableIra Weiny2022-07-201-0/+7
* cxl/pmem: Delete unused nvdimm attributeDan Williams2022-07-111-1/+0
* cxl/port: Cache CXL host bridge dataDan Williams2022-07-101-0/+2
* cxl: Introduce cxl_to_{ways,granularity}Dan Williams2022-07-101-0/+26
* cxl/core: Drop is_cxl_decoder()Dan Williams2022-07-101-1/+0
* cxl/core: Drop ->platform_res attribute for root decodersDan Williams2022-07-101-5/+1
* cxl/core: Rename ->decoder_range ->hpa_rangeDan Williams2022-07-101-2/+2
* cxl/core: Use is_endpoint_decoderBen Widawsky2022-06-211-0/+1
* cxl: Drop cxl_device_lock()Dan Williams2022-04-281-78/+0
* cxl/core/port: Add endpoint decodersBen Widawsky2022-02-091-0/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-091-0/+6
* cxl/core/port: Add switch port enumerationDan Williams2022-02-091-0/+19
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-091-4/+4
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-091-0/+4
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-091-6/+27
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-091-12/+4
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-091-0/+1
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-091-0/+3
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-091-0/+2
* cxl: Prove CXL lockingDan Williams2022-02-091-0/+81
* cxl/core: Track port depthBen Widawsky2022-02-091-0/+2
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-091-1/+15
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