summaryrefslogtreecommitdiffstats
path: root/drivers/cxl/mem.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* cxl/mem: Enumerate port targets before adding endpointsDan Williams2022-07-221-29/+1
* cxl/port: Record parent dport when adding portsDan Williams2022-07-221-4/+6
* cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams2022-07-101-0/+23
* cxl: Fix cleanup of port devices on failure to probe driver.Jonathan Cameron2022-06-211-1/+6
* cxl/port: Move endpoint HDM Decoder Capability init to port driverDan Williams2022-05-191-11/+0
* cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams2022-05-191-2/+1
* cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams2022-05-191-79/+1
* cxl/mem: Skip range enumeration if mem_enable clearDan Williams2022-05-191-1/+1
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-191-6/+8
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-191-1/+1
* cxl/mem: Validate port connectivity before dvsec rangesDan Williams2022-05-191-16/+16
* cxl/mem: Fix cxl_mem_probe() error exitDan Williams2022-05-191-2/+4
* cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams2022-05-191-18/+1
* cxl/mem: Drop mem_enabled check from wait_for_media()Dan Williams2022-05-191-4/+0
* cxl: Drop cxl_device_lock()Dan Williams2022-04-281-2/+2
* PM: CXL: Disable suspendDan Williams2022-04-231-1/+21
* cxl/mem: Replace redundant debug message with a commentDan Williams2022-04-131-4/+10
* cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()Dan Williams2022-04-131-6/+6
* cxl/mem: Make cxl_dvsec_range() init failure fatalDan Williams2022-04-131-0/+3
* cxl/mem: Drop DVSEC vs EFI Memory Map sanity checkDan Williams2022-04-131-23/+1
* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-091-0/+228
* cxl: Rename mem to pciBen Widawsky2021-05-261-1525/+0
* cxl/core: Refactor CXL register lookup for bridge reuseDan Williams2021-05-151-44/+6
* cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams2021-05-151-20/+24
* cxl/mem: Move some definitions to mem.hDan Williams2021-05-151-20/+1
* cxl/mem: Fix memory device capacity probingDan Williams2021-04-171-2/+5
* cxl/mem: Fix register block offset calculationBen Widawsky2021-04-161-1/+1
* cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAXRobert Richter2021-04-061-1/+1
* cxl/mem: Disable cxl device power managementDan Williams2021-04-061-0/+1
* cxl/mem: Do not rely on device_add() side effects for dev_set_name() failuresDan Williams2021-04-061-10/+29
* cxl/mem: Fix synchronization mechanism for device removal vs ioctl operationsDan Williams2021-04-061-47/+50
* cxl/mem: Use sysfs_emit() for attribute show routinesDan Williams2021-04-061-4/+4
* cxl/mem: Fix potential memory leakBen Widawsky2021-02-221-1/+3
* cxl/mem: Return -EFAULT if copy_to_user() failsDan Carpenter2021-02-191-1/+4
* cxl/mem: Add set of informational commandsBen Widawsky2021-02-171-0/+9
* cxl/mem: Enable commands via CELBen Widawsky2021-02-171-7/+216
* cxl/mem: Add a "RAW" send commandBen Widawsky2021-02-171-0/+132
* cxl/mem: Add basic IOCTL interfaceBen Widawsky2021-02-171-1/+282
* cxl/mem: Register CXL memX devicesDan Williams2021-02-171-2/+283
* cxl/mem: Find device capabilitiesBen Widawsky2021-02-171-2/+575
* cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpointsDan Williams2021-02-171-0/+62
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 05:08:27 +0100