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path: root/drivers/cxl/pci.c (follow)
Commit message (Expand)AuthorAgeFilesLines
* cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams2022-05-191-135/+0
* cxl/pci: Move cxl_await_media_ready() to the coreDan Williams2022-05-191-44/+1
* cxl/pci: Drop wait_for_valid() from cxl_await_media_ready()Dan Williams2022-05-191-4/+0
* cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams2022-05-191-2/+2
* cxl/pci: Make cxl_dvsec_ranges() failure not fatal to cxl_pciDan Williams2022-04-131-9/+18
* cxl/pci: Add debug for DVSEC range init failuresDan Williams2022-04-131-3/+10
* cxl/mbox: Use new return_code handlingDavidlohr Bueso2022-04-131-1/+2
* cxl/mbox: Improve handling of mbox_cmd hw return codesDavidlohr Bueso2022-04-131-1/+1
* cxl/pci: Use CXL_MBOX_SUCCESS to check against mbox_cmd return codeDavidlohr Bueso2022-04-131-2/+2
* cxl/pci: Drop shadowed variableDan Williams2022-04-081-1/+0
* cxl/pci: Emit device serial numberDan Williams2022-02-091-0/+1
* cxl/pci: Implement wait for media activeBen Widawsky2022-02-091-1/+48
* cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky2022-02-091-0/+119
* cxl/pci: Cache device DVSEC offsetBen Widawsky2022-02-091-0/+6
* cxl/pci: Store component register base in cxldsBen Widawsky2022-02-091-0/+11
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-091-1/+1
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-091-52/+0
* cxl: Flesh out register namesBen Widawsky2022-02-091-7/+7
* cxl/pci: Defer mailbox status checks to command timeoutsDan Williams2022-02-091-101/+33
* cxl/pci: Implement Interface Ready TimeoutBen Widawsky2022-02-091-0/+35
* cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2021-11-151-60/+60
* cxl/pci: Use pci core's DVSEC functionalityBen Widawsky2021-10-291-24/+2
* cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky2021-10-291-36/+37
* cxl/pci: Add @base to cxl_register_mapDan Williams2021-10-291-15/+16
* cxl/pci: Make more use of cxl_register_mapBen Widawsky2021-10-291-34/+25
* cxl/pci: Remove pci request/release regionsBen Widawsky2021-10-291-5/+0
* cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams2021-10-291-1/+1
* cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky2021-10-291-3/+0
* cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky2021-09-211-33/+35
* cxl/pci: Use module_pci_driverDan Williams2021-09-211-22/+8
* cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams2021-09-211-922/+2
* cxl/pci: Drop idr.hDan Williams2021-09-211-1/+0
* cxl/mbox: Introduce the mbox_send operationDan Williams2021-09-211-55/+21
* cxl/pci: Clean up cxl_mem_get_partition_info()Dan Williams2021-09-211-24/+11
* cxl/pci: Make 'struct cxl_mem' device type genericDan Williams2021-09-211-40/+35
* cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)2021-09-071-2/+2
* cxl/pci: Fix lockdown levelDan Williams2021-09-071-1/+1
* cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny2021-08-111-8/+6
* cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny2021-08-101-5/+91
* cxl/pci: Store memory capacity valuesIra Weiny2021-08-071-3/+33
* cxl/pci: Simplify register setupBen Widawsky2021-08-061-26/+12
* cxl/pci: Ignore unknown register block typesBen Widawsky2021-08-061-8/+12
* cxl/core: Move memdev management to coreBen Widawsky2021-08-061-227/+1
* cxl/pci: Introduce cdevm_file_operationsDan Williams2021-08-061-27/+38
* cxl: Move cxl_core to new directoryBen Widawsky2021-08-061-1/+1
* cxl/pci: Rename CXL REGLOC IDBen Widawsky2021-06-181-1/+1
* cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams2021-06-161-6/+17
* cxl/pci: Add media provisioning required commandsBen Widawsky2021-06-151-0/+19
* cxl/pci: Add HDM decoder capabilitiesBen Widawsky2021-06-061-0/+15
* cxl/pci: Reserve individual register block regionsIra Weiny2021-06-061-0/+2
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-25 23:58:26 +0100