summaryrefslogtreecommitdiffstats
path: root/drivers/cxl (follow)
Commit message (Expand)AuthorAgeFilesLines
...
| * | cxl/pci: Update commentIra Weiny2023-09-161-1/+4
| * | cxl/port: Quiet warning messages from the cxl_test environmentDan Williams2023-09-162-2/+7
* | | Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams2023-10-315-12/+60
|\ \ \
| * | | cxl: Add support for reading CXL switch CDAT tableDave Jiang2023-10-282-5/+20
| * | | cxl: Add checksum verification to CDAT from CXLDave Jiang2023-10-281-7/+23
| * | | cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang2023-10-283-0/+17
* | | | Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams2023-10-3110-129/+406
|\ \ \ \ | |_|_|/ |/| | |
| * | | cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter2023-10-283-6/+4
| * | | cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Robert Richter2023-10-281-3/+3
| * | | cxl/pci: Disable root port interrupts in RCH modeTerry Bowman2023-10-281-0/+32
| * | | cxl/pci: Add RCH downstream port error loggingTerry Bowman2023-10-281-0/+96
| * | | cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman2023-10-282-0/+46
| * | | cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman2023-10-281-13/+31
| * | | PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman2023-10-281-0/+1
| * | | cxl/pci: Add RCH downstream port AER register discoveryRobert Richter2023-10-285-0/+61
| * | | cxl/port: Remove Component Register base address from struct cxl_portRobert Richter2023-10-282-5/+1
| * | | cxl/pci: Remove Component Register base address from struct cxl_dev_stateRobert Richter2023-10-282-5/+0
| * | | cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter2023-10-283-39/+43
| * | | cxl/pci: Store the endpoint's Component Register mappings in struct cxl_dev_s...Robert Richter2023-10-283-4/+9
| * | | cxl/port: Pre-initialize component register mappingsRobert Richter2023-10-281-5/+7
| * | | cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter2023-10-282-7/+7
| * | | cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams2023-10-281-12/+31
| * | | cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter2023-10-285-20/+20
| * | | cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams2023-10-281-15/+19
| |/ /
* | | cxl/region: Fix x1 root-decoder granularity calculationsJim Harris2023-10-271-1/+8
* | | cxl/region: Fix cxl_region_rwsem lock held when returning to user spaceLi Zhijian2023-10-271-1/+1
* | | cxl/region: Use cxl_calc_interleave_pos() for auto-discoveryAlison Schofield2023-10-271-112/+15
* | | cxl/region: Calculate a target position in a region interleaveAlison Schofield2023-10-271-0/+127
* | | cxl/region: Prepare the decoder match range helper for reuseAlison Schofield2023-10-261-6/+11
* | | cxl/region: Do not try to cleanup after cxl_region_setup_targets() failsJim Harris2023-10-241-7/+7
* | | cxl/mem: Fix shutdown orderDan Williams2023-10-091-1/+1
* | | cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams2023-10-068-49/+90
* | | cxl/pci: Fix sanitize notifier setupDan Williams2023-10-063-42/+50
* | | cxl/pci: Clarify devm host for memdev relative setupDan Williams2023-10-063-12/+13
* | | cxl/pci: Remove inconsistent usage of dev_err_probe()Dan Williams2023-10-061-11/+2
* | | cxl/pci: Remove hardirq handler for cxl_request_irq()Dan Williams2023-10-061-6/+6
* | | cxl/pci: Cleanup 'sanitize' to always pollDan Williams2023-09-303-39/+26
* | | cxl/pci: Remove unnecessary device reference management in sanitize workDan Williams2023-09-291-5/+0
|/ /
* | cxl/acpi: Annotate struct cxl_cxims_data with __counted_byKees Cook2023-09-221-2/+2
* | cxl/port: Fix cxl_test register enumeration regressionDan Williams2023-09-221-4/+9
|/
* cxl/region: Refactor granularity select in cxl_port_setup_targets()Alison Schofield2023-09-151-9/+8
* cxl/region: Match auto-discovered region decoders by HPA rangeAlison Schofield2023-09-151-1/+23
* cxl/mbox: Fix CEL logic for poison and security commandsIra Weiny2023-09-141-11/+12
* cxl/pci: Replace host_bridge->native_aer with pcie_aer_is_native()Smita Koralahalli2023-09-121-2/+1
* cxl/pci: Fix appropriate checking for _OSC while handling CXL RAS registersSmita Koralahalli2023-09-121-3/+3
* cxl/memdev: Only show sanitize sysfs files when supportedDavidlohr Bueso2023-07-283-1/+78
* cxl/memdev: Document security state in kern-docDavidlohr Bueso2023-07-281-0/+1
* cxl/acpi: Return 'rc' instead of '0' in cxl_parse_cfmws()Breno Leitao2023-07-181-1/+1
* cxl/acpi: Fix a use-after-free in cxl_parse_cfmws()Breno Leitao2023-07-181-2/+1
* cxl/mem: Fix a double shift bugDan Carpenter2023-07-141-1/+1
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-04 06:01:01 +0100