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* cxl/mem: Add the cxl_mem driverBen Widawsky2022-02-099-5/+391
* cxl/core/port: Add switch port enumerationDan Williams2022-02-093-25/+438
* cxl/memdev: Add numa_node attributeDan Williams2022-02-091-0/+17
* cxl/pci: Emit device serial numberDan Williams2022-02-093-0/+14
* cxl/pci: Implement wait for media activeBen Widawsky2022-02-092-1/+50
* cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky2022-02-093-0/+146
* cxl/pci: Cache device DVSEC offsetBen Widawsky2022-02-092-0/+8
* cxl/pci: Store component register base in cxldsBen Widawsky2022-02-092-0/+14
* cxl/core/port: Remove @host argument for dport + decoder enumerationDan Williams2022-02-097-24/+24
* cxl/port: Add a driver for 'struct cxl_port' objectsBen Widawsky2022-02-098-29/+108
* cxl/core: Emit modalias for CXL devicesDan Williams2022-02-091-9/+17
* cxl/core/hdm: Add CXL standard decoder enumeration to the coreDan Williams2022-02-098-49/+348
* cxl/core: Generalize dport enumeration in the coreDan Williams2022-02-096-110/+167
* cxl/pci: Rename pci.h to cxlpci.hDan Williams2022-02-094-3/+4
* cxl/port: Up-level cxl_add_dport() locking requirements to the callerDan Williams2022-02-092-2/+3
* cxl/pmem: Introduce a find_cxl_root() helperDan Williams2022-02-093-4/+60
* cxl/port: Introduce cxl_port_to_pci_bus()Dan Williams2022-02-093-5/+49
* cxl/core/port: Use dedicated lock for decoder target listDan Williams2022-02-092-7/+25
* cxl: Prove CXL lockingDan Williams2022-02-095-24/+130
* cxl/core: Track port depthBen Widawsky2022-02-092-0/+4
* cxl/core/port: Make passthrough decoder init implicitBen Widawsky2022-02-092-6/+8
* cxl/core: Fix cxl_probe_component_regs() error messageDan Williams2022-02-091-1/+1
* cxl/core/port: Clarify decoder creationBen Widawsky2022-02-093-11/+92
* cxl/core: Convert decoder range to resourceBen Widawsky2022-02-093-18/+35
* cxl/decoder: Hide physical address information from non-rootDan Williams2022-02-091-1/+1
* cxl/core/port: Rename bus.c to port.cDan Williams2022-02-092-1/+1
* cxl: Introduce module_cxl_driverBen Widawsky2022-02-091-0/+3
* cxl/acpi: Map component registers for Root PortsBen Widawsky2022-02-095-54/+80
* cxl/pci: Add new DVSEC definitionsBen Widawsky2022-02-091-0/+15
* cxl: Flesh out register namesBen Widawsky2022-02-092-16/+17
* cxl/pci: Defer mailbox status checks to command timeoutsDan Williams2022-02-091-101/+33
* cxl/pci: Implement Interface Ready TimeoutBen Widawsky2022-02-091-0/+35
* cxl: Rename CXL_MEM to CXL_PCIBen Widawsky2022-02-092-12/+13
* cxl/core: Remove cxld_const_init in cxl_decoder_alloc()Nathan Chancellor2022-01-052-5/+3
* cxl/pmem: Fix module reload vs workqueue stateDan Williams2021-11-153-3/+42
* ACPI: NUMA: Add a node and memblk for each CFMWS not in SRATAlison Schofield2021-11-151-1/+2
* cxl/test: Mock acpi_table_parse_cedt()Dan Williams2021-11-151-0/+2
* cxl/acpi: Convert CFMWS parsing to ACPI sub-table helpersDan Williams2021-11-152-147/+88
* cxl/memdev: Remove unused cxlmd fieldIra Weiny2021-11-151-2/+0
* cxl/core: Convert to EXPORT_SYMBOL_NS_GPLDan Williams2021-11-156-29/+29
* cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny2021-11-155-211/+214
* cxl/mbox: Remove bad commentIra Weiny2021-11-151-2/+0
* cxl/pmem: Fix reference counting for delayed workDan Williams2021-11-151-4/+13
* Merge tag 'cxl-for-5.16' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2021-11-0812-1311/+1580
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| * cxl/pci: Use pci core's DVSEC functionalityBen Widawsky2021-10-291-24/+2
| * cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky2021-10-291-36/+37
| * cxl/pci: Add @base to cxl_register_mapDan Williams2021-10-292-15/+26
| * cxl/pci: Make more use of cxl_register_mapBen Widawsky2021-10-291-34/+25
| * cxl/pci: Remove pci request/release regionsBen Widawsky2021-10-291-5/+0
| * cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams2021-10-291-1/+1
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