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| * | cxl: Refactor to use __free() for cxl_root allocation in cxl_find_nvdimm_brid...Dave Jiang2024-01-051-5/+3
| * | cxl: Fix device reference leak in cxl_port_perf_data_calculate()Dave Jiang2024-01-051-2/+5
| * | cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang2024-01-056-23/+28
| * | cxl: Introduce put_cxl_root() helperDave Jiang2024-01-052-0/+12
* | | Merge branch 'for-6.8/cxl-cdat' into for-6.8/cxlDan Williams2024-01-0217-39/+1009
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| * | cxl: Check qos_class validity on memdev probeDave Jiang2023-12-231-0/+103
| * | cxl: Export sysfs attributes for memory device QoS classDave Jiang2023-12-231-6/+61
| * | cxl: Store QTG IDs and related info to the CXL memory device contextDave Jiang2023-12-233-0/+92
| * | cxl: Compute the entire CXL path latency and bandwidth dataDave Jiang2023-12-231-1/+58
| * | cxl: Add helper function that calculate performance data for downstream portsDave Jiang2023-12-232-0/+78
| * | cxl: Store the access coordinates for the generic portsDave Jiang2023-12-232-0/+27
| * | cxl: Calculate and store PCI link latency for the downstream portsDave Jiang2023-12-225-0/+61
| * | cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang2023-12-223-13/+193
| * | cxl: Add callback to parse the SSLBIS subtable from CDATDave Jiang2023-12-223-0/+104
| * | cxl: Add callback to parse the DSLBIS subtable from CDATDave Jiang2023-12-221-2/+100
| * | cxl: Add callback to parse the DSMAS subtables from CDATDave Jiang2023-12-225-0/+99
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| * cxl/pmu: Ensure put_device on pmu devicesIra Weiny2023-12-151-1/+1
| * cxl/cdat: Free correct buffer on checksum errorIra Weiny2023-12-091-7/+6
| * cxl/hdm: Fix dpa translation lockingDan Williams2023-12-082-4/+3
| * cxl/memdev: Hold region_rwsem during inject and clear poison opsAlison Schofield2023-11-301-2/+16
| * cxl/core: Always hold region_rwsem while reading poison listsAlison Schofield2023-11-302-6/+8
| * cxl/hdm: Fix a benign lockdep splatDave Jiang2023-11-231-0/+2
* | cxl/region: use %pap format to print resource_size_tRandy Dunlap2024-01-021-2/+2
* | cxl/region: Add dev_dbg() detail on failure to allocate HPA spaceAlison Schofield2023-12-241-2/+3
* | cxl: Fix unregister_region() callback parameter assignmentDave Jiang2023-12-191-4/+4
* | cxl: Add Support for Get TimestampDavidlohr Bueso2023-12-072-0/+2
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* cxl/pci: Change CXL AER support check to use native AERTerry Bowman2023-11-021-2/+2
* cxl/hdm: Remove broken error pathDan Williams2023-10-312-17/+10
* cxl/hdm: Fix && vs || bugDan Carpenter2023-10-311-1/+1
* Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams2023-10-315-6/+40
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| * cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang2023-10-281-0/+25
| * cxl: Add cxl_decoders_committed() helperDave Jiang2023-10-285-6/+15
* | Merge branch 'for-6.7/cxl' into cxl/nextDan Williams2023-10-314-5/+11
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| * | cxl/mbox: Remove useless cast in cxl_mem_create_range_info()Alison Schofield2023-10-251-2/+1
| * | cxl/pci: Update commentIra Weiny2023-09-161-1/+4
| * | cxl/port: Quiet warning messages from the cxl_test environmentDan Williams2023-09-162-2/+7
* | | Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams2023-10-315-12/+60
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| * | | cxl: Add support for reading CXL switch CDAT tableDave Jiang2023-10-282-5/+20
| * | | cxl: Add checksum verification to CDAT from CXLDave Jiang2023-10-281-7/+23
| * | | cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang2023-10-283-0/+17
* | | | Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams2023-10-3110-129/+406
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| * | | cxl/core/regs: Rework cxl_map_pmu_regs() to use map->dev for devmRobert Richter2023-10-283-6/+4
| * | | cxl/core/regs: Rename phys_addr in cxl_map_component_regs()Robert Richter2023-10-281-3/+3
| * | | cxl/pci: Disable root port interrupts in RCH modeTerry Bowman2023-10-281-0/+32
| * | | cxl/pci: Add RCH downstream port error loggingTerry Bowman2023-10-281-0/+96
| * | | cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman2023-10-282-0/+46
| * | | cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman2023-10-281-13/+31
| * | | PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman2023-10-281-0/+1
| * | | cxl/pci: Add RCH downstream port AER register discoveryRobert Richter2023-10-285-0/+61
| * | | cxl/port: Remove Component Register base address from struct cxl_portRobert Richter2023-10-282-5/+1
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