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* Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds2021-09-0913-723/+988
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| * cxl/registers: Fix Documentation warningDan Williams2021-09-071-1/+14
| * cxl/pmem: Fix Documentation warningDan Williams2021-09-071-2/+28
| * cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)2021-09-071-2/+2
| * cxl/pci: Fix lockdown levelDan Williams2021-09-071-1/+1
| * cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge portsAlison Schofield2021-09-071-4/+8
| * cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny2021-08-111-8/+6
| * cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny2021-08-102-5/+96
| * cxl/pci: Store memory capacity valuesIra Weiny2021-08-072-3/+37
| * cxl/pci: Simplify register setupBen Widawsky2021-08-063-27/+13
| * cxl/pci: Ignore unknown register block typesBen Widawsky2021-08-061-8/+12
| * cxl/core: Move memdev management to coreBen Widawsky2021-08-066-234/+275
| * cxl/pci: Introduce cdevm_file_operationsDan Williams2021-08-062-27/+53
| * cxl/core: Move register mapping infrastructureDan Williams2021-08-063-228/+237
| * cxl/core: Move pmem functionalityDan Williams2021-08-064-202/+225
| * cxl/core: Improve CXL core kernel docsBen Widawsky2021-08-061-2/+9
| * cxl: Move cxl_core to new directoryBen Widawsky2021-08-066-7/+10
* | bus: Make remove callback return voidUwe Kleine-König2021-07-211-2/+1
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* cxl/pci: Rename CXL REGLOC IDBen Widawsky2021-06-182-2/+2
* cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield2021-06-181-0/+122
* cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield2021-06-181-5/+95
* cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams2021-06-165-16/+215
* cxl/pmem: Add initial infrastructure for pmem supportDan Williams2021-06-166-2/+335
* cxl/core: Add cxl-bus driver infrastructureDan Williams2021-06-162-0/+95
* cxl/pci: Add media provisioning required commandsBen Widawsky2021-06-151-0/+19
* cxl/component_regs: Fix offsetBen Widawsky2021-06-121-1/+1
* cxl/hdm: Fix decoder count calculationBen Widawsky2021-06-122-1/+8
* cxl/acpi: Introduce cxl_decoder objectsDan Williams2021-06-103-1/+347
* cxl/acpi: Enumerate host bridge root portsDan Williams2021-06-101-1/+92
* cxl/acpi: Add downstream port data to cxl_port instancesDan Williams2021-06-103-4/+167
* cxl/Kconfig: Default drivers to CONFIG_CXL_BUSDan Williams2021-06-101-0/+2
* cxl/acpi: Introduce the root of a cxl_port topologyDan Williams2021-06-105-0/+247
* cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams2021-06-061-7/+8
* cxl/pci: Add HDM decoder capabilitiesBen Widawsky2021-06-063-6/+166
* cxl/pci: Reserve individual register block regionsIra Weiny2021-06-062-4/+34
* cxl/pci: Map registers based on capabilitiesIra Weiny2021-06-063-38/+180
* cxl/pci: Reserve all device regions at onceIra Weiny2021-06-061-7/+11
* cxl/pci: Introduce cxl_decode_register_block()Ira Weiny2021-06-061-8/+18
* cxl/mem: Get rid of @cxlm.baseBen Widawsky2021-05-262-15/+11
* cxl/mem: Move register locator logic into reg setupBen Widawsky2021-05-261-67/+68
* cxl/mem: Split creation from mapping in probeBen Widawsky2021-05-261-24/+40
* cxl/mem: Use dev instead of pdev->devBen Widawsky2021-05-261-1/+1
* cxl/mem: Demarcate vendor specific capability IDsBen Widawsky2021-05-261-1/+4
* cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma2021-05-262-0/+15
* cxl: Rename mem to pciBen Widawsky2021-05-263-16/+10
* cxl/core: Refactor CXL register lookup for bridge reuseDan Williams2021-05-153-44/+66
* cxl/core: Rename bus.c to core.cDan Williams2021-05-152-9/+10
* cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams2021-05-153-28/+61
* cxl/mem: Move some definitions to mem.hDan Williams2021-05-153-77/+82
* cxl/mem: Fix memory device capacity probingDan Williams2021-04-171-2/+5
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