summaryrefslogtreecommitdiffstats
path: root/drivers/dma/sun6i-dma.c (follow)
Commit message (Collapse)AuthorAgeFilesLines
* dmaengine: sun6i: Retrieve channel count/max request from devicetreeStefan Brüns2017-10-231-1/+26
| | | | | | | | | | | | | To avoid introduction of a new compatible for each small SoC/DMA controller variation, move the definition of the channel count to the devicetree. The number of vchans is no longer explicit, but limited by the highest port/DMA request number. The result is a slight overallocation for SoCs with a sparse port mapping. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Add support for Allwinner A64 and compatiblesStefan Brüns2017-10-161-0/+20
| | | | | | | | | | | The A64 SoC has the same dma engine as the H3 (sun8i), with a reduced amount of physical channels. To allow future reuse of the compatible, leave the channel count etc. in the config data blank and retrieve it from the devicetree. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Move number of pchans/vchans/request to device structStefan Brüns2017-10-161-10/+16
| | | | | | | | | | | Preparatory patch: If the same compatible is used for different SoCs which have a common register layout, but different number of channels, the channel count can no longer be stored in the config. Store it in the device structure instead. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Enable additional burst lengths/widths on H3Stefan Brüns2017-10-161-9/+45
| | | | | | | | | | | | The H3 supports bursts lengths of 1, 4, 8 and 16 transfers, each with a width of 1, 2, 4 or 8 bytes. The register value for the the width is log2-encoded, change the conversion function to provide the correct value for width == 8. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Restructure code to allow extension for new SoCsStefan Brüns2017-10-161-28/+38
| | | | | | | | | | | | | | | | The current code mixes three distinct operations when transforming the slave config to register settings: 1. special handling of DMA_SLAVE_BUSWIDTH_UNDEFINED, maxburst == 0 2. range checking 3. conversion of raw to register values As the range checks depend on the specific SoC, move these out of the conversion to distinct operations. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Correct burst length field offsets for H3Stefan Brüns2017-10-161-7/+27
| | | | | | | | | | | | | For the H3, the burst lengths field offsets in the channel configuration register differs from earlier SoC generations. Using the A31 register macros actually configured the H3 controller do to bursts of length 1 always, which although working leads to higher bus utilisation. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Correct setting of clock autogating register for A83T/H3Stefan Brüns2017-10-161-5/+23
| | | | | | | | | | | | | | | The H83T uses a compatible string different from the A23, but requires the same clock autogating register setting. The H3 also requires setting the clock autogating register, but has the register at a different offset. Add three suitable callbacks for the existing controller generations and set it in the controller config structure. Signed-off-by: Stefan Brüns <stefan.bruens@rwth-aachen.de> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: use of_device_get_match_dataCorentin Labbe2017-09-211-4/+2
| | | | | | | | | | The usage of of_device_get_match_data reduce the code size a bit. Furthermore, it prevents an improbable dereference when of_match_device() return NULL. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Corentin Labbe <clabbe.montjoie@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: support V3s SoC variantIcenowy Zheng2017-09-051-0/+13
| | | | | | | | | | | | Allwinner V3s has a DMA engine similar to the ones from A31, but with fewer channels and DRQs. Add support for it. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: make gate bit in sun8i's DMA engines a common quirkIcenowy Zheng2017-09-051-7/+13
| | | | | | | | | | | | | | Originally we enable a special gate bit when the compatible indicates A23/33. But according to BSP sources and user manuals, more SoCs will need this gate bit. So make it a common quirk configured in the config struct. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: fix the uninitialized value for v_lliAxl-zhang2016-11-141-1/+1
| | | | | | | | | | | dma_pool_alloc does not initialize the value of the newly allocated block for the v_lli, and the uninitilize value make the tests failed which is on pine64 with dmatest. we can fix it just change the "|=" to "=" for the v_lli->cfg. Signed-off-by: Hao Zhang <hao5781286@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Add support for Allwinner A83T (sun8i) variantJean-Francois Moine2016-09-261-0/+7
| | | | | | | | | The A83T SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i-dma: Only calculate residue if state exists.Peter Griffin2016-06-211-1/+1
| | | | | | | | There is no point in calculating the residue if state does not exist to store the value. Signed-off-by: Peter Griffin <peter.griffin@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Add cyclic capabilityJean-Francois Moine2016-05-021-7/+122
| | | | | | | | DMA cyclic transfers are required by audio streaming. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Remove useless checkJean-Francois Moine2016-05-021-5/+0
| | | | | | | | The transfer direction is now checked in set_config. There is no need to check it twice. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Set default maxburst size and bus widthJean-Francois Moine2016-05-021-4/+24
| | | | | | | | | | Some DMA clients, as audio, don't set the maxburst size and bus width on the memory side when starting DMA transfers. This patch prevents such transfers to be aborted by providing system default values to the lacking ones. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Simplify lli settingJean-Francois Moine2016-04-261-55/+47
| | | | | | | | Checking the DMA config before setting the lli list avoids to do tests inside the setting loop. Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Fix impossible settings of burst and bus widthJean-Francois Moine2016-04-261-5/+5
| | | | | | | | | | | | | | In the commit 1f9cd915b64bb95f ("dmaengine: sun6i: Fix memcpy operation"), the signed values returned by convert_burst() and convert_buswidth() were stored in an unsigned value. Then, these values were considered as errors when non null. As a result, DMA transfers were rejected when the burst or buswidth had values different from 1, as 8 for the burst or 4 for the bus width. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Fix the access of the IRQ registerJean-Francois Moine2016-04-261-2/+2
| | | | | | | | | | The IRQ register number is computed, but this number was not used and the register was the one indexed by the channel index instead. Then, only the first DMA channel was working. Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Jean-Francois Moine <moinejf@free.fr> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Fix module autoload for OF platform driverLuis de Bethencourt2015-10-011-0/+1
| | | | | | | | | This platform driver has a OF device ID table but the OF module alias information is not created so module autoloading won't work. Signed-off-by: Luis de Bethencourt <luisbg@osg.samsung.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: Add an enum for the dmaengine alignment constraintsMaxime Ripard2015-08-051-1/+1
| | | | | | | | | | | | | | Most drivers need to set constraints on the buffer alignment for async tx operations. However, even though it is documented, some drivers either use a defined constant that is not matching what the alignment variable expects (like DMA_BUSWIDTH_* constants) or fill the alignment in bytes instead of power of two. Add a new enum for these alignments that matches what the framework expects, and convert the drivers to it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Add support for Allwinner H3 (sun8i) variantJens Kuske2015-05-081-0/+12
| | | | | | | | | | The H3 SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Add the proper config data and compatible string to support it. Signed-off-by: Jens Kuske <jenskuske@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'topic/alloc_removal' into for-linusVinod Koul2015-03-181-6/+0
|\
| * dmaengine: sun6i: remove device_alloc_chan_resources handlerVinod Koul2015-03-181-6/+0
| | | | | | | | | | | | | | | | Now that device_alloc_chan_resources handler in not mandatory, remove dummy implementations Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: constify of_device_id arrayFabian Frederick2015-03-181-1/+1
|/ | | | | | | | of_device_id is always used as const. (See driver.of_match_table and open firmware functions) Signed-off-by: Fabian Frederick <fabf@skynet.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Declare slave capabilities for the generic codeMaxime Ripard2014-12-221-1/+9
| | | | | | | | | | Now that the generic slave caps code can make use of the device assigned capabilities, instead of relying on a callback to be implemented. Make use of this code. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Split device_controlMaxime Ripard2014-12-221-72/+78
| | | | | | | | | Split the device_control callback of the Allwinner A31 DMA driver to make use of the newly introduced callbacks, that will eventually be used to retrieve slave capabilities. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge branch 'for-linus' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2014-12-121-35/+87
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "Main features this time are: - BAM v1.3.0 support form qcom bam dma - support for Allwinner sun8i dma - atmels eXtended DMA Controller driver - chancnt cleanup by Maxime - fixes spread over drivers" * 'for-linus' of git://git.infradead.org/users/vkoul/slave-dma: (56 commits) dmaenegine: Delete a check before free_percpu() dmaengine: ioatdma: fix dma mapping errors dma: cppi41: add a delay while setting the TD bit dma: cppi41: wait longer for the HW to return the descriptor dmaengine: fsl-edma: fixup reg offset and hw S/G support in big-endian model dmaengine: fsl-edma: fix calculation of remaining bytes drivers/dma/pch_dma: declare pch_dma_id_table as static dmaengine: ste_dma40: fix error return code dma: imx-sdma: clarify about firmware not found error Documentation: devicetree: Fix Xilinx VDMA specification dmaengine: pl330: update author info dmaengine: clarify the issue_pending expectations dmaengine: at_xdmac: Add DMA_PRIVATE ARM: dts: at_xdmac: fix bad value of dma-cells in documentation dmaengine: at_xdmac: fix missing spin_unlock dmaengine: at_xdmac: fix a bug in transfer residue computation dmaengine: at_xdmac: fix software lockup at_xdmac_tx_status() dmaengine: at_xdmac: remove chancnt affectation dmaengine: at_xdmac: prefer usage of readl/writel_relaxed dmaengine: xdmac: fix print warning on dma_addr_t variable ...
| * dmaengine: sun6i: Add support for Allwinner A23 (sun8i) variantChen-Yu Tsai2014-11-171-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | The A23 SoC has the same dma engine as the A31 (sun6i), with a reduced amount of endpoints and physical channels. Add the proper config data and compatible string to support it. A slight difference in sun8i is an undocumented register needs to be toggled for dma to function. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sun6i: support parameterized compatible stringsChen-Yu Tsai2014-11-171-34/+60
| | | | | | | | | | | | | | | | | | This patch adds support for hardware parameters tied to compatible strings, so similar hardware can reuse the driver. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: sun6i: Remove chancnt affectationsMaxime Ripard2014-11-061-1/+0
| | | | | | | | | | | | | | | | | | | | | | chanctnt is already filled by dma_async_device_register, which uses the channel list to know how much channels there is. Since it's already filled, we can safely remove it from the drivers' probe function. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | dmaengine: sun6i: Fix memcpy operationMaxime Ripard2014-11-121-31/+30
|/ | | | | | | | | | | | The prep_memcpy call was not setting any meaningful burst and width because it was relying on the dma_slave_config was not set already. Rework the needed conversion functions, and hardcode the width and burst to use. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Cc: stable@vger.kernel.org Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Remove obsolete clk muxing codeChen-Yu Tsai2014-09-241-23/+0
| | | | | | | | | | | | | | The sun6i DMA controller requires the AHB1 bus clock to be clocked from PLL6. This was originally done by the dmaengine driver during probe time. The AHB1 clock driver has since been unified, so the original code does not work. Remove the clk muxing code, and replace it with DT clk default properties. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Fix memory leaksMaxime Ripard2014-07-301-9/+12
| | | | | | | | | | | | | | The sun6i_dma_prep_memcpy and sun6i_dma_prep_slave_sg functions were both leaking the descriptor they allocated if an error was happening after a successful dma_pool_alloc call. It also fixes a memleak that was happening in the scatter gather list traversal, that was allocating as much descriptor as there was scatter gather items, but only freeing the current descriptor if an error was to arise. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Free the interrupt before killing the taskletMaxime Ripard2014-07-301-2/+2
| | | | | | | | | | | | There's still a small window between the call to sun6i_kill_tasklet and the end of the driver remove function where a spurious interrupt might trigger, and start using deallocated resources. Replace the call to synchronize_irq by a free_irq, so that we're sure that we won't get any further interrupts when we're deallocating resources. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Remove switch statement from buswidth convertion routineMaxime Ripard2014-07-301-12/+3
| | | | | | | | Since the conversion routine is quite trivial, we don't need this switch, and we can just use a simple calculation. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun61: fix warning on bad print specfierVinod Koul2014-07-281-2/+2
| | | | | | | | | | | | | | The sg_dma_len() returns unsigned int but we had driver print it as %zu, use %u as documented in Documentation/printk-formats.txt drivers/dma/sun6i-dma.c: In function ‘sun6i_dma_prep_slave_sg’: drivers/dma/sun6i-dma.c:643: warning: format ‘%zu’ expects type ‘size_t’, but argument 8 has type ‘unsigned int’ drivers/dma/sun6i-dma.c:661: warning: format ‘%zu’ expects type ‘size_t’, but argument 8 has type ‘unsigned int’ Reported-by: kbuild test robot <fengguang.wu@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: fix build failure on x86, xilinx targetsVinod Koul2014-07-281-2/+2
| | | | | | | | | | | | Since the driver defined COMPILE_TEST, it gets compiled for different arch's The driver uses __virt_to_phys() insteadof virt_to_phys, so replace it drivers/dma/sun6i-dma.c: In function ‘sun6i_dma_dump_chan_regs’: drivers/dma/sun6i-dma.c:203: error: implicit declaration of function '__virt_to_phys' Reported-by: kbuild test robot <fengguang.wu@intel.com> Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: sun6i: Add driver for the Allwinner A31 DMA controllerMaxime Ripard2014-07-251-0/+1059
The Allwinner A31 has a 16 channels DMA controller that it shares with the newer A23. Although sharing some similarities with the DMA controller of the older Allwinner SoCs, it's significantly different, I don't expect it to be possible to share the driver for these two. The A31 Controller is able to memory-to-memory or memory-to-device transfers on the 16 channels in parallel. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Vinod Koul <vinod.koul@intel.com>