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* dmaengine: xilinx_dma: Fix SG capability check for MCDMAMatthew Murrian2020-11-091-3/+4
| | | | | | | | | | | | The SG capability is inherently present with Multichannel DMA operation. The register used to check for this capability with other DMA driver types is not defined for MCDMA. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Signed-off-by: Matthew Murrian <matthew.murrian@goctsi.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1604473206-32573-4-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Fix usage of xilinx_aximcdma_tx_segmentMatthew Murrian2020-11-091-5/+24
| | | | | | | | | | | | Several code sections incorrectly use struct xilinx_axidma_tx_segment instead of struct xilinx_aximcdma_tx_segment when operating as Multichannel DMA. As their structures are similar, this just works. Fixes: 6ccd692bfb7f ("dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver support") Signed-off-by: Matthew Murrian <matthew.murrian@goctsi.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1604473206-32573-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: use readl_poll_timeout_atomic variantMarc Ferland2020-11-091-2/+2
| | | | | | | | | | | | | The xilinx_dma_poll_timeout macro is sometimes called while holding a spinlock (see xilinx_dma_issue_pending() for an example) this means we shouldn't sleep when polling the dma channel registers. To address it in xilinx poll timeout macro use readl_poll_timeout_atomic instead of readl_poll_timeout variant. Signed-off-by: Marc Ferland <ferlandm@amotus.ca> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1604473206-32573-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: fix kernel-doc style for taskletVinod Koul2020-10-081-1/+1
| | | | | | | | | | | Commit f19a11d40a78 ("dmaengine: xilinx: convert tasklets to use new tasklet_setup() API") updated driver to use new tasklet_setup() API but missed to update the documentation for the tasklet function. Fixes: f19a11d40a78 ("dmaengine: xilinx: convert tasklets to use new tasklet_setup() API") Acked-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/20201007083113.567559-4-vkoul@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx: convert tasklets to use new tasklet_setup() APIAllen Pais2020-09-181-4/+3
| | | | | | | | | | | | In preparation for unconditionally passing the struct tasklet_struct pointer to all tasklet callbacks, switch to using the new tasklet_setup() and from_tasklet() to pass the tasklet pointer explicitly. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Allen Pais <allen.lkml@gmail.com> Link: https://lore.kernel.org/r/20200831103542.305571-33-allen.lkml@gmail.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx: Simplify with dev_err_probe()Krzysztof Kozlowski2020-09-031-28/+8
| | | | | | | | | Common pattern of handling deferred probe can be simplified with dev_err_probe(). Less code and the error value gets printed. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Link: https://lore.kernel.org/r/20200828152637.16903-3-krzk@kernel.org Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Add missing check for empty listSebastian von Ohr2020-04-151-10/+10
| | | | | | | | | | | | | | The DMA transfer might finish just after checking the state with dma_cookie_status, but before the lock is acquired. Not checking for an empty list in xilinx_dma_tx_status may result in reading random data or data corruption when desc is written to. This can be reliably triggered by using dma_sync_wait to wait for DMA completion. Signed-off-by: Sebastian von Ohr <vonohr@smaract.com> Tested-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/20200303130518.333-1-vonohr@smaract.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: In dma channel probe fix node order dependencyRadhey Shyam Pandey2020-02-251-22/+17
| | | | | | | | | | | | | | | | | | | | | | | In overlay application we noticed that dma channel node probe order is inverted i.e s2mm channel is probed first followed by mm2s channel. The reason for this inversion is fdtoverlay utility which uses a function called fdt_add_subnode(*). It stores the subnodes after the properties, this has the effect of inserting the new subnode before any others and the end result is a reversal. Because of this inverted channel probe order, the node probed first is assigned a '0' index instead of Channel ID should be '0' for tx and '1' for rx and dmatest client using the DT convention fails in dma transfer as channel are swapped. To fix above behavior and make channel assignment index independent of probe order, always assign mm2s channel at '0' index and the s2mm channel at IP specific fixed offset derived from the max_channels count. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1580388865-9960-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Extend dma_config structure to store max channel countRadhey Shyam Pandey2020-02-251-1/+8
| | | | | | | | | | | Extend dma_config structure to store the max channel count. This input is used to populate dma device channel nodes at the fixed offset. It serves as a preparatory patch for removing dma channel DT node order dependency, added in the subsequent commit. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1580388865-9960-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Reset DMA channel in dma_terminate_allRadhey Shyam Pandey2020-02-241-8/+9
| | | | | | | | | | | | Reset DMA channel after stop to ensure that pending transfers and FIFOs in the datapath are flushed or completed. It also cleanup the terminate path and removes stop for the cyclic mode as after the reset stop is not required. This fixes intermittent data verification failure when xilinx dma test the client is stressed and loaded/unloaded multiple times. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1580283909-32678-1-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge branch 'fixes' into nextVinod Koul2019-11-141-1/+9
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| * dmaengine: xilinx_dma: Fix control reg update in vdma_channel_set_configRadhey Shyam Pandey2019-10-151-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | In vdma_channel_set_config clear the delay, frame count and master mask before updating their new values. It avoids programming incorrect state when input parameters are different from default. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Acked-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1569495060-18117-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: Fix 64-bit simple AXIDMA transferRadhey Shyam Pandey2019-10-151-1/+2
| | | | | | | | | | | | | | | | | | | | In AXI DMA simple mode also pass MSB bits of source and destination address to xilinx_write function. It fixes simple AXI DMA operation mode using 64-bit addressing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1569495060-18117-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Add Xilinx AXI MCDMA Engine driver supportRadhey Shyam Pandey2019-11-061-9/+451
| | | | | | | | | | | | | | | | | | | | | | | | | | Add support for AXI Multichannel Direct Memory Access (AXI MCDMA) core, which is a soft Xilinx IP core that provides high-bandwidth direct memory access between memory and AXI4-Stream target peripherals. The AXI MCDMA core provides scatter-gather interface with multiple independent transmit and receive channels. The driver supports device_prep_slave_sg slave transfer mode. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Extend dma_config struct to store irq routine handleRadhey Shyam Pandey2019-11-061-2/+6
| | | | | | | | | | | | | | | | | | | | | | Extend dma_config structure to store irq routine handle. It enables runtime handler selection based on xdma_ip_type and serves as preparatory patch for adding MCDMA IP support. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Suggested-by: Vinod Koul <vkoul@kernel.org> Link: https://lore.kernel.org/r/1571763622-29281-6-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Remove axidma multichannel mode supportRadhey Shyam Pandey2019-11-061-147/+8
| | | | | | | | | | | | | | | | | | | | | | | | The AXI DMA multichannel support is deprecated in the IP and it is no longer actively supported. For multichannel support, refer to the AXI multichannel direct memory access IP product guide(PG228) and MCDMA driver. So inline with it remove axidma multichannel support from from the driver. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571763622-29281-5-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Clear desc_pendingcount in xilinx_dma_resetNicholas Graumann2019-10-201-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whenever we reset the channel, we need to clear desc_pendingcount along with desc_submitcount. Otherwise when a new transaction is submitted, the irq coalesce level could be programmed to an incorrect value in the axidma case. This behavior can be observed when terminating pending transactions with xilinx_dma_terminate_all() and then submitting new transactions without releasing and requesting the channel. Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-8-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Print debug message when no free tx segmentsNicholas Graumann2019-10-201-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver should not run out of tx segments in normal operation. But, if the user attempts to prepare a transaction with a large sg list, the driver may not have enough free segments to accommodate the request. Log a message at the debug level to inform the user in case they are experiencing issues. Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-7-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Add callback_result supportNicholas Graumann2019-10-201-1/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | Take advantage of dmaengine_desc_get_callback_invoke which allows either a callback or callback_result to be specified. This can be useful when using the AXI DMA transfer unknown quantities of data where the residue contained in the result can be used to calculate the number of bytes transferred. Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-6-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Introduce xilinx_dma_get_residueNicholas Graumann2019-10-201-17/+54
| | | | | | | | | | | | | | | | | | | | Introduce a function that can calculate residues for IPs that support it: AXI DMA and CDMA. Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-5-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Remove residue from channel dataRadhey Shyam Pandey2019-10-201-4/+1
| | | | | | | | | | | | | | | | | | There is no use of storing channel data residue field. So clean it up. In tx_status simply pass calculated residue to dma_set_residue. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-4-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Merge get_callback and _invokeNicholas Graumann2019-10-201-4/+1
| | | | | | | | | | | | | | | | | | | | The dma api provides a single interface to get the appropriate callback and invoke it directly. Prefer using it. Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-3-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Remove desc_callback_valid checkRadhey Shyam Pandey2019-10-201-5/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | In descriptor cleanup the call to desc_callback_valid can be safely removed as both callback pointers i.e callback_result and callback are anyway checked in invoke(). There is no much benefit in having redundant checks. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Nicholas Graumann <nick.graumann@gmail.com> Reviewed-by: Appana Durga Kedareswara rao <appana.durga.rao@xilinx.com> Link: https://lore.kernel.org/r/1571150904-3988-2-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: Remove clk_get error message for probe deferRadhey Shyam Pandey2019-10-151-5/+14
| | | | | | | | | | | | | | | | | | | | | | In dma probe, the driver checks for devm_clk_get return and print error message in the failing case. However for -EPROBE_DEFER this message is confusing so avoid it. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Link: https://lore.kernel.org/r/1569495060-18117-5-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | dmaengine: xilinx_dma: use devm_platform_ioremap_resource()Radhey Shyam Pandey2019-10-151-3/+1
|/ | | | | | | | | | | | | Replace the chain of platform_get_resource() and devm_ioremap_resource() with devm_platform_ioremap_resource(). It simplifies the flow and there is no functional change. Fixes below cocinelle warning- WARNING: Use devm_platform_ioremap_resource for xdev -> regs Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Link: https://lore.kernel.org/r/1569495060-18117-4-git-send-email-radhey.shyam.pandey@xilinx.com Signed-off-by: Vinod Koul <vkoul@kernel.org>
* Merge tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2019-07-171-3/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: - Add support in dmaengine core to do device node checks for DT devices and update bunch of drivers to use that and remove open coding from drivers - New driver/driver support for new hardware, namely: - MediaTek UART APDMA - Freescale i.mx7ulp edma2 - Synopsys eDMA IP core version 0 - Allwinner H6 DMA - Updates to axi-dma and support for interleaved cyclic transfers - Greg's debugfs return value check removals on drivers - Updates to stm32-dma, hsu, dw, pl330, tegra drivers * tag 'dmaengine-5.3-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (68 commits) dmaengine: Revert "dmaengine: fsl-edma: add i.mx7ulp edma2 version support" dmaengine: at_xdmac: check for non-empty xfers_list before invoking callback Documentation: dmaengine: clean up description of dmatest usage dmaengine: tegra210-adma: remove PM_CLK dependency dmaengine: fsl-edma: add i.mx7ulp edma2 version support dt-bindings: dma: fsl-edma: add new i.mx7ulp-edma dmaengine: fsl-edma-common: version check for v2 instead dmaengine: fsl-edma-common: move dmamux register to another single function dmaengine: fsl-edma: add drvdata for fsl-edma dmaengine: Revert "dmaengine: fsl-edma: support little endian for edma driver" dmaengine: rcar-dmac: Reject zero-length slave DMA requests dmaengine: dw: Enable iDMA 32-bit on Intel Elkhart Lake dmaengine: dw-edma: fix semicolon.cocci warnings dmaengine: sh: usb-dmac: Use [] to denote a flexible array member dmaengine: dmatest: timeout value of -1 should specify infinite wait dmaengine: dw: Distinguish ->remove() between DW and iDMA 32-bit dmaengine: fsl-edma: support little endian for edma driver dmaengine: hsu: Revert "set HSU_CH_MTSR to memory width" dmagengine: pl330: add code to get reset property dt-bindings: pl330: document the optional resets property ...
| * dmaengine: xilinx_dma: Remove set but unused ‘tail_desc’Vinod Koul2019-05-221-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | We get a compiler warn about variable ‘tail_desc’ set but not used drivers/dma/xilinx/xilinx_dma.c:1102:42: warning: variable ‘tail_desc’ set but not used [-Wunused-but-set-variable] struct xilinx_dma_tx_descriptor *desc, *tail_desc; So remove it. Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 152Thomas Gleixner2019-05-301-5/+1
|/ | | | | | | | | | | | | | | | | | | | | Based on 1 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license as published by the free software foundation either version 2 of the license or at your option any later version extracted by the scancode license scanner the SPDX license identifier GPL-2.0-or-later has been chosen to replace the boilerplate/reference in 3029 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190527070032.746973796@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2019-03-141-70/+100
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: - dmatest updates for modularizing common struct and code - remove SG support for VDMA xilinx IP and updates to driver - Update to dw driver to support Intel iDMA controllers multi-block support - tegra updates for proper reporting of residue - Add Snow Ridge ioatdma device id and support for IOATDMA v3.4 - struct_size() usage and useless LIST_HEAD cleanups in subsystem. - qDMA controller driver for Layerscape SoCs - stm32-dma PM Runtime support - And usual updates to imx-sdma, sprd, Documentation, fsl-edma, bcm2835, qcom_hidma etc * tag 'dmaengine-5.1-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (81 commits) dmaengine: imx-sdma: fix consistent dma test failures dmaengine: imx-sdma: add a test for imx8mq multi sdma devices dmaengine: imx-sdma: add clock ratio 1:1 check dmaengine: dmatest: move test data alloc & free into functions dmaengine: dmatest: add short-hand `buf_size` var in dmatest_func() dmaengine: dmatest: wrap src & dst data into a struct dmaengine: ioatdma: support latency tolerance report (LTR) for v3.4 dmaengine: ioatdma: add descriptor pre-fetch support for v3.4 dmaengine: ioatdma: disable DCA enabling on IOATDMA v3.4 dmaengine: ioatdma: Add Snow Ridge ioatdma device id dmaengine: sprd: Change channel id to slave id for DMA cell specifier dt-bindings: dmaengine: sprd: Change channel id to slave id for DMA cell specifier dmaengine: mv_xor: Use correct device for DMA API Documentation :dmaengine: clarify DMA desc. pointer after submission Documentation: dmaengine: fix dmatest.rst warning dmaengine: k3dma: Add support for dma-channel-mask dmaengine: k3dma: Delete axi_config dmaengine: k3dma: Upgrade k3dma driver to support hisi_asp_dma hardware Documentation: bindings: dma: Add binding for dma-channel-mask Documentation: bindings: k3dma: Extend the k3dma driver binding to support hisi-asp ...
| * dmaengine: xilinx_dma: remove set but not used variable 'tail_segment'YueHaibing2019-01-201-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fixes gcc '-Wunused-but-set-variable' warning: drivers/dma/xilinx/xilinx_dma.c: In function 'xilinx_vdma_start_transfer': drivers/dma/xilinx/xilinx_dma.c:1104:33: warning: variable 'tail_segment' set but not used [-Wunused-but-set-variable] It not used since commit b8349172b400 ("dmaengine: xilinx_dma: Drop SG support for VDMA IP") Signed-off-by: YueHaibing <yuehaibing@huawei.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: Drop SG support for VDMA IPAndrea Merello2019-01-071-52/+32
| | | | | | | | | | | | | | | | | | | | | | | | xilinx_vdma_start_transfer() is used only for VDMA IP, still it contains conditional code on has_sg variable. has_sg is set only whenever the HW does support SG mode, that is never true for VDMA IP. This patch drops the never-taken branches. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: autodetect whether the HW supports scatter-gatherAndrea Merello2019-01-071-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AXIDMA and CDMA HW can be either direct-access or scatter-gather version. These are SW incompatible. The driver can handle both versions: a DT property was used to tell the driver whether to assume the HW is in scatter-gather mode. This patch makes the driver to autodetect this information. The DT property is not required anymore. No changes for VDMA. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: program hardware supported buffer lengthRadhey Shyam Pandey2019-01-071-4/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AXI-DMA IP supports configurable (c_sg_length_width) buffer length register width, hence read buffer length (xlnx,sg-length-width) DT property and ensure that driver doesn't program buffer length exceeding the supported limit. For VDMA and CDMA there is no change. Cc: Rob Herring <robh+dt@kernel.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: devicetree@vger.kernel.org Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> [rebase, reword] Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: in axidma slave_sg and dma_cyclic mode align split ↵Andrea Merello2019-01-071-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | descriptors Whenever a single or cyclic transaction is prepared, the driver could eventually split it over several SG descriptors in order to deal with the HW maximum transfer length. This could end up in DMA operations starting from a misaligned address. This seems fatal for the HW if DRE (Data Realignment Engine) is not enabled. This patch eventually adjusts the transfer size in order to make sure all operations start from an aligned address. Cc: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
| * dmaengine: xilinx_dma: commonize DMA copy size calculationAndrea Merello2019-01-071-8/+31
| | | | | | | | | | | | | | | | | | | | | | | | This patch removes a bit of duplicated code by introducing a new function that implements calculations for DMA copy size, and prepares for changes to the copy size calculation that will happen in following patches. Suggested-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* | cross-tree: phase out dma_zalloc_coherent()Luis Chamberlain2019-01-081-7/+7
|/ | | | | | | | | | | | | | | | | | | We already need to zero out memory for dma_alloc_coherent(), as such using dma_zalloc_coherent() is superflous. Phase it out. This change was generated with the following Coccinelle SmPL patch: @ replace_dma_zalloc_coherent @ expression dev, size, data, handle, flags; @@ -dma_zalloc_coherent(dev, size, handle, flags) +dma_alloc_coherent(dev, size, handle, flags) Suggested-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Luis Chamberlain <mcgrof@kernel.org> [hch: re-ran the script on the latest tree] Signed-off-by: Christoph Hellwig <hch@lst.de>
* dmaengine: xilinx_dma: Fix 64-bit simple CDMA transferRadhey Shyam Pandey2018-11-111-2/+4
| | | | | | | | | | | In AXI CDMA simple mode also pass MSB bits of source and destination address to xilinx_write function. This fixes simple CDMA operation mode using 64-bit addressing. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Introduce helper macro for preparing dma addressRadhey Shyam Pandey2018-11-111-0/+2
| | | | | | | | | | This patch introduces the xilinx_prep_dma_addr_t macro which prepares dma_addr_t from hardware buffer descriptor LSB and MSB fields. It will be used in simple dma 64-bit programming sequence. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Reviewed-by: Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Refactor axidma channel allocationRadhey Shyam Pandey2018-11-111-18/+18
| | | | | | | | In axidma alloc_chan_resources merge BD and cyclic BD allocation. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Enable VDMA S2MM vertical flip supportRadhey Shyam Pandey2018-06-291-0/+22
| | | | | | | | | | | Vertical flip state is exported in xilinx_vdma_config and depending on IP configuration(c_enable_vert_flip) vertical flip state is programmed in hardware. Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vkoul@kernel.org>
* dmaengine: xilinx_dma: Free BD consistent memoryKedareswara rao Appana2018-01-081-0/+5
| | | | | | | | | Free BD consistent memory while freeing the channel i.e in free_chan_resources. Signed-off-by: Radhey Shyam Pandey <radheys@xilinx.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Fix warning variable prev set but not usedKedareswara rao Appana2018-01-081-3/+1
| | | | | | | | | | This patch fixes the below sparse warning in the driver drivers/dma/xilinx/xilinx_dma.c: In function ‘xilinx_vdma_dma_prep_interleaved’: drivers/dma/xilinx/xilinx_dma.c:1614:43: warning: variable ‘prev’ set but not used [-Wunused-but-set-variable] struct xilinx_vdma_tx_segment *segment, *prev = NULL; Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: properly configure the SG mode bit in the driver for cdmaKedareswara rao Appana2018-01-081-0/+10
| | | | | | | | | | | | | If the hardware is configured for Scatter Gather(SG) mode, and hardware is idle, in the control register SG mode bit must be set to a 0 then back to 1 by the software, to force the CDMA SG engine to use a new value written to the CURDESC_PNTR register, failure to do so could result errors from the dmaengine. This patch updates the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Fix typosVinod Koul2017-12-181-3/+3
| | | | | | | | | | some typos is comments, so fix them up /s/enusres/ensures /s/descripotrs/descriptors /s/Submited/Submitted /s/pollling/polling Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Differentiate probe based on the ip typeKedareswara rao Appana2017-12-181-1/+6
| | | | | | | This patch updates the probe banner info based on the ip probed. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: fix style issues from checkpatchKedareswara rao Appana2017-12-181-1/+2
| | | | | | | | | | This patch fixes below. ERROR: open brace '{' following function definitions go on the next line +static int xilinx_dma_child_probe(struct xilinx_dma_device *xdev, + struct device_node *node) { Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Fix kernel doc warningsKedareswara rao Appana2017-12-181-13/+24
| | | | | | | | This patch fixes the kernel doc warnings in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Fix race condition in the driver for multiple ↵Kedareswara rao Appana2017-12-181-51/+84
| | | | | | | | | | | | | | | | | | | | descriptor scenario As per axi dmaengine spec the software must not move the tail pointer to a location that has not been updated (next descriptor field of the h/w descriptor should always point to a valid address). When user submits multiple descriptors on the recv side, with the current driver flow the last buffer descriptor next descriptor field points to a invalid location, resulting the invalid data or errors from the axidma dmaengine. This patch fixes this issue by creating a buffer descritpor chain during channel allocation itself and use those buffer descriptors for the subsequent dma operations. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaeninge: xilinx_dma: Fix bug in multiple frame stores scenario in vdmaKedareswara rao Appana2017-12-181-22/+19
| | | | | | | | | | | | | | | | | | | | | | | VDMA engine default frame buffer configuration is cirular mode. in this mode dmaengine continuously circles through h/w configured fstore frame buffers. When vdma h/w is configured for more than one frame. for example h/w is configured for n number of frames, user submits less than n number of frames and triggered the dmaengine using issue_pending API. since the h/w (or) driver default configuraiton is circular mode h/w tries to write/read from an invalid frame buffer resulting errors from the vdma dmaengine. This patch fixes this issue by enabling the park mode as default mode configuration for frame buffers in s/w, so that driver can handle all cases for "k" frames where n%k==0 (n is a multiple of k) by simply replicating the frame pointers. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* dmaengine: xilinx_dma: Check for channel idle state before submitting dma ↵Kedareswara rao Appana2017-12-181-38/+22
| | | | | | | | | | | | | | descriptor Add variable for checking channel idle state to ensure that dma descriptor is not submitted when dmaengine is in progress. This will avoid the polling for a bit in the status register to know dma state in the driver hot path. Reviewed-by: Jose Abreu <joabreu@synopsys.com> Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 06:07:43 +0100