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* Merge branch 'fix/edma' into fixesVinod Koul2016-04-161-38/+25
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| * dmaengine: edma: special case slot limit workaroundJohn Ogness2016-04-061-3/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently drivers are limited to 19 slots for cyclic transfers. However, if the DMA burst size is the same as the period size, the period size can be changed to the full buffer size and intermediate interrupts activated. Since intermediate interrupts will trigger for each burst and the burst size is the same as the period size, the driver will get interrupts each period as expected. This has the benefit of allowing the functionality of many more slots, but only uses 2 slots. This workaround is only active if more than 19 slots are needed and the burst size matches the period size. Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: John Ogness <john.ogness@linutronix.de> Signed-off-by: Sekhar Nori <nsekhar@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * dmaengine: edma: Remove dynamic TPTC power management featurePeter Ujfalusi2016-04-061-35/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The dynamic or on demand pm_runtime does not work correctly on am335x and am437x due to interference with hwmod. Fall back using the pm_runtime usage as it was in the old driver stack, meaning that at probe time call pm_runtime_enable() and pm_runtime_get_sync() for the TPTCs as well. Fixes: 1be5336bc7ba ("dmaengine: edma: New device tree binding") Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Reported-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge branch 'fix/xilinx' into fixesVinod Koul2016-04-161-1/+1
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| * | dmaengine: vdma: don't crash when bad channel is requestedFranck Jullien2016-04-051-1/+1
| |/ | | | | | | | | | | | | | | | | When client request a non existing channel from of_dma_xilinx_xlate we get a NULL pointer dereferencing. This patch fix this problem. Signed-off-by: Franck Jullien <franck.jullien@odyssee-systemes.fr> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge branch 'fix/omap' into fixesVinod Koul2016-04-161-9/+17
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| * | dmaengine: omap-dma: Do not suppress interrupts for memcpyPeter Ujfalusi2016-04-051-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | If the client queues up more transfers the driver will not able to move to the next transfer without knowing that the previous descriptor is completed. Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: omap-dma: Fix polled channel completion detection and handlingPeter Ujfalusi2016-04-051-6/+16
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When based on the CCR_ENABLE bit the channel is stopped we should not call omap_dma_callback(), only change the return value to DMA_COMPLETE. Client drivers will do the right thing to clean up the channel after the transfer has been completed. Check the CCR_ENABLE only if the channel is running and not paused since pause in sDMA means that the channel is stopped. This will fix one hard to reproduce race condition when the channel is terminated during transfer (affecting cyclic operation). Fixes: 1a7cf7b26f25 ("dmaengine: omap-dma: Handle cases when the channel is polled for completion") Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* | Merge branch 'fix/hsu' into fixesVinod Koul2016-04-162-5/+11
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| * | dmaengine: hsu: correct use of channel status registerAndy Shevchenko2016-04-042-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a typo in documentation regarding to descriptor empty bit (DESCE) which is set to 1 when descriptor is empty. Thus, status register at the end of a transfer usually returns all DESCE bits set and thus it will never be zero. Moreover, there are 2 bits (CDESC) that encode current descriptor, on which interrupt has been asserted. In case when we have few descriptors programmed we might have non-zero value. Remove DESCE and CDESC bits from DMA channel status register (HSU_CH_SR) when reading it. Fixes: 2b49e0c56741 ("dmaengine: append hsu DMA driver") Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: hsu: correct residue calculation of active descriptorAndy Shevchenko2016-04-041-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation") speeded up calculation of the queued descriptor but broke the initial residue value for active descriptor. In accordance with documentation the hardware descriptor is updated each time DMA transfered some bytes. It means we have to calculate a sum of lengths of non-submitted hardware descriptors and whatever current values in the hardware. Do this straightforward. Fixes: f0579c8ceaf1 ("dmaengine: hsu: speed up residue calculation") Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | dmaengine: hsu: set HSU_CH_MTSR to memory widthAndy Shevchenko2016-04-041-2/+2
| |/ | | | | | | | | | | | | | | HSU_CH_MTSR register should be programmed to a minimum size to transfer. This size on a memory side of the transfer. Program it accordingly. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* / dmaengine: dw: fix master selectionAndy Shevchenko2016-04-131-15/+19
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 895005202987 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") cleaned up the code to avoid usage of depricated slave_id member of generic slave configuration. Meanwhile it broke the master selection by removing important call to dwc_set_masters() in ->device_alloc_chan_resources() which copied masters from custom slave configuration to the internal channel structure. Everything works until now since there is no customized connection of DesignWare DMA IP to the bus, i.e. one bus and one or more masters are in use. The configurations where 2 masters are connected to the different masters are not working anymore. We are expecting one user of such configuration and need to select masters properly. Besides that it is obviously a performance regression since only one master is in use in multi-master configuration. Select masters in accordance with what user asked for. Keep this patch in a form more suitable for back porting. We are safe to take necessary data in ->device_alloc_chan_resources() because we don't support generic slave configuration embedded into custom one, and thus the only way to provide such is to use the parameter to a filter function which is called exactly before channel resource allocation. While here, replase BUG_ON to less noisy dev_warn() and prevent channel allocation in case of error. Fixes: 895005202987 ("dmaengine: dw: apply both HS interfaces and remove slave_id usage") Cc: stable@vger.kernel.org Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
* Merge tag 'asm-generic-4.6' of ↵Linus Torvalds2016-03-251-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic Pull asm-generic updates from Arnd Bergmann: "There are only three patches this time, most other changes to files in include/asm-generic tend to go through the tree of whoever depends on the change. Two patches are cleanups for stuff that is no longer needed, the main change is to adapt the generic version of BUG_ON() for CONFIG_BUG=n to make it behave consistently with BUG(). This avoids undefined behavior along with a number of warnings about that undefined behavior in randconfig builds when we keep going on after hitting a BUG_ON()" * tag 'asm-generic-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic: asm-generic: remove old nonatomic-io wrapper files asm-generic: default BUG_ON(x) to if(x)BUG() asm-generic: page.h: Remove useless get_user_page and free_user_page
| * asm-generic: remove old nonatomic-io wrapper filesArnd Bergmann2016-03-011-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The two header files got moved to include/linux, and most users were already converted, this changes the remaining drivers and removes the files. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Vinod Koul <vinod.koul@intel.com> Acked-by: Simon Horman <simon.horman@netronome.com> Acked-by: Yisen Zhuang <yisen.zhuang@huawei.com>
* | Merge tag 'armsoc-soc' of ↵Linus Torvalds2016-03-201-11/+28
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform updates from Arnd Bergmann: "Newly added support for additional SoCs: - Axis Artpec-6 SoC family - Allwinner A83T SoC - Mediatek MT7623 - NXP i.MX6QP SoC - ST Microelectronics stm32f469 microcontroller New features: - SMP support for Mediatek mt2701 - Big-endian support for NXP i.MX - DaVinci now uses the new DMA engine dma_slave_map - OMAP now uses the new DMA engine dma_slave_map - earlyprintk support for palmchip uart on mach-tango - delay timer support for orion Other: - Exynos PMU driver moved out to drivers/soc/ - Various smaller updates for Renesas, Xilinx, PXA, AT91, OMAP, uniphier" * tag 'armsoc-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits) ARM: uniphier: rework SMP code to support new System Bus binding ARM: uniphier: add missing of_node_put() ARM: at91: avoid defining CONFIG_* symbols in source code ARM: DRA7: hwmod: Add data for eDMA tpcc, tptc0, tptc1 ARM: imx: Make reset_control_ops const ARM: imx: Do L2 errata only if the L2 cache isn't enabled ARM: imx: select ARM_CPU_SUSPEND only for imx6 dmaengine: pxa_dma: fix the maximum requestor line ARM: alpine: select the Alpine MSI controller driver ARM: pxa: add the number of DMA requestor lines dmaengine: mmp-pdma: add number of requestors dma: mmp_pdma: Add the #dma-requests DT property documentation ARM: OMAP2+: Add rtc hwmod configuration for ti81xx ARM: s3c24xx: Avoid warning for inb/outb ARM: zynq: Move early printk virtual address to vmalloc area ARM: DRA7: hwmod: Add custom reset handler for PCIeSS ARM: SAMSUNG: Remove unused register offset definition ARM: EXYNOS: Cleanup header files inclusion drivers: soc: samsung: Enable COMPILE_TEST MAINTAINERS: Add maintainers entry for drivers/soc/samsung ...
| * | dmaengine: pxa_dma: fix the maximum requestor lineRobert Jarzmik2016-02-261-11/+28
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current number of requestor lines is limited to 31. This was an error of a previous commit, as this number is platform dependent, and is actually : - for pxa25x: 40 requestor lines - for pxa27x: 75 requestor lines - for pxa3xx: 100 requestor lines The previous testing did not reveal the faulty constant as on pxa[23]xx platforms, only camera, MSL and USB are above requestor 32, and in these only the camera has a driver using dma. Fixes: e87ffbdf0697 ("dmaengine: pxa_dma: fix the no-requestor case") Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr> Acked-by: Vinod Koul <vinod.koul@intel.com>
* | Merge tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dmaLinus Torvalds2016-03-1732-460/+1943
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull dmaengine updates from Vinod Koul: "This is smallish update with minor changes to core and new driver and usual updates. Nothing super exciting here.. - We have made slave address as physical to enable driver to do the mapping. - We now expose the maxburst for slave dma as new capability so clients can know this and program accordingly - addition of device synchronize callbacks on omap and edma. - pl330 updates to support DMAFLUSHP for Rockchip platforms. - Updates and improved sg handling in Xilinx VDMA driver. - New hidma qualcomm dma driver, though some bits are still in progress" * tag 'dmaengine-4.6-rc1' of git://git.infradead.org/users/vkoul/slave-dma: (40 commits) dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platforms dmaengine: add Qualcomm Technologies HIDMA channel driver dmaengine: add Qualcomm Technologies HIDMA management driver dmaengine: hidma: Add Device Tree binding dmaengine: qcom_bam_dma: move to qcom directory dmaengine: tegra: Move of_device_id table near to its user dmaengine: xilinx_vdma: Remove unnecessary variable initializations dmaengine: sirf: use __maybe_unused to hide pm functions dmaengine: rcar-dmac: clear pertinence number of channels dmaengine: sh: shdmac: don't open code of_device_get_match_data() dmaengine: tegra: don't open code of_device_get_match_data() dmaengine: qcom_bam_dma: Make driver work for BE dmaengine: sun4i: support module autoloading dma/mic_x100_dma: IS_ERR() vs PTR_ERR() typo dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop's dmaengine: xilinx_vdma: Simplify spin lock handling dmaengine: xilinx_vdma: Fix issues with non-parking mode dmaengine: xilinx_vdma: Improve SG engine handling dmaengine: pl330: fix to support the burst mode dmaengine: make slave address physical ...
| * \ Merge branch 'topic/xilinx' into for-linusVinod Koul2016-03-141-95/+109
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| | * | dmaengine: xilinx_vdma: Remove unnecessary variable initializationsKedareswara rao Appana2016-03-041-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes the unnecessary variable initializations in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: xilinx_vdma: Use readl_poll_timeout instead of do while loop'sKedareswara rao Appana2016-03-031-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is sometimes necessary to poll a memory-mapped register until its value satisfies some condition use convenience macros that do this instead of do while loop's. This patch updates the same in the driver. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: xilinx_vdma: Simplify spin lock handlingKedareswara rao Appana2016-03-031-17/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch simplifies the spin lock handling in the driver by moving locking out of xilinx_dma_start_transfer() API and xilinx_dma_update_completed_cookie() API. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: xilinx_vdma: Fix issues with non-parking modeKedareswara rao Appana2016-03-031-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes issues with the Non-parking mode(Cirular mode). With the existing driver in cirular mode if we submit frames less than h/w configured we simply end-up having misconfigured vdma h/w. This patch fixes this issue by configuring the frame count register. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: xilinx_vdma: Improve SG engine handlingKedareswara rao Appana2016-03-031-55/+72
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current driver allows user to queue up multiple segments on to a single transaction descriptor. User will submit this single desc and in the issue_pending() we decode multiple segments and submit to SG HW engine. We free up the allocated_desc when it is submitted to the HW. Existing code prevents the user to prepare multiple trasactions at same time as we are overwrite with the allocated_desc. The best utilization of HW SG engine would happen if we collate the pending list when we start dma this patch updates the same. Signed-off-by: Kedareswara rao Appana <appanad@xilinx.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/sh' into for-linusVinod Koul2016-03-143-5/+5
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| | * | dmaengine: rcar-dmac: clear pertinence number of channelsKuninori Morimoto2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DMACHCLR clears each channels, but its channel number is based on its SoC or IP. Current driver is using fixed 0x7fff (= for 15ch), it is not good match for Gen3 or Gen2 Audio DMAC. This patch fixes it Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: sh: shdmac: don't open code of_device_get_match_data()Wolfram Sang2016-03-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change will also make Coverity happy by avoiding a theoretical NULL pointer dereference; yet another reason is to use the above helper function to tighten the code and make it more readable. Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com> Acked-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: sh: Use ARCH_RENESASSimon Horman2016-02-081-3/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make use of ARCH_RENESAS in place of ARCH_SHMOBILE. This is part of an ongoing process to migrate from ARCH_SHMOBILE to ARCH_RENESAS the motivation for which being that RENESAS seems to be a more appropriate name than SHMOBILE for the majority of Renesas ARM based SoCs. Signed-off-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/qcom' into for-linusVinod Koul2016-03-1410-20/+1550
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| | * | dmaengine: add Qualcomm Technologies HIDMA channel driverSinan Kaya2016-03-113-0/+876
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for hidma engine. The driver consists of two logical blocks. The DMA engine interface and the low-level interface. The hardware only supports memcpy/memset and this driver only support memcpy interface. HW and driver doesn't support slave interface. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: add Qualcomm Technologies HIDMA management driverSinan Kaya2016-03-115-0/+649
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Qualcomm Technologies HIDMA device has been designed to support virtualization technology. The driver has been divided into two to follow the hardware design. 1. HIDMA Management driver 2. HIDMA Channel driver Each HIDMA HW consists of multiple channels. These channels share some set of common parameters. These parameters are initialized by the management driver during power up. Same management driver is used for monitoring the execution of the channels. Management driver can change the performance behavior dynamically such as bandwidth allocation and prioritization. The management driver is executed in host context and is the main management entity for all channels provided by the device. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: qcom_bam_dma: move to qcom directorySinan Kaya2016-03-115-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Creating a QCOM directory for all QCOM DMA source files. Signed-off-by: Sinan Kaya <okaya@codeaurora.org> Reviewed-by: Andy Gross <agross@codeaurora.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: qcom_bam_dma: Make driver work for BEAndy Gross2016-03-031-8/+11
| | |/ | | | | | | | | | | | | | | | | | | | | | This patch fixes the Qualcomm BAM dmaenging driver to work with big endian kernels. Signed-off-by: Andy Gross <andy.gross@linaro.org> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/pl330' into for-linusVinod Koul2016-03-142-28/+74
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| | * | dmaengine: pl330: fix to support the burst modeCaesar Wang2016-03-011-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the burst mode that will break DMA uart on SoCFPGA. In some cases, some SoCS didn't support the multi-burst even if the devices who use the pl330 claim support the maxburst. Fixes: commit 848e977 "dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmit" Reported-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> Tested-by: Dinh Nguyen <dinguyen@opensource.altera.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl330: add max burst for dmaengineShawn Lin2016-02-091-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add max burst capability for dmaengine and limit burst capability to one for PL330_QUIRK_BROKEN_NO_FLUSHP Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: core: expose max burst capability to clientsShawn Lin2016-02-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add max_burst to dma_get_slave_caps for clients to get the burst capability of slave dma controller. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl330: add quirk for broken no flushpAddy Ke2016-02-091-25/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch add "arm,pl330-broken-no-flushp" quirk to avoid execute DMAFLUSHP if Soc doesn't support it. Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> cc: Doug Anderson <dianders@chromium.org> cc: Heiko Stuebner <heiko@sntech.de> cc: Olof Johansson <olof@lixom.net> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: pl330: support burst mode for dev-to-mem and mem-to-dev transmitBoojin Kim2016-02-091-7/+13
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds to support burst mode for dev-to-mem and mem-to-dev transmit. Signed-off-by: Boojin Kim <boojin.kim@samsung.com> Signed-off-by: Addy Ke <addy.ke@rock-chips.com> Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> cc: Heiko Stuebner <heiko@sntech.de> cc: Doug Anderson <dianders@chromium.org> cc: Olof Johansson <olof@lixom.net> Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/omap' into for-linusVinod Koul2016-03-141-0/+8
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| | * | dmaengine: omap-dma: Implement device_synchronize callbackPeter Ujfalusi2016-02-221-0/+8
| | |/ | | | | | | | | | | | | | | | | | | We need the callback to support the dmaengine_terminate_sync(). Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/ioatdma' into for-linusVinod Koul2016-03-144-234/+108
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| | * | dmaengine: IOATDMA: revise channel reset workaround on CB3.3 platformsDave Jiang2016-03-112-36/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we unloaded the interrupts and reloaded in order to work around a channel reset bug that cleared the MSIX table. This approach just isn't practical when a reset needs to happen in the error handler that just happens to be running in interrupt context (bottom half). It looks like we can work around the hardware issue by just storing a shadow copy of the MSIX table and restore it after reset. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: IOATDMA: Allocate DMA descriptor ring in contig DMA memoryDave Jiang2016-02-154-34/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Future IOATDMA hardware will take advantage of descriptors residing in contiguous memory. Setting the descriptor ring in max config DMA memory of 2MB. Each channel will need 2 of these chunks. This should provide 64k of 64B descriptors. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: IOATDMA: Removing descriptor ring reshapeDave Jiang2016-02-153-157/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moving to contingous memory backed descriptor rings. This makes is really difficult and complex to do reshape. Going to remove this as I don't think we need to do it anymore. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: IOATDMA: Convert pci_pool_* to dma_pool_*Dave Jiang2016-02-153-15/+15
| | |/ | | | | | | | | | | | | | | | | | | | | | Converting old pci_pool_* calls to "new" dma_pool_* to make everything uniform. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/idma' into for-linusVinod Koul2016-03-142-1/+4
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| | * | dmaengine: idma64: fix typo in WR_ISSUE_THD(x)Andy Shevchenko2016-02-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a typo in the definition of IDMA64C_CFGH_WR_ISSUE_THD(x). Fix it by swapping characters. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| | * | dmaengine: idma64: clear LLP_[SD]_EN bits in last descriptorAndy Shevchenko2016-02-151-0/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | The datasheet requires that the user must clear LLP_[SD]_EN bits whenever LLP.LOC is zero, i.e. in the last descriptor of a multi-block chain. Make the driver do this. Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Vinod Koul <vinod.koul@intel.com>
| * | Merge branch 'topic/edma' into for-linusVinod Koul2016-03-141-27/+36
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