| Commit message (Expand) | Author | Age | Files | Lines |
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| * | EDAC/i10nm: Add Intel Sapphire Rapids server support | Qiuxu Zhuo | 2020-11-19 | 1 | -9/+25 |
| * | EDAC/i10nm: Use readl() to access MMIO registers | Qiuxu Zhuo | 2020-11-19 | 1 | -4/+7 |
| * | EDAC, {skx,i10nm}: Use CPU stepping macro to pass configurations | Qiuxu Zhuo | 2020-06-15 | 1 | -7/+5 |
| *-. | Merge branches 'edac-i10nm' and 'edac-misc' into edac-updates-for-5.8 | Borislav Petkov | 2020-06-01 | 1 | -5/+24 |
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| | | * | EDAC/skx: Use the mcmtr register to retrieve close_pg/bank_xor_enable | Qiuxu Zhuo | 2020-05-20 | 1 | -1/+1 |
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| | * | EDAC/i10nm: Update driver to support different bus number config register off... | Qiuxu Zhuo | 2020-04-27 | 1 | -4/+14 |
| | * | EDAC, {skx,i10nm}: Make some configurations CPU model specific | Qiuxu Zhuo | 2020-04-27 | 1 | -4/+13 |
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| * | EDAC: Convert to new X86 CPU match macros | Thomas Gleixner | 2020-03-24 | 1 | -4/+4 |
| * | EDAC: Replace EDAC_DIMM_PTR() macro with edac_get_dimm() function | Robert Richter | 2019-11-09 | 1 | -2/+1 |
| * | x86/intel: Aggregate microserver naming | Peter Zijlstra | 2019-08-28 | 1 | -2/+2 |
| * | EDAC, skx, i10nm: Fix source ID register offset | Qiuxu Zhuo | 2019-06-26 | 1 | -1/+1 |
| * | EDAC, i10nm: Check ECC enabling status per channel | Qiuxu Zhuo | 2019-06-26 | 1 | -3/+3 |
| * | EDAC, i10nm: Add Intel additional Ice-Lake support | Qiuxu Zhuo | 2019-06-20 | 1 | -0/+2 |
| * | EDAC, skx, i10nm: Make skx_common.c a pure library | Qiuxu Zhuo | 2019-03-23 | 1 | -2/+50 |
| * | EDAC, i10nm: Add a driver for Intel 10nm server processors | Qiuxu Zhuo | 2019-02-02 | 1 | -0/+275 |
