linux - linux

	Commit message (Expand)	Author	Age	Files	Lines
*	fpga: zynq: Remove clk_get error message for probe defer	Shubhrajyoti Datta	2020-03-31	1	-1/+2
*	fpga: Remove dev_err() usage after platform_get_irq()	Stephen Boyd	2019-10-05	1	-3/+1
*	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 285	Thomas Gleixner	2019-06-05	1	-9/+1
*	zynq-fpga: Only route PR via PCAP when required	Mike Looijmans	2018-11-11	1	-0/+4
*	fpga: mgr: add devm_fpga_mgr_create	Alan Tull	2018-10-16	1	-3/+2
*	fpga: manager: change api, don't use drvdata	Alan Tull	2018-05-25	1	-3/+11
*	fpga: zynq: Add support for encrypted bitstreams	Moritz Fischer	2017-03-17	1	-3/+25
*	fpga zynq: Use the scatterlist interface	Jason Gunthorpe	2017-02-10	1	-39/+135
*	fpga zynq: Check the bitstream for validity	Jason Gunthorpe	2017-02-10	1	-0/+21
*	fpga zynq: Check for errors after completing DMA	Jason Gunthorpe	2017-02-10	1	-22/+32
*	fpga zynq: Fix incorrect ISR state on bootup	Jason Gunthorpe	2016-11-29	1	-7/+10
*	fpga zynq: Remove priv->dev	Jason Gunthorpe	2016-11-29	1	-11/+8
*	fpga zynq: Add missing \n to messages	Jason Gunthorpe	2016-11-29	1	-11/+11
*	fpga-mgr: add fpga image information struct	Alan Tull	2016-11-10	1	-4/+6
*	fpga: zynq-fpga: Fix issue with drvdata being overwritten.	Moritz Fischer	2015-10-24	1	-3/+4
*	fpga: zynq-fpga: Change fw format to handle bin instead of bit.	Moritz Fischer	2015-10-24	1	-22/+2
*	fpga: zynq-fpga: Fix unbalanced clock handling	Moritz Fischer	2015-10-24	1	-2/+2
*	fpga manager: Adding FPGA Manager support for Xilinx Zynq 7000	Moritz Fischer	2015-10-18	1	-0/+533