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path: root/drivers/gpu/drm/gma500/intel_bios.c (unfollow)
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2018-07-27drm/i915/guc: Avoid wasting memory on incorrect GuC pin biasJakub Bartmiński1-29/+20
2018-07-27drm/i915: Remove superfluous GEN8_LR_CONTEXT_ALIGNChris Wilson2-3/+1
2018-07-27drm/i915: Eliminate use of PAGE_SIZE as a virtual alignmentChris Wilson4-7/+6
2018-07-26drm/i915/selftests: Exercise resetting in the middle of a wait-on-fenceChris Wilson1-8/+77
2018-07-26drm/i915/selftests: Use a full emulation of a user ppgtt contextChris Wilson1-4/+12
2018-07-26drm/i915: Don't disable the GPU for older gen on wedgingChris Wilson1-1/+2
2018-07-26drm/i915: Restore sane defaults for KMS on GEM error loadChris Wilson1-1/+10
2018-07-26drm/i915: Protect guc_fini_wq() against module load abortChris Wilson1-5/+7
2018-07-26drm/i915: Mark up object tiling-and-stride getters as constChris Wilson2-7/+7
2018-07-26drm/i915: Avoid computing tile_row_size() for untiled objectsChris Wilson1-1/+1
2018-07-26drm/i915/mst: Continue state updates even if AUX writes fail.Dhinakaran Pandiyan1-4/+1
2018-07-26drm/i915/mst: Do not retrain new linksDhinakaran Pandiyan1-1/+3
2018-07-25drm/i915/icl: toggle PHY clock gating around link trainingPaulo Zanoni4-0/+91
2018-07-25drm/i915/icl: program MG_DP_MODEPaulo Zanoni4-0/+84
2018-07-25drm/i915/icl: Update FIA supported lane count for hpd.Animesh Manna2-1/+35
2018-07-25drm/i915/icl: store the port type for TC portsPaulo Zanoni3-2/+46
2018-07-25drm/i915/icl: implement icl_digital_port_connected()Paulo Zanoni2-1/+62
2018-07-25drm/i915/dp: Improve clock recovery loop limit commentNathan Ciobanu1-4/+6
2018-07-25drm/i915: Skip repeated calls to i915_gem_set_wedged()Chris Wilson1-2/+3
2018-07-25drm/i915/icl: Implement voltage swing programming sequence for MG PHY DDIManasi Navare1-6/+129
2018-07-25drm/i915/icl: Add remaining registers and bitfields for MG PHY DDIManasi Navare1-113/+157
2018-07-24drm/i915: Show stack (by WARN) for hitting forcewake errorsChris Wilson1-4/+14
2018-07-24drm/i915: Pull unpin map into vma releaseChris Wilson10-40/+24
2018-07-24drm/i915/dp: Refactor max_vswing_tries variableNathan Ciobanu1-4/+4
2018-07-24drm/i915/dp: Limit link training clock recovery loopNathan Ciobanu1-2/+15
2018-07-24drm/i915/kvmgt: Fix compilation errorMichał Winiarski1-6/+0
2018-07-21drm/i915/dsc: Add missing _MMIO() from PPS registersAnusha Srivatsa1-38/+38
2018-07-20drm/i915: Fix psr sink status report.Rodrigo Vivi1-2/+11
2018-07-20drm/i915: Remove unused "ret" variable.Rodrigo Vivi1-3/+2
2018-07-20drm/i915: Only force GGTT coherency w/a on required chipsetsChris Wilson5-0/+41
2018-07-20drm/i915: Suppress assertion for i915_ggtt_disable_gucChris Wilson1-0/+4
2018-07-20drm/i915/icl: compute the TBT PLL registersPaulo Zanoni1-1/+21
2018-07-19drm/i915: Fix assert_plane() warning on bootup with external displayAzhar Shaikh1-2/+59
2018-07-19drm/amdgpu: clean up UVD instance handling v2Christian König2-67/+64
2018-07-19drm/amdgpu: remove superflous UVD encode entityChristian König3-27/+0
2018-07-19drm/amdgpu/display: Replace CONFIG_DRM_AMD_DC_DCN1_0 with CONFIG_X86Michel Dänzer26-64/+56
2018-07-19drm/amd/powerplay: fixed uninitialized valueEvan Quan1-1/+1
2018-07-19drm/amdgpu/powerplay: use irq source defines for smu7 sourcesAlex Deucher1-3/+4
2018-07-19drm/i915/gtt: Full ppgtt everywhere, no excusesChris Wilson1-6/+0
2018-07-19drm/i915/gtt: Enable full-ppgtt by default everywhereChris Wilson1-6/+4
2018-07-19drm/i915: Update DRIVER_DATE to 20180719Rodrigo Vivi1-2/+2
2018-07-19drm/i915: Remove intel_panel_detect()Ville Syrjälä4-26/+0
2018-07-19drm/i915: Assume eDP is always connectedVille Syrjälä1-9/+2
2018-07-19drm/i915: Nuke the LVDS lid notifierVille Syrjälä3-152/+2
2018-07-19drm/i915/execlists: Move the assertion we have the rpm wakeref downChris Wilson1-14/+11
2018-07-19drm/i915: Handle recursive shrinker for vma->last_active allocationChris Wilson1-0/+8
2018-07-19drm/i915/guc: Keep guc submission permanently engagedChris Wilson3-16/+31
2018-07-19drm/nouveau/kms/nv50-: allocate push buffers in vidmem on pascalBen Skeggs1-2/+27
2018-07-19i915/dp/dsc: Add Rate Control Range Parameter RegistersAnusha Srivatsa1-0/+104
2018-07-19i915/dp/dsc: Add Rate Control Buffer Threshold RegistersAnusha Srivatsa1-0/+51
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