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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
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* drm/i915: fix hsw uncached pteDaniel Vetter2012-08-171-0/+1
* drm/i915: fix up PCH backlight #define mixupDaniel Vetter2012-07-201-1/+1
* drm/i915: Add comments to explain the BSD tail write workaroundChris Wilson2012-07-201-4/+4
* drm/i915/context: Add missing IVB context sizesBen Widawsky2012-07-201-1/+5
* drm/i915/context/: s/CTX/CXTBen Widawsky2012-07-201-9/+9
* drm/i915: program FDI_RX TP and FDI delaysEugeni Dodonov2012-07-051-0/+3
* drm/i915: adjust framebuffer base address on gen4+Daniel Vetter2012-07-051-1/+1
* drm/i915: introduce crtc->dspaddr_offsetDaniel Vetter2012-07-051-0/+1
* drm/i915: fix PIPE_DDI_PORT_MASKPaulo Zanoni2012-07-051-1/+1
* drm/i915: enable RC6 workaround on HaswellEugeni Dodonov2012-07-051-0/+5
* drm/i915: add RPS configuration for HaswellEugeni Dodonov2012-07-051-0/+1
* drm/i915: support Haswell force wakingEugeni Dodonov2012-07-031-0/+1
* drm/i915: Implement w/a for sporadic read failures on waking from rc6Chris Wilson2012-07-031-0/+4
* drm/i915: fix PIPE_WM_LINETIME definitionPaulo Zanoni2012-06-281-1/+1
* Merge tag 'v3.5-rc4' into drm-intel-next-queuedDaniel Vetter2012-06-251-3/+40
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| * drm/i915: pch_irq_handler -> {ibx, cpt}_irq_handlerAdam Jackson2012-06-061-3/+32
| * drm/i915: fix up ivb plane 3 pageflipsDaniel Vetter2012-06-051-0/+8
* | drm/i915: enable display messages to GT on ValleyViewJesse Barnes2012-06-201-2/+2
* | drm/i915: add HDMI and DP port enumeration on ValleyViewJesse Barnes2012-06-201-1/+0
* | drm/i915: Enable DP panel power sequencing for ValleyViewShobhit Kumar2012-06-201-0/+13
* | drm/i915: ValleyView mode setting limits and PLL functionsJesse Barnes2012-06-201-0/+1
* | drm/i915: add L3 bank clock gating disable on VLVJesse Barnes2012-06-181-0/+3
* | drm/i915: add TDL unit clock gating disable for VLVJesse Barnes2012-06-181-0/+1
* | drm/i915: disable RCBP and VDS unit clock gating on SNB and VLVJesse Barnes2012-06-181-0/+1
* | drm/i915: PIPE_CONTROL_TLB_INVALIDATEBen Widawsky2012-06-141-0/+1
* | drm/i915: Ivybridge MI_ARB_ON_OFF context w/aBen Widawsky2012-06-141-0/+3
* | drm/i915: CXT_SIZE register offsets addedBen Widawsky2012-06-141-0/+21
* | drm/i915: clear up backlight #define confusion on gen4+Daniel Vetter2012-06-121-20/+35
* | drm/i915: pnv has a backlight polarity control bit, tooDaniel Vetter2012-06-121-0/+2
* | drm/i915: remap l3 on hw initBen Widawsky2012-05-311-0/+3
* | drm/i915: Dynamic Parity Detection handlingBen Widawsky2012-05-311-0/+17
* | drm/i915: explicitly disable the DIPs we're not usingPaulo Zanoni2012-05-301-0/+6
* | drm/i915: SDVO hotplug have different interrupt status bits for i915/i965/g4xChris Wilson2012-05-211-3/+8
* | drm/i915: Inspect the right status bits for DP/HDMI hotplug on gen4Chris Wilson2012-05-211-6/+15
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* drm/i915: implement hsw_write_infoframePaulo Zanoni2012-05-201-0/+4
* drm/i915: add new Haswell DIP controls registersEugeni Dodonov2012-05-191-0/+36
* drm/i915: set the DIP port on ibx_write_infoframePaulo Zanoni2012-05-081-0/+1
* drm/i915: mask the video DIP frequency when changing itPaulo Zanoni2012-05-081-0/+1
* drm/i915: mask the video DIP port selectPaulo Zanoni2012-05-081-0/+1
* drm/i915: DSL_LINEMASK is 12 bits only on gen2Paulo Zanoni2012-05-081-1/+2
* drm/i915: Support pageflipping interrupts for all 3-pipes on IVBChris Wilson2012-05-061-2/+5
* drm/i915: also reset the media engine on gen4/5Daniel Vetter2012-05-051-0/+1
* drm/i915: use the new masked bit macro some moreDaniel Vetter2012-05-031-2/+0
* drm/i915: create macros to handle masked bitsDaniel Vetter2012-05-031-5/+3
* drm/i915: manage PCH PLLs separately from pipesJesse Barnes2012-05-031-3/+3
* drm/i915: [GEN7] Use HW scheduler for fixed function shadersBen Widawsky2012-04-181-0/+15
* drm/i915: Replace open coded MI_BATCH_GTTChris Wilson2012-04-181-0/+1
* drm/i915: Mask reserved bits in display/sprite address registersArmin Reese2012-04-171-0/+7
* drm/i915: add WRPLL divider programming bitsEugeni Dodonov2012-04-171-0/+4
* drm/i915: add definition of LPT FDI port width registersEugeni Dodonov2012-04-171-0/+3
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