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path: root/drivers/gpu/drm/i915/i915_reg.h (follow)
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* Revert "drm/i915: Mask reserved bits in display/sprite address registers"Daniel Vetter2014-01-241-2/+0
* drm/i915: VLV2 - Fix hotplug detect bitsTodd Previte2014-01-231-3/+7
* drm/i915: g4x/vlv: fix dp aux interrupt maskImre Deak2014-01-221-1/+2
* drm/i915/vlv: Add drpc debugfs support for valleyviewDeepak S2014-01-101-0/+2
* drm/i915: remove unused WM definesImre Deak2013-12-171-36/+0
* drm/i915: Add IVB DDB partitioning controlVille Syrjälä2013-12-171-0/+2
* drm/i915: Reorder/respace MI instruction definitionBen Widawsky2013-12-171-26/+26
* drm/i915/bdw: Implement ff workaroundsBen Widawsky2013-12-131-0/+1
* drm/i915/bdw: Force all Data Cache Data Port access to be Non-CoherentBen Widawsky2013-12-131-0/+4
* drm/i915: Use FLISDSI interface for band gap resetShobhit Kumar2013-12-111-0/+1
* drm/i915: Record BB_ADDR for every ringVille Syrjälä2013-12-111-1/+2
* drm/i915: Fix bogus FBC1 definesVille Syrjälä2013-12-041-2/+2
* drm/i915/vlv: use parallel context restore when coming out of RC6Jesse Barnes2013-11-281-0/+1
* drm/i915: Fix GT wake FIFO free entries for VLVVille Syrjälä2013-11-281-1/+2
* drm/i915: Report all GTFIFODBG errorsVille Syrjälä2013-11-281-1/+4
* drm/i915: Enable pipe gamma for spritesVille Syrjälä2013-11-211-1/+1
* drm/i915: Emit SRM after the MSG_FBC_REND_STATE LRIVille Syrjälä2013-11-211-0/+1
* drm/i915: dp aux irq support for g4x/vlvDaniel Vetter2013-11-181-0/+4
* Merge branch 'backlight-rework' into drm-intel-next-queuedDaniel Vetter2013-11-151-2/+154
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| * Merge tag 'bdw-stage1-2013-11-08-v2' of git://people.freedesktop.org/~danvet/...Dave Airlie2013-11-101-2/+121
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| | * drm/i915: Wire up cpu fifo underrun reporting support for bdwDaniel Vetter2013-11-081-1/+1
| | * drm/i915: Wire up port A aux channelDaniel Vetter2013-11-081-1/+2
| | * drm/i915: Fix up the bdw pipe interrupt enable listsDaniel Vetter2013-11-081-5/+4
| | * drm/i915: Optimize pipe irq handling on bdwDaniel Vetter2013-11-081-4/+1
| | * drm/i915/bdw: WaSingleSubspanDispatchOnAALinesAndPointsBen Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: conservative SBE VUE cache modeBen Widawsky2013-11-081-0/+2
| | * drm/i915/bdw: Limit SDE poly depth FIFO to 2Ben Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: Sampler power bypass disableBen Widawsky2013-11-081-0/+1
| | * ddrm/i915/bdw: Disable centroid pixel perf optimizationBen Widawsky2013-11-081-0/+3
| | * drm/i915/bdw: BWGTLB clock gate disableBen Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: Implement edp PSR workaroundsBen Widawsky2013-11-081-0/+6
| | * drm/i915/bdw: Support eDP PSRBen Widawsky2013-11-081-2/+2
| | * drm/i915/bdw: Use The GT mailbox for IPS enable/disableBen Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: Add Broadwell display FIFO limitsVille Syrjälä2013-11-081-0/+1
| | * drm/i915/bdw: add support for BDW DP voltage swings and pre-emphasisPaulo Zanoni2013-11-081-0/+11
| | * drm/i915/bdw: get the correct LCPLL frequency on BroadwellPaulo Zanoni2013-11-081-0/+3
| | * drm/i915/bdw: Broadwell has PIPEMISCPaulo Zanoni2013-11-081-0/+12
| | * drm/i915/bdw: Implement PPGTT enableBen Widawsky2013-11-081-0/+3
| | * drm/i915/bdw: Support BDW cachingBen Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: dispatch updates (64b related)Ben Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: Implement interrupt changesBen Widawsky2013-11-081-0/+68
| | * drm/i915/bdw: display stuffBen Widawsky2013-11-081-0/+1
| | * drm/i915/bdw: HW context supportBen Widawsky2013-11-081-0/+3
| | * drm/i915/bdw: Swizzling supportBen Widawsky2013-11-081-0/+2
| * | drm/i915/vlv: use per-pipe backlight controls v2Jesse Barnes2013-11-061-0/+15
| * | drm/i915/vlv: enable HDA display audio for Valleyview2Mengdong Lin2013-11-051-0/+18
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* | drm/i915/vlv: Make the vlv_dpio_read/vlv_dpio_write more PHY centricChon Ming Lee2013-11-111-0/+3
* | drm/i915/vlv: Rename VLV DPIO register to be more structure to match configdb...Chon Ming Lee2013-11-081-101/+90
* | drm/i915/vlv: modeset_global_* for VLV v7Jesse Barnes2013-11-051-0/+9
* | drm/i915: add bunit read/write routinesJesse Barnes2013-11-051-0/+1
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