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* Merge tag 'imx-drm-fixes-2015-03-31' of ↵Dave Airlie2015-04-081-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.pengutronix.de/git/pza/linux into drm-next imx-drm limit fixes Fix IPU IC downscaler to its hardware limitation of 4:1 and the IPU DI pixel clock divider integer part to 8-bit. * tag 'imx-drm-fixes-2015-03-31' of git://git.pengutronix.de/git/pza/linux: gpu: ipu-v3: turns out the IPU can only downsize 4:1 gpu: ipu-v3: limit pixel clock divider to 8-bits drm/radeon: programm the VCE fw BAR as well drm/radeon: always dump the ring content if it's available radeon: Do not directly dereference pointers to BIOS area. drm/radeon/dpm: fix 120hz handling harder
| * drm/radeon: programm the VCE fw BAR as wellChristian König2015-03-271-0/+1
| | | | | | | | | | | | | | Otherwise the VCE firmware needs to be in the first 256MB of VRAM. Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* | drm/radeon: add get_allowed_info_register for CIKAlex Deucher2015-03-191-0/+2
|/ | | | | | | Registers that can be fetched from the info ioctl. Tested-by: Marek Olšák <marek.olsak@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: enable SRBM timeout interrupt on CIK v2Leo Liu2015-02-251-0/+4
| | | | | | | v2: disable it on suspend Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Assign VMID to PASID for IH in non-HWS modeBen Goz2014-12-171-0/+2
| | | | | | | | | | | | | This patch fixes a bug in kgd_set_pasid_vmid_mapping(), where the function only updated the ATC registers (IOMMU) with the new VMID <--> PASID mapping, but didn't update the IH (Interrupt) registers. The bug only occurs when using non-HWS mode. In HWS mode, the CP automatically does the VMID <--> PASID mapping. Signed-off-by: Ben Goz <ben.goz@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fix typo in new fan control registers for SI/CIAlex Deucher2014-12-031-4/+4
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add smc fan control for CI (v2)Alex Deucher2014-11-201-2/+38
| | | | | | | | | | | | | Enable smc fan control for CI boards. Should reduce the fan noise on systems with a higher default fan profile. v2: disable by default, add additional fan setup, rpm control bug: https://bugs.freedesktop.org/show_bug.cgi?id=73338 Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Add radeon <--> amdkfd interfaceOded Gabbay2014-07-151-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the interface between the radeon driver and the amdkfd driver. The interface implementation is contained in radeon_kfd.c and radeon_kfd.h. The interface itself is represented by a pointer to struct kfd_dev. The pointer is located inside radeon_device structure. All the register accesses that amdkfd need are done using this interface. This allows us to avoid direct register accesses in amdkfd proper, while also avoiding locking between amdkfd and radeon. The single exception is the doorbells that are used in both of the drivers. However, because they are located in separate pci bar pages, the danger of sharing registers between the drivers is minimal. Having said that, we are planning to move the doorbells as well to radeon. v3: Add interface for sa manager init and fini. The init function will allocate a buffer on system memory and pin it to the GART address space via the radeon sa manager. All mappings of buffers to GART address space are done via the radeon sa manager. The interface of allocate memory will use the radeon sa manager to sub allocate from the single buffer that was allocated during the init function. Change lower_32/upper_32 calls to use linux macros Add documentation for the interface v4: Change ptr field type in kgd_mem from uint32_t* to void* to match to type that is returned by radeon_sa_bo_cpu_addr v5: Change format of mqd structure to work with latest KV firmware Add support for AQL queues creation to enable working with open-source HSA runtime. Move generic kfd-->kgd interface and other generic kgd definitions to a generic header file that will be used by AMD's radeon and amdgpu drivers Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
* drm/radeon: reduce number of free VMIDs and pipes in KVOded Gabbay2014-01-161-0/+2
| | | | | | | | | | | | | | To support HSA on KV, we need to limit the number of vmids and pipes that are available for radeon's use with KV. This patch reserves VMIDs 8-15 for amdkfd (so radeon can only use VMIDs 0-7) and also makes radeon thinks that KV has only a single MEC with a single pipe in it v3: Use define for static vmid allocation in radeon Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Oded Gabbay <oded.gabbay@amd.com>
* drm/radeon/cik: fix typo in EOP packetAlex Deucher2014-07-021-1/+1
| | | | | | | | Volatile bit was in the wrong location. This bit is not used at the moment. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* Merge commit '9e9a928eed8796a0a1aaed7e0b676db86ba84594' into drm-nextDave Airlie2014-06-051-0/+9
|\ | | | | | | | | | | | | | | | | | | | | | | | | Merge drm-fixes into drm-next. Both i915 and radeon need this done for later patches. Conflicts: drivers/gpu/drm/drm_crtc_helper.c drivers/gpu/drm/i915/i915_drv.h drivers/gpu/drm/i915/i915_gem.c drivers/gpu/drm/i915/i915_gem_execbuffer.c drivers/gpu/drm/i915/i915_gem_gtt.c
| * drm/radeon: use pflip irq on R600+ v2Christian König2014-05-011-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing the update pending bit directly after issuing an update is nonsense cause depending on the pixel clock the CRTC needs a bit of time to execute the flip even when we are in the VBLANK period. This is just a non invasive patch to solve the problem at hand, a more complete and cleaner solution should follow in the next merge window. Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=76564 v2: fix source IDs for CRTC2-6 Signed-off-by: Christian König <christian.koenig@amd.com> Cc: stable@vger.kernel.org
* | drm/radeon: add proper support for RADEON_VM_BLOCK_SIZE v2Christian König2014-06-021-0/+1
|/ | | | | | | | | | This patch makes it possible to decide how many address bits are spend on the page directory vs the page tables. v2: remove unintended change Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support for vce 2.0 clock gatingAlex Deucher2014-02-181-0/+10
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: fill in set_vce_clocks for CIK asicsAlex Deucher2014-02-181-0/+6
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: initial VCE support v4Christian König2014-02-181-0/+33
| | | | | | | | | | | Only VCE 2.0 support so far. v2: squashing multiple patches into this one v3: add IRQ support for CIK, major cleanups, basic code documentation v4: remove HAINAN from chipset list Signed-off-by: Christian König <christian.koenig@amd.com>
* drm/radeon: implement pci config reset for CIK (v3)Alex Deucher2014-01-091-0/+11
| | | | | | | | | | | pci config reset is a low level reset that resets the entire chip from the bus interface. It can be more reliable if soft reset fails. v2: fix rebase v3: hide behind module parameter Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update rb setup for hawaiiAlex Deucher2013-11-081-1/+3
| | | | | | | The formula needs to be adjusted since there are 4 RBs per SH rather than 2 as on previous asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update cik_tiling_mode_table_init() for hawaiiAlex Deucher2013-11-081-0/+2
| | | | | | | Hawaii uses a different tiling configuration. Add support for it. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: minor updates to cik.c for hawaiiAlex Deucher2013-11-081-0/+1
| | | | | | | Skip programming a register that was removed and adjust the mask of the VM client status. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update cik_gpu_init() for hawaiiAlex Deucher2013-11-081-0/+1
| | | | | | | This adds the hawaii asic specific configuration details. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: implement blit copy callback for CIKAlex Deucher2013-11-011-0/+62
| | | | | | | Uses the CP ring rather than the DMA ring. Useful for debugging and benchmarking. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Add support for programming the FMT blocksAlex Deucher2013-11-011-0/+33
| | | | | | | | | | | | The FMT blocks control how data is sent from the backend of the display pipe to to monitor. Proper set up of the FMT blocks are required for 30bpp formats. Additionally, dithering can be enabled on for better display with 18 and 24bpp displays. The exception is LVDS/eDP which atom takes care of in the SelectCRTC_Source table. For now just enable truncation until we test dithering more. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update line buffer allocation for dce8Alex Deucher2013-08-301-0/+4
| | | | | | | | | | | | | We need to allocate line buffer to each display when setting up the watermarks. Failure to do so can lead to a blank screen. This fixes blank screen problems on dce8 asics. Based on an initial fix from: Jay Cornwall <jay.cornwall@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org
* drm/radeon: restructure cg/pg on cik (v2)Alex Deucher2013-08-301-0/+1
| | | | | | | | | | | - use new cg/pg flags for finer grained clock and powergating control - restructure the cg/pg code so it can be called from other components such as dpm v2: fix build breakage from rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add debugfs support for KB/KVAlex Deucher2013-08-301-0/+4
| | | | | | | This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dpm: add debugfs support for CIAlex Deucher2013-08-301-0/+12
| | | | | | This allows you to look at the current DPM state via debugfs. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add dpm support for CI dGPUs (v2)Alex Deucher2013-08-301-1/+258
| | | | | | | | | | | | | | | This adds dpm support for btc asics. This includes: - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen switching Set radeon.dpm=1 to enable. v2: remove unused radeon_atombios.c changes, make missing smc ucode non-fatal Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/kms: add dpm support for KB/KVAlex Deucher2013-08-301-0/+72
| | | | | | | | | | | | This adds dpm support for KB/KV asics. This includes: - dynamic engine clock scaling - dynamic voltage scaling - power containment - shader power scaling Set radeon.dpm=1 to enable. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add get_temperature() callbacks for CIK (v2)Alex Deucher2013-08-301-0/+8
| | | | | | | | | This added support for the on-chip thermal sensors on CIK asics. v2: fix register offset. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add rlc helpers for DPMAlex Deucher2013-08-301-0/+9
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: implement clock and power gating for CIK (v3)Alex Deucher2013-08-301-1/+94
| | | | | | | | | Only the APUs support power gating. v2: disable cgcg for now v3: workaround hw issue in mgcg Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: restructure rlc setupAlex Deucher2013-08-301-0/+1
| | | | | | | Restructure rlc setup to handle clock and power gating. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support for ASPM on CIK asicsAlex Deucher2013-08-301-1/+71
| | | | | | | Enables PCIE ASPM (Active State Power Management) on CIK asics. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add support for pcie gen1/2/3 switchingAlex Deucher2013-08-301-0/+57
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add fault decode function for CIKAlex Deucher2013-07-141-0/+16
| | | | | | | Helpful for debugging GPUVM errors as we can see what hw block and page generated the fault in the log. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: Add support for compute queues (v4)Alex Deucher2013-06-271-0/+62
| | | | | | | | | | | | | | | | | | | | | On CIK, the compute rings work slightly differently than on previous asics, however the basic concepts are the same. The main differences: - New MEC engines for compute queues - Multiple queues per MEC: - CI/KB: 1 MEC, 4 pipes per MEC, 8 queues per pipe = 32 queues - KV: 2 MEC, 4 pipes per MEC, 8 queues per pipe = 64 queues - Queues can be allocated and scheduled by another queue - New doorbell aperture allows you to assign space in the aperture for the wptr which allows for userspace access to queues v2: add wptr shadow, fix eop setup v3: fix comment v4: switch to new callback method Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Jerome Glisse <jglisse@redhat.com>
* drm/radeon: add UVD support for CIK (v3)Christian König2013-06-261-0/+28
| | | | | | | | v2: agd5f: fix clock dividers setup for bonaire v3: agd5f: rebase Signed-off-by: Christian König <christian.koenig@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add pcie_port indirect register accessorsAlex Deucher2013-06-261-0/+3
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add get_xclk() callback for CIKAlex Deucher2013-06-261-0/+7
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: update CIK soft resetAlex Deucher2013-06-261-0/+12
| | | | | | Update to the newer programming model. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add get_gpu_clock_counter() callback for cikAlex Deucher2013-06-261-1/+3
| | | | | | Used for GPU clock counter snapshots. Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/dce8: add support for display watermark setupAlex Deucher2013-06-261-0/+11
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: add support for sDMA dma engines (v8)Alex Deucher2013-06-251-0/+130
| | | | | | | | | | | | | | | | | | CIK has new asynchronous DMA engines called sDMA (system DMA). Each engine supports 1 ring buffer for kernel and gfx and 2 userspace queues for compute. TODO: fill in the compute setup. v2: update to the latest reset code v3: remove ib_parse v4: fix copy_dma() v5: drop WIP compute sDMA queues v6: rebase v7: endian fixes for IB v8: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon/cik: log and handle VM page fault interruptsAlex Deucher2013-06-251-0/+4
| | | | Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support for interrupts on CIK (v5)Alex Deucher2013-06-251-0/+170
| | | | | | | | | | | | Todo: - handle interrupts for compute queues v2: add documentation v3: update to latest reset code v4: update to latest illegal CP handling v5: fix missing break in interrupt handler switch statement Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Add support for RLC init on CIK (v4)Alex Deucher2013-06-251-0/+47
| | | | | | | | | | | RLC handles the interrupt controller and other tasks on the GPU. v2: add documentation v3: update programming sequence v4: additional setup Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add IB and fence dispatch functions for CIK gfx (v7)Alex Deucher2013-06-251-3/+117
| | | | | | | | | | | | | For gfx ring only. Compute is still todo. v2: add documentation v3: update to latest reset changes, integrate emit update patch. v4: fix count on wait_reg_mem for HDP flush v5: use old hdp flush method for fence v6: set valid bit for IB v7: cleanup for release Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: Add CP init for CIK (v7)Alex Deucher2013-06-251-0/+222
| | | | | | | | | | | | | | | | Sets up the GFX ring and loads ucode for GFX and Compute. Todo: - handle compute queue setup. v2: add documentation v3: integrate with latest reset changes v4: additional init fixes v5: scratch reg write back no longer supported on CIK v6: properly set CP_RB0_BASE_HI v7: rebase Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
* drm/radeon: add support mc ucode loading on CIK (v2)Alex Deucher2013-06-251-0/+16
| | | | | | | | Load the GDDR5 ucode and train the links. v2: update ucode Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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