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path: root/drivers/gpu/drm/tegra (follow)
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* drm/tegra: dc: Move more code into ->init()Thierry Reding2015-02-191-38/+36
* drm/tegra: dc: Wire up CRTC parent of atomic stateThierry Reding2015-02-191-1/+3
* drm/tegra: dc: Reset state's active_changed fieldThierry Reding2015-02-191-0/+1
* drm/tegra: hdmi: Explicitly set clock rateThierry Reding2015-02-191-0/+8
* drm/tegra: Use correct relocation target offsetsDavid Ung2015-01-271-1/+1
* drm/tegra: Add minimal power managementThierry Reding2015-01-271-0/+25
* drm/tegra: dc: Unify enabling the display controllerThierry Reding2015-01-275-52/+16
* drm/tegra: Track tiling and format in plane stateThierry Reding2015-01-272-30/+101
* drm/tegra: Track active planes in CRTC stateThierry Reding2015-01-271-28/+44
* drm/tegra: Remove unused ->mode_fixup() callbacksThierry Reding2015-01-274-179/+0
* drm/tegra: Atomic conversion, phase 3, step 3Thierry Reding2015-01-273-119/+100
* drm/tegra: Atomic conversion, phase 3, step 2Thierry Reding2015-01-271-1/+1
* drm/tegra: dc: Use atomic clock state in modesetThierry Reding2015-01-271-0/+37
* drm/tegra: sor: Implement ->atomic_check()Thierry Reding2015-01-271-0/+22
* drm/tegra: hdmi: Implement ->atomic_check()Thierry Reding2015-01-271-0/+22
* drm/tegra: dsi: Implement ->atomic_check()Thierry Reding2015-01-271-73/+196
* drm/tegra: rgb: Implement ->atomic_check()Thierry Reding2015-01-271-0/+42
* drm/tegra: dc: Store clock setup in atomic stateThierry Reding2015-01-272-3/+72
* drm/tegra: Atomic conversion, phase 3, step 1Thierry Reding2015-01-272-6/+10
* drm/tegra: Atomic conversion, phase 2Thierry Reding2015-01-276-0/+22
* drm/tegra: Atomic conversion, phase 1Thierry Reding2015-01-277-185/+223
* drm/tegra: dc: Do not needlessly deassert resetThierry Reding2015-01-271-4/+0
* drm/tegra: Output cleanup functions cannot failThierry Reding2015-01-276-32/+13
* drm/tegra: Remove remnants of the output midlayerThierry Reding2015-01-277-212/+32
* drm/tegra: debugfs cleanup cannot failThierry Reding2015-01-273-27/+9
* drm/tegra: sor: DemidlayerThierry Reding2015-01-273-368/+410
* drm/tegra: dsi: DemidlayerThierry Reding2015-01-273-169/+195
* drm/tegra: hdmi: DemidlayerThierry Reding2015-01-273-139/+147
* drm/tegra: rgb: DemidlayerThierry Reding2015-01-274-112/+161
* drm/tegra: Add tegra_dc_setup_clock() helperThierry Reding2015-01-272-0/+22
* drm/tegra: output: Make ->setup_clock() optionalThierry Reding2015-01-272-11/+9
* drm/tegra: Convert output midlayer to helpersThierry Reding2015-01-272-12/+21
* drm/tegra: dc: No longer disable planes at CRTC disableThierry Reding2015-01-271-14/+0
* drm/tegra: Move tegra_drm_mode_funcs to the coreThierry Reding2015-01-273-21/+23
* drm/tegra: dc: Wait for idle when disabledThierry Reding2015-01-271-5/+65
* drm/tegra: Stop CRTC at CRTC disable timeThierry Reding2015-01-275-16/+6
* drm/tegra: Use tegra_commit_dc() in output driversThierry Reding2015-01-276-18/+11
* drm/tegra: gem: oops in error handlingDan Carpenter2015-01-271-3/+2
* drm/tegra: dc: Fix bad irqsave/restore in tegra_dc_finish_page_flip()Dan Carpenter2015-01-271-2/+2
* drm/tegra: dsi: Adjust D-PHY timingDavid Ung2015-01-271-6/+19
* drm/tegra: dsi: Reset across ->exit()/->init()Thierry Reding2015-01-271-13/+14
* drm/tegra: dsi: Soft-reset controller on ->disableThierry Reding2015-01-271-0/+25
* drm/tegra: dsi: Registers are 32-bitThierry Reding2015-01-271-7/+7
* drm/tegra: hdmi: Registers are 32-bitThierry Reding2015-01-271-18/+18
* drm/tegra: dc: Return planar flag for non-YUV modesThierry Reding2015-01-271-0/+3
* drm/tegra: dc: Describe register copiesThierry Reding2015-01-271-0/+12
* drm/tegra: dc: Initialize border colorThierry Reding2015-01-271-0/+8
* drm/tegra: Check for NULL pointer instead of IS_ERR()Dan Carpenter2015-01-271-2/+2
* drm/tegra: plane: Use proper possible_crtcs maskThierry Reding2015-01-271-1/+14
* drm/tegra: Remove redundant zeroing out of memoryThierry Reding2015-01-272-18/+0