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* remove lots of IS_ERR_VALUE abusesArnd Bergmann2016-05-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most users of IS_ERR_VALUE() in the kernel are wrong, as they pass an 'int' into a function that takes an 'unsigned long' argument. This happens to work because the type is sign-extended on 64-bit architectures before it gets converted into an unsigned type. However, anything that passes an 'unsigned short' or 'unsigned int' argument into IS_ERR_VALUE() is guaranteed to be broken, as are 8-bit integers and types that are wider than 'unsigned long'. Andrzej Hajda has already fixed a lot of the worst abusers that were causing actual bugs, but it would be nice to prevent any users that are not passing 'unsigned long' arguments. This patch changes all users of IS_ERR_VALUE() that I could find on 32-bit ARM randconfig builds and x86 allmodconfig. For the moment, this doesn't change the definition of IS_ERR_VALUE() because there are probably still architecture specific users elsewhere. Almost all the warnings I got are for files that are better off using 'if (err)' or 'if (err < 0)'. The only legitimate user I could find that we get a warning for is the (32-bit only) freescale fman driver, so I did not remove the IS_ERR_VALUE() there but changed the type to 'unsigned long'. For 9pfs, I just worked around one user whose calling conventions are so obscure that I did not dare change the behavior. I was using this definition for testing: #define IS_ERR_VALUE(x) ((unsigned long*)NULL == (typeof (x)*)NULL && \ unlikely((unsigned long long)(x) >= (unsigned long long)(typeof(x))-MAX_ERRNO)) which ends up making all 16-bit or wider types work correctly with the most plausible interpretation of what IS_ERR_VALUE() was supposed to return according to its users, but also causes a compile-time warning for any users that do not pass an 'unsigned long' argument. I suggested this approach earlier this year, but back then we ended up deciding to just fix the users that are obviously broken. After the initial warning that caused me to get involved in the discussion (fs/gfs2/dir.c) showed up again in the mainline kernel, Linus asked me to send the whole thing again. [ Updated the 9p parts as per Al Viro - Linus ] Signed-off-by: Arnd Bergmann <arnd@arndb.de> Cc: Andrzej Hajda <a.hajda@samsung.com> Cc: Andrew Morton <akpm@linux-foundation.org> Link: https://lkml.org/lkml/2016/1/7/363 Link: https://lkml.org/lkml/2016/5/27/486 Acked-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> # For nvmem part Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge branch 'drm-next' of git://people.freedesktop.org/~airlied/linuxLinus Torvalds2016-03-212-2/+4
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull drm updates from Dave Airlie: "This is the main drm pull request for 4.6 kernel. Overall the coolest thing here for me is the nouveau maxwell signed firmware support from NVidia, it's taken a long while to extract this from them. I also wish the ARM vendors just designed one set of display IP, ARM display block proliferation is definitely increasing. Core: - drm_event cleanups - Internal API cleanup making mode_fixup optional. - Apple GMUX vga switcheroo support. - DP AUX testing interface Panel: - Refactoring of DSI core for use over more transports. New driver: - ARM hdlcd driver i915: - FBC/PSR (framebuffer compression, panel self refresh) enabled by default. - Ongoing atomic display support work - Ongoing runtime PM work - Pixel clock limit checks - VBT DSI description support - GEM fixes - GuC firmware scheduler enhancements amdkfd: - Deferred probing fixes to avoid make file or link ordering. amdgpu/radeon: - ACP support for i2s audio support. - Command Submission/GPU scheduler/GPUVM optimisations - Initial GPU reset support for amdgpu vmwgfx: - Support for DX10 gen mipmaps - Pageflipping and other fixes. exynos: - Exynos5420 SoC support for FIMD - Exynos5422 SoC support for MIPI-DSI nouveau: - GM20x secure boot support - adds acceleration for Maxwell GPUs. - GM200 support - GM20B clock driver support - Power sensors work etnaviv: - Correctness fixes for GPU cache flushing - Better support for i.MX6 systems. imx-drm: - VBlank IRQ support - Fence support - OF endpoint support msm: - HDMI support for 8996 (snapdragon 820) - Adreno 430 support - Timestamp queries support virtio-gpu: - Fixes for Android support. rockchip: - Add support for Innosilicion HDMI rcar-du: - Support for 4 crtcs - R8A7795 support - RCar Gen 3 support omapdrm: - HDMI interlace output support - dma-buf import support - Refactoring to remove a lot of legacy code. tilcdc: - Rewrite of pageflipping code - dma-buf support - pinctrl support vc4: - HDMI modesetting bug fixes - Significant 3D performance improvement. fsl-dcu (FreeScale): - Lots of fixes tegra: - Two small fixes sti: - Atomic support for planes - Improved HDMI support" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (1063 commits) drm/amdgpu: release_pages requires linux/pagemap.h drm/sti: restore mode_fixup callback drm/amdgpu/gfx7: add MTYPE definition drm/amdgpu: removing BO_VAs shouldn't be interruptible drm/amd/powerplay: show uvd/vce power gate enablement for tonga. drm/amd/powerplay: show uvd/vce power gate info for fiji drm/amdgpu: use sched fence if possible drm/amdgpu: move ib.fence to job.fence drm/amdgpu: give a fence param to ib_free drm/amdgpu: include the right version of gmc header files for iceland drm/radeon: fix indentation. drm/amd/powerplay: add uvd/vce dpm enabling flag to fix the performance issue for CZ drm/amdgpu: switch back to 32bit hw fences v2 drm/amdgpu: remove amdgpu_fence_is_signaled drm/amdgpu: drop the extra fence range check v2 drm/amdgpu: signal fences directly in amdgpu_fence_process drm/amdgpu: cleanup amdgpu_fence_wait_empty v2 drm/amdgpu: keep all fences in an RCU protected array v2 drm/amdgpu: add number of hardware submissions to amdgpu_fence_driver_init_ring drm/amdgpu: RCU protected amd_sched_fence_release ...
| * Merge tag 'drm/tegra/for-4.6-rc1' of ↵Dave Airlie2016-03-162-2/+4
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | http://anongit.freedesktop.org/git/tegra/linux into drm-next drm/tegra: Changes for v4.6-rc1 Only two cleanups this time around. One fixes reference counting of device tree nodes, the other changes the return value of a function from an unsigned int to an int to reflect that it will return error codes. * tag 'drm/tegra/for-4.6-rc1' of http://anongit.freedesktop.org/git/tegra/linux: gpu: host1x: Use a signed return type for do_relocs() gpu: host1x: bus: Add missing of_node_put()
| | * gpu: host1x: Use a signed return type for do_relocs()Markus Elfring2016-03-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The return type "unsigned int" was used by the do_relocs() function despite the fact that it will eventually return a negative error code. Use a signed integer instead to accomodate for error codes. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * gpu: host1x: bus: Add missing of_node_put()Amitoj Kaur Chawla2016-03-161-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | for_each_child_of_node() performs an of_node_get() on each iteration, so to break out of the loop an of_node_put() is required. Found using Coccinelle. The semantic patch used for this is as follows: // <smpl> @@ expression e; local idexpression n; @@ for_each_child_of_node(..., n) { ... when != of_node_put(n) when != e = n ( return n; | + of_node_put(n); ? return ...; ) ... } // </smpl> Signed-off-by: Amitoj Kaur Chawla <amitoj1606@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | | dma, mm/pat: Rename dma_*_writecombine() to dma_*_wc()Luis R. Rodriguez2016-03-092-10/+8
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename dma_*_writecombine() to dma_*_wc(), so that the naming is coherent across the various write-combining APIs. Keep the old names for compatibility for a while, these can be removed at a later time. A guard is left to enable backporting of the rename, and later remove of the old mapping defines seemlessly. Build tested successfully with allmodconfig. The following Coccinelle SmPL patch was used for this simple transformation: @ rename_dma_alloc_writecombine @ expression dev, size, dma_addr, gfp; @@ -dma_alloc_writecombine(dev, size, dma_addr, gfp) +dma_alloc_wc(dev, size, dma_addr, gfp) @ rename_dma_free_writecombine @ expression dev, size, cpu_addr, dma_addr; @@ -dma_free_writecombine(dev, size, cpu_addr, dma_addr) +dma_free_wc(dev, size, cpu_addr, dma_addr) @ rename_dma_mmap_writecombine @ expression dev, vma, cpu_addr, dma_addr, size; @@ -dma_mmap_writecombine(dev, vma, cpu_addr, dma_addr, size) +dma_mmap_wc(dev, vma, cpu_addr, dma_addr, size) We also keep the old names as compatibility helpers, and guard against their definition to make backporting easier. Generated-by: Coccinelle SmPL Suggested-by: Ingo Molnar <mingo@kernel.org> Signed-off-by: Luis R. Rodriguez <mcgrof@suse.com> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: airlied@linux.ie Cc: akpm@linux-foundation.org Cc: benh@kernel.crashing.org Cc: bhelgaas@google.com Cc: bp@suse.de Cc: dan.j.williams@intel.com Cc: daniel.vetter@ffwll.ch Cc: dhowells@redhat.com Cc: julia.lawall@lip6.fr Cc: konrad.wilk@oracle.com Cc: linux-fbdev@vger.kernel.org Cc: linux-pci@vger.kernel.org Cc: luto@amacapital.net Cc: mst@redhat.com Cc: tomi.valkeinen@ti.com Cc: toshi.kani@hp.com Cc: vinod.koul@intel.com Cc: xen-devel@lists.xensource.com Link: http://lkml.kernel.org/r/1453516462-4844-1-git-send-email-mcgrof@do-not-panic.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
* | gpu: host1x: Set DMA ops on device creationAlexandre Courbot2016-03-041-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Currently host1x-instanciated devices have their dma_ops left to NULL, which makes any DMA operation (like buffer import) on ARM64 fallback to the dummy_dma_ops and fail with an error. This patch calls of_dma_configure() with the host1x node when creating such a device, so the proper DMA operations are set. Suggested-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | gpu: host1x: Set DMA maskAlexandre Courbot2016-03-042-0/+8
|/ | | | | | | | | The default DMA mask covers a 32 bits address range, but host1x devices can address a larger range on TK1 and TX1. Set the DMA mask to the range addressable when we use the IOMMU to prevent the use of bounce buffers. Signed-off-by: Alexandre Courbot <acourbot@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add Tegra210 supportThierry Reding2015-12-148-1/+768
| | | | | | | The host1x unit found in Tegra210 SoCs is very similar to the unit in Tegra124, but it has 2 additional channels for a total of 14 channels. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Remove core driver on unregisterThierry Reding2015-12-141-0/+2
| | | | | | | | When unregistering a host1x driver, make sure to unregister the core driver as well to prevent it from sticking around and oppose reloading of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Use platform_register/unregister_drivers()Thierry Reding2015-12-141-14/+8
| | | | | | | | These new helpers simplify implementing multi-driver modules and properly handle failure to register one driver by unregistering all previously registered drivers. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix MLOCK's debug infoDmitry Osipenko2015-10-024-13/+13
| | | | | | | | | | MLOCK's debug info, spewed on CDMA timeout, contains meaningless MLOCK owner channel ID because HOST1X_SYNC_MLOCK_OWNER_CHID_F() returns shifted value, while unshifted should be used. Fix it by changing '_F' to '_V'. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Reviewed-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Power down regulators when unusedThierry Reding2015-08-131-12/+98
| | | | | | | Keep track of the number of users of DSI and CSI pads and power down the regulators that supply the bricks when all users are gone. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Add Tegra210 supportThierry Reding2015-08-131-1/+35
| | | | | | | Some changes are needed to the configuration settings for some lanes. In addition, the clock lanes for the CSI pads can no longer be calibrated. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Add Tegra132 supportThierry Reding2015-08-131-0/+18
| | | | | | | While Tegra132 has the same pads as Tegra124, some configuration values need to be programmed slightly differently. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Constify OF match tableThierry Reding2015-08-131-1/+1
| | | | | | | This table is never modified and can therefore reside in read-only memory. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Clear calibration statusThierry Reding2015-08-131-0/+4
| | | | | | | Before starting a new calibration cycle, make sure to clear the current status by writing a 1 to the various "calibration done" bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Fix clock lane register for DSIThierry Reding2015-08-131-5/+5
| | | | | | | | Use more consistent names for the clock lane configuration registers and fix the offset of the upper clock lane configuration register for the first DSI pad. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Parameterize to support future SoCsThierry Reding2015-08-131-8/+79
| | | | | | | Parameterize more of the register programming to accomodate for changes required by future SoC generations. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Export host1x_syncpt_read()Thierry Reding2015-04-021-0/+6
| | | | | | | | | This function is used to read the current value of the syncpt and is useful in situations where drivers don't schedule work and wait for the syncpoint to increment. One particular use-case is using the syncpoint as a VBLANK counter. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Provide a proper struct bus_typeThierry Reding2015-01-273-40/+81
| | | | | | | | | | | | | | | | | | | | | Previously the struct bus_type exported by the host1x infrastructure was only a very basic skeleton. Turn that implementation into a more full- fledged bus to support proper probe ordering and power management. Note that the bus infrastructure needs to be available before any of the drivers can be registered. This is automatically ensured if all drivers are built as loadable modules (via symbol dependencies). If all drivers are built-in there are no such guarantees and the link order determines the initcall ordering. Adjust drivers/gpu/Makefile to make sure that the host1x bus infrastructure is initialized prior to any of its users (only drm/tegra currently). v2: Fix building host1x and tegra-drm as modules Reported-by: Dave Airlie <airlied@gmail.com> Reviewed-by: Sean Paul <seanpaul@chromium.org> Reviewed-by: Mark Zhang <markz@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Factor out __host1x_device_del()Thierry Reding2015-01-231-44/+49
| | | | | | This function is needed in several places, so factor it out. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Call host1x_device_add() under lockThierry Reding2015-01-231-4/+2
| | | | | | | Instead of locking within host1x_device_add(), call it under the lock to make the locking more consistent. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Call ->remove() only when a device is boundThierry Reding2015-01-231-2/+7
| | | | | | | | When a driver's ->probe() function fails, the host1x bus must not call its ->remove() function because the driver will already have cleaned up in the error handling path in ->probe(). Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Set MIPI_CAL_BIAS_PAD_CFG1 registerSean Paul2014-11-131-0/+4
| | | | | | | | During calibration, sets the "internal reference level for drive pull- down" to the value specified in the Tegra TRM. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Calibrate clock lanesSean Paul2014-11-131-32/+92
| | | | | | | | | Include the clock lanes when calibrating the MIPI PHY on Tegra124 compatible devices. Signed-off-by: Sean Paul <seanpaul@chromium.org> [treding@nvidia.com: bikeshedding] Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Preserve the contents of MIPI_CAL_CTRLSean Paul2014-11-131-1/+3
| | | | | | | | | | | | | | By paving the CTRL reg value, the current code changes MIPI_CAL_PRESCALE ("Auto-cal calibration step prescale") from 1us to 0.1us (val=0). In the description for PHY's noise filter (MIPI_CAL_NOISE_FLT), the TRM states that if the value of the prescale is 0 (or 0.1us), the filter should be set between 2-5. However, the current code sets it to 0. For now, let's keep the prescale and filter values as-is, which is most likely the power-on-reset values of 0x2 and 0xa, respectively. Signed-off-by: Sean Paul <seanpaul@chromium.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: mipi: Registers are 32 bits wideThierry Reding2014-11-131-8/+8
| | | | | | | | On 64-bit platforms an unsigned long would be 64 bit and cause unnecessary casting when being passed to writel() or returned from readl(). Make register values 32 bits wide to avoid that. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Make gather offsets unsignedThierry Reding2014-11-131-1/+1
| | | | | | | | Use the u32 type for the offset in the host1x_job_gather structure for consistentcy with other structures. Negative offsets don't make sense in this context. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Print address/offset pairs consistentlyThierry Reding2014-11-132-4/+4
| | | | | | | Consistently use a format of %pad+%#x to print address/offset in debug messages. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix typo in commentThierry Reding2014-11-131-1/+1
| | | | Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Make mapped field of push buffers void *Thierry Reding2014-11-133-4/+4
| | | | | | | This reduces the amount of casting that needs to be done to get rid of annoying warnings on 64-bit builds. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Use struct host1x_bo pointers in tracesThierry Reding2014-11-131-4/+8
| | | | | | | Rather than cast to a u32 use the struct host1x_bo pointers directly. This avoid annoying warnings for 64-bit builds. Signed-off-by: Thierry Reding <treding@nvidia.com>
* drm/tegra: Make job submission 64-bit safeThierry Reding2014-08-041-11/+11
| | | | | | | | | | | | | | | | | | | | | | Job submission currently relies on the fact that struct drm_tegra_reloc and struct host1x_reloc are the same size and uses a simple call to the copy_from_user() function to copy them to kernel space. This causes the handle to be stored in the buffer object field, which then needs a cast to a 32 bit integer to resolve it to a proper buffer object pointer and store it back in the buffer object field. On 64-bit architectures that will no longer work, since pointers are 64 bits wide whereas handles will remain 32 bits. This causes the sizes of both structures to because different and copying will no longer work. Fix this by adding a new function, host1x_reloc_get_user(), that copies the structures field by field. While at it, use substructures for the command and target buffers in struct host1x_reloc for better readability. Also use unsized types to make it more obvious that this isn't part of userspace ABI. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Rename internal functions for clarityThierry Reding2014-06-051-6/+6
| | | | | | | | | | The internal host1x_{,un}register_client() functions can potentially be confused with public the host1x_client_{,un}register() functions. Rename them to host1x_{add,del}_client() to remove some of the possible confusion. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: handle the correct # of syncpt regsStephen Warren2014-04-161-2/+2
| | | | | | | | | | | | | | | | | | | | BIT_WORD() truncates rather than rounds, so the loops in syncpt_thresh_isr() and _host1x_intr_disable_all_syncpt_intrs() use <= rather than < in an attempt to process the correct number of registers when rounding of the conversion of count of bits to count of words is necessary. However, when rounding isn't necessary because the value is already a multiple of the divisor (as is the case for all values of nb_pts the code actually sees), this causes one too many registers to be processed. Solve this by using and explicit DIV_ROUND_UP() call, rather than BIT_WORD(), and comparing with < rather than <=. Fixes: 7ede0b0bf3e2 ("gpu: host1x: Add syncpoint wait and interrupts") Cc: <stable@vger.kernel.org> # 3.10 Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'drm/tegra/for-3.15-rc1' of ↵Dave Airlie2014-04-051-0/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://anongit.freedesktop.org/tegra/linux into drm-next drm/tegra: Changes for v3.15-rc1 Implement eDP support for Tegra124 and support the PRIME vmap()/vunmap() operations. A symbol that is required for upcoming V4L2 support is now exported by the host1x driver. Relicense drivers under the GPL v2 for consistency. One exception is the public header file, which is relicensed under MIT to abide by the common rule. * tag 'drm/tegra/for-3.15-rc1' of git://anongit.freedesktop.org/tegra/linux: drm/tegra: Use standard GPL v2 license text drm/tegra: Relicense under GPL v2 drm/tegra: Relicense public header under MIT drm/tegra: Add eDP support gpu: host1x: export host1x_syncpt_incr_max() function drm/tegra: prime: Add vmap support
| * gpu: host1x: export host1x_syncpt_incr_max() functionBryan Wu2014-04-041-0/+1
| | | | | | | | | | | | | | Tegra V4L2 camera driver needs this function to do frame capture. Signed-off-by: Bryan Wu <pengw@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | gpu: host1x: do not check previously handled gathersErik Faye-Lund2014-02-121-1/+1
|/ | | | | | | | | | When patching gathers, we don't need to check against gathers with lower indices than the current one, as they are guaranteed to already have been handled. Signed-off-by: Erik Faye-Lund <kusmabite@gmail.com> Acked-By: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Remove unnecessary includeThierry Reding2014-01-141-1/+0
| | | | | | | Nothing from the asm/mach/irq.h header is needed in this file, so there is no need to include it. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add Tegra124 supportThierry Reding2013-12-198-1/+768
| | | | | | | | Tegra124 has 192 syncpoints whereas its predecessors had 32 syncpoints. This required changes to the hardware register layout. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix build warningsThierry Reding2013-12-191-5/+8
| | | | | | | | | | | When debugfs support isn't enabled, gcc complains about some variables being unused. To avoid further #ifdefery, move debugfs specific setup code into static functions and use IS_ENABLED(CONFIG_DEBUG_FS) to have the compiler, rather than the preprocessor, discard them when unused. The advantage of doing it this way is that all the code will be compile-tested whether or not debugfs support is enabled. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Increase compile test coverageThierry Reding2013-12-191-1/+1
| | | | | | | | | | The ARCH_MULTIPLATFORM dependency was introduced back when Tegra didn't support multiplatform yet as a means to allow the driver to be easily compile-tested along with other DRM drivers. In the meantime, the new COMPILE_TEST Kconfig option has been introduced for exactly that purpose, so use that instead to clarify the intention. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix more sparse warningsThierry Reding2013-12-191-0/+3
| | | | | | | | Include the linux/host1x.h and dev.h headers so that function prototypes are visible to keep sparse from suggesting that their implementations be made static. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Use the correct HW headers for host1x02Thierry Reding2013-12-193-2/+150
| | | | | | | An earlier patch added a subset of the required HW specific header files but didn't actually include the right ones when compiling for host1x02. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Export public APIThierry Reding2013-12-194-0/+22
| | | | | | | Make the public API symbols visible so that depending drivers can be built as a module. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add MIPI pad calibration supportThierry Reding2013-12-194-4/+288
| | | | | | | This driver adds support to perform calibration of the MIPI pads for CSI and DSI. Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Fix a few sparse warningsThierry Reding2013-12-031-2/+3
| | | | | | | | | | | | | Include the bus.h header, so that various function declarations are visible in the source file that implements those functions. This keeps sparse from suggesting that they should be made static. Make the host1x_bus_type variable static since it isn't used globally. Finally replace the slightly unsafe dev_set_name(dev, name) by the more secure dev_set_name(dev, "%s", name). Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Silence a few warnings with LPAE=yOlof Johansson2013-11-282-4/+4
| | | | | | | | | | | | | | | When building with LPAE=y (64-bit dma_addr_t), the following warnings are seen: drivers/gpu/host1x/hw/cdma_hw.c:57:3: warning: format '%x' expects argument of type 'unsigned int', but argument 5 has type 'dma_addr_t' drivers/gpu/host1x/hw/debug_hw.c:167:10: warning: format '%x' expects argument of type 'unsigned int', but argument 3 has type 'dma_addr_t' The agreed-to solution for this is upcast to u64 and using %llx. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Thierry Reding <treding@nvidia.com>
* gpu: host1x: Add syncpoint base supportArto Merilainen2013-10-315-2/+87
| | | | | | | | | | This patch adds support for hardware syncpoint bases. This creates a simple mechanism to stall the command FIFO until an operation is completed. Signed-off-by: Arto Merilainen <amerilainen@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-19 14:49:22 +0100