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* Merge tag 'char-misc-4.16-rc1' of ↵Linus Torvalds2018-02-015-33/+18
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc driver updates from Greg KH: "Here is the big pull request for char/misc drivers for 4.16-rc1. There's a lot of stuff in here. Three new driver subsystems were added for various types of hardware busses: - siox - slimbus - soundwire as well as a new vboxguest subsystem for the VirtualBox hypervisor drivers. There's also big updates from the FPGA subsystem, lots of Android binder fixes, the usual handful of hyper-v updates, and lots of other smaller driver updates. All of these have been in linux-next for a long time, with no reported issues" * tag 'char-misc-4.16-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (155 commits) char: lp: use true or false for boolean values android: binder: use VM_ALLOC to get vm area android: binder: Use true and false for boolean values lkdtm: fix handle_irq_event symbol for INT_HW_IRQ_EN EISA: Delete error message for a failed memory allocation in eisa_probe() EISA: Whitespace cleanup misc: remove AVR32 dependencies virt: vbox: Add error mapping for VERR_INVALID_NAME and VERR_NO_MORE_FILES soundwire: Fix a signedness bug uio_hv_generic: fix new type mismatch warnings uio_hv_generic: fix type mismatch warnings auxdisplay: img-ascii-lcd: add missing MODULE_DESCRIPTION/AUTHOR/LICENSE uio_hv_generic: add rescind support uio_hv_generic: check that host supports monitor page uio_hv_generic: create send and receive buffers uio: document uio_hv_generic regions doc: fix documentation about uio_hv_generic vmbus: add monitor_id and subchannel_id to sysfs per channel vmbus: fix ABI documentation uio_hv_generic: use ISR callback method ...
| * Merge 4.15-rc6 into char-misc-nextGreg Kroah-Hartman2018-01-021-2/+4
| |\ | | | | | | | | | | | | | | | We want the fixes in here as well. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | coresight: etb10: remove duplicate includesPravin Shedge2017-12-191-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | These duplicate includes have been found with scripts/checkincludes.pl but they have been removed manually to avoid removing false positives. Signed-off-by: Pravin Shedge <pravin.shedge4linux@gmail.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | coresight: Fix disabling of CoreSight TPIURobert Walker2017-12-191-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The CoreSight TPIU should be disabled when tracing to other sinks to allow them to operate at full bandwidth. This patch fixes tpiu_disable_hw() to correctly disable the TPIU by configuring the TPIU to stop on flush, initiating a manual flush, waiting for the flush to complete and then waits for the TPIU to indicate it has stopped. Signed-off-by: Robert Walker <robert.walker@arm.com> Tested-by: Mike Leach <mike.leach@linaro.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | coresight: Use PTR_ERR_OR_ZERO()Vasyl Gomonovych2017-12-193-9/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix ptr_ret.cocci warnings: drivers/hwtracing/coresight/coresight-tpiu.c:163:1-3: WARNING: PTR_ERR_OR_ZERO can be used drivers/hwtracing/coresight/coresight-funnel.c:217:1-3: WARNING: PTR_ERR_OR_ZERO can be used drivers/hwtracing/coresight/coresight-dynamic-replicator.c:166:1-3: WARNING: PTR_ERR_OR_ZERO can be used Use PTR_ERR_OR_ZERO rather than if(IS_ERR(...)) + PTR_ERR Generated by: scripts/coccinelle/api/ptr_ret.cocci Signed-off-by: Vasyl Gomonovych <gomonovych@gmail.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * | coresight: Deduplicate bus_find_device() by name matchingLukas Wunner2017-12-191-20/+5
| | | | | | | | | | | | | | | | | | | | | | | | No need to reinvent the wheel, we have bus_find_device_by_name(). Signed-off-by: Lukas Wunner <lukas@wunner.de> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | | Merge tag 'arm64-upstream' of ↵Linus Torvalds2018-01-301-12/+3
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux Pull arm64 updates from Catalin Marinas: "The main theme of this pull request is security covering variants 2 and 3 for arm64. I expect to send additional patches next week covering an improved firmware interface (requires firmware changes) for variant 2 and way for KPTI to be disabled on unaffected CPUs (Cavium's ThunderX doesn't work properly with KPTI enabled because of a hardware erratum). Summary: - Security mitigations: - variant 2: invalidate the branch predictor with a call to secure firmware - variant 3: implement KPTI for arm64 - 52-bit physical address support for arm64 (ARMv8.2) - arm64 support for RAS (firmware first only) and SDEI (software delegated exception interface; allows firmware to inject a RAS error into the OS) - perf support for the ARM DynamIQ Shared Unit PMU - CPUID and HWCAP bits updated for new floating point multiplication instructions in ARMv8.4 - remove some virtual memory layout printks during boot - fix initial page table creation to cope with larger than 32M kernel images when 16K pages are enabled" * tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (104 commits) arm64: Fix TTBR + PAN + 52-bit PA logic in cpu_do_switch_mm arm64: Turn on KPTI only on CPUs that need it arm64: Branch predictor hardening for Cavium ThunderX2 arm64: Run enable method for errata work arounds on late CPUs arm64: Move BP hardening to check_and_switch_context arm64: mm: ignore memory above supported physical address size arm64: kpti: Fix the interaction between ASID switching and software PAN KVM: arm64: Emulate RAS error registers and set HCR_EL2's TERR & TEA KVM: arm64: Handle RAS SErrors from EL2 on guest exit KVM: arm64: Handle RAS SErrors from EL1 on guest exit KVM: arm64: Save ESR_EL2 on guest SError KVM: arm64: Save/Restore guest DISR_EL1 KVM: arm64: Set an impdef ESR for Virtual-SError using VSESR_EL2. KVM: arm/arm64: mask/unmask daif around VHE guests arm64: kernel: Prepare for a DISR user arm64: Unconditionally enable IESB on exception entry/return for firmware-first arm64: kernel: Survive corrected RAS errors notified by SError arm64: cpufeature: Detect CPU RAS Extentions arm64: sysreg: Move to use definitions for all the SCTLR bits arm64: cpufeature: __this_cpu_has_cap() shouldn't stop early ...
| * | coresight: of: Use of_cpu_node_to_id helperSuzuki K Poulose2018-01-021-12/+3
| |/ | | | | | | | | | | | | | | | | | | Reuse the new generic helper, of_cpu_node_to_id() to map a given CPU phandle to a logical CPU number. Acked-by: Mathieu Poirier <mathieu.poirier@linaro.org> Tested-by: Leo Yan <leo.yan@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* / tracing: Pass export pointer as argument to ->write()Felipe Balbi2017-12-041-2/+4
|/ | | | | | | | | | | | | By passing an export descriptor to the write function, users don't need to keep a global static pointer and can rely on container_of() to fetch their own structure. Link: http://lkml.kernel.org/r/20170602102025.5140-1-felipe.balbi@linux.intel.com Acked-by: Steven Rostedt (VMware) <rostedt@goodmis.org> Reviewed-by: Chunyan Zhang <zhang.chunyan@linaro.org> Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com> Signed-off-by: Steven Rostedt (VMware) <rostedt@goodmis.org>
* Merge tag 'char-misc-4.15-rc1' of ↵Linus Torvalds2017-11-167-26/+26
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc Pull char/misc updates from Greg KH: "Here is the big set of char/misc and other driver subsystem patches for 4.15-rc1. There are small changes all over here, hyperv driver updates, pcmcia driver updates, w1 driver updats, vme driver updates, nvmem driver updates, and lots of other little one-off driver updates as well. The shortlog has the full details. All of these have been in linux-next for quite a while with no reported issues" * tag 'char-misc-4.15-rc1' of ssh://gitolite.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (90 commits) VME: Return -EBUSY when DMA list in use w1: keep balance of mutex locks and refcnts MAINTAINERS: Update VME subsystem tree. nvmem: sunxi-sid: add support for A64/H5's SID controller nvmem: imx-ocotp: Update module description nvmem: imx-ocotp: Enable i.MX7D OTP write support nvmem: imx-ocotp: Add i.MX7D timing write clock setup support nvmem: imx-ocotp: Move i.MX6 write clock setup to dedicated function nvmem: imx-ocotp: Add support for banked OTP addressing nvmem: imx-ocotp: Pass parameters via a struct nvmem: imx-ocotp: Restrict OTP write to IMX6 processors nvmem: uniphier: add UniPhier eFuse driver dt-bindings: nvmem: add description for UniPhier eFuse nvmem: set nvmem->owner to nvmem->dev->driver->owner if unset nvmem: qfprom: fix different address space warnings of sparse nvmem: mtk-efuse: fix different address space warnings of sparse nvmem: mtk-efuse: use stack for nvmem_config instead of malloc'ing it nvmem: imx-iim: use stack for nvmem_config instead of malloc'ing it thunderbolt: tb: fix use after free in tb_activate_pcie_devices MAINTAINERS: Add git tree for Thunderbolt development ...
| * coresight: Extend the PIDR mask to cover relevant bits in PIDR2Suzuki K Poulose2017-10-207-26/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As per coresight standards, PIDR2 register has the following format : [2-0] - JEP106_bits6to4 [3] - JEDEC, designer ID is specified by JEDEC. However some of the drivers only use mask of 0x3 for the PIDR2 leaving bits [3-2] unchecked, which could potentially match the component for a different device altogether. This patch fixes the mask and the corresponding id bits for the existing devices. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | Merge tag 'configfs-for-4.15' of git://git.infradead.org/users/hch/configfsLinus Torvalds2017-11-141-5/+5
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull configfs updates from Christoph Hellwig: "A couple of configfs cleanups: - proper use of the bool type (Thomas Meyer) - constification of struct config_item_type (Bhumika Goyal)" * tag 'configfs-for-4.15' of git://git.infradead.org/users/hch/configfs: RDMA/cma: make config_item_type const stm class: make config_item_type const ACPI: configfs: make config_item_type const nvmet: make config_item_type const usb: gadget: configfs: make config_item_type const PCI: endpoint: make config_item_type const iio: make function argument and some structures const usb: gadget: make config_item_type structures const dlm: make config_item_type const netconsole: make config_item_type const nullb: make config_item_type const ocfs2/cluster: make config_item_type const target: make config_item_type const configfs: make ci_type field, some pointers and function arguments const configfs: make config_item_type const configfs: Fix bool initialization/comparison
| * | stm class: make config_item_type constBhumika Goyal2017-10-191-5/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | Make config_item_type structures const as they are either passed to a function having the argument as const or used inside a if statement or stored in the const "ci_type" field of a config_item structure. Done using Coccinelle. Signed-off-by: Bhumika Goyal <bhumirks@gmail.com> Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Christoph Hellwig <hch@lst.de>
* / License cleanup: add SPDX GPL-2.0 license identifier to files with no licenseGreg Kroah-Hartman2017-11-023-0/+3
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many source files in the tree are missing licensing information, which makes it harder for compliance tools to determine the correct license. By default all files without license information are under the default license of the kernel, which is GPL version 2. Update the files which contain no license information with the 'GPL-2.0' SPDX license identifier. The SPDX identifier is a legally binding shorthand, which can be used instead of the full boiler plate text. This patch is based on work done by Thomas Gleixner and Kate Stewart and Philippe Ombredanne. How this work was done: Patches were generated and checked against linux-4.14-rc6 for a subset of the use cases: - file had no licensing information it it. - file was a */uapi/* one with no licensing information in it, - file was a */uapi/* one with existing licensing information, Further patches will be generated in subsequent months to fix up cases where non-standard license headers were used, and references to license had to be inferred by heuristics based on keywords. The analysis to determine which SPDX License Identifier to be applied to a file was done in a spreadsheet of side by side results from of the output of two independent scanners (ScanCode & Windriver) producing SPDX tag:value files created by Philippe Ombredanne. Philippe prepared the base worksheet, and did an initial spot review of a few 1000 files. The 4.13 kernel was the starting point of the analysis with 60,537 files assessed. Kate Stewart did a file by file comparison of the scanner results in the spreadsheet to determine which SPDX license identifier(s) to be applied to the file. She confirmed any determination that was not immediately clear with lawyers working with the Linux Foundation. Criteria used to select files for SPDX license identifier tagging was: - Files considered eligible had to be source code files. - Make and config files were included as candidates if they contained >5 lines of source - File already had some variant of a license header in it (even if <5 lines). All documentation files were explicitly excluded. The following heuristics were used to determine which SPDX license identifiers to apply. - when both scanners couldn't find any license traces, file was considered to have no license information in it, and the top level COPYING file license applied. For non */uapi/* files that summary was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 11139 and resulted in the first patch in this series. If that file was a */uapi/* path one, it was "GPL-2.0 WITH Linux-syscall-note" otherwise it was "GPL-2.0". Results of that was: SPDX license identifier # files ---------------------------------------------------|------- GPL-2.0 WITH Linux-syscall-note 930 and resulted in the second patch in this series. - if a file had some form of licensing information in it, and was one of the */uapi/* ones, it was denoted with the Linux-syscall-note if any GPL family license was found in the file or had no licensing in it (per prior point). Results summary: SPDX license identifier # files ---------------------------------------------------|------ GPL-2.0 WITH Linux-syscall-note 270 GPL-2.0+ WITH Linux-syscall-note 169 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-2-Clause) 21 ((GPL-2.0 WITH Linux-syscall-note) OR BSD-3-Clause) 17 LGPL-2.1+ WITH Linux-syscall-note 15 GPL-1.0+ WITH Linux-syscall-note 14 ((GPL-2.0+ WITH Linux-syscall-note) OR BSD-3-Clause) 5 LGPL-2.0+ WITH Linux-syscall-note 4 LGPL-2.1 WITH Linux-syscall-note 3 ((GPL-2.0 WITH Linux-syscall-note) OR MIT) 3 ((GPL-2.0 WITH Linux-syscall-note) AND MIT) 1 and that resulted in the third patch in this series. - when the two scanners agreed on the detected license(s), that became the concluded license(s). - when there was disagreement between the two scanners (one detected a license but the other didn't, or they both detected different licenses) a manual inspection of the file occurred. - In most cases a manual inspection of the information in the file resulted in a clear resolution of the license that should apply (and which scanner probably needed to revisit its heuristics). - When it was not immediately clear, the license identifier was confirmed with lawyers working with the Linux Foundation. - If there was any question as to the appropriate license identifier, the file was flagged for further research and to be revisited later in time. In total, over 70 hours of logged manual review was done on the spreadsheet to determine the SPDX license identifiers to apply to the source files by Kate, Philippe, Thomas and, in some cases, confirmation by lawyers working with the Linux Foundation. Kate also obtained a third independent scan of the 4.13 code base from FOSSology, and compared selected files where the other two scanners disagreed against that SPDX file, to see if there was new insights. The Windriver scanner is based on an older version of FOSSology in part, so they are related. Thomas did random spot checks in about 500 files from the spreadsheets for the uapi headers and agreed with SPDX license identifier in the files he inspected. For the non-uapi files Thomas did random spot checks in about 15000 files. In initial set of patches against 4.14-rc6, 3 files were found to have copy/paste license identifier errors, and have been fixed to reflect the correct identifier. Additionally Philippe spent 10 hours this week doing a detailed manual inspection and review of the 12,461 patched files from the initial patch version early this week with: - a full scancode scan run, collecting the matched texts, detected license ids and scores - reviewing anything where there was a license detected (about 500+ files) to ensure that the applied SPDX license was correct - reviewing anything where there was no detection but the patch license was not GPL-2.0 WITH Linux-syscall-note to ensure that the applied SPDX license was correct This produced a worksheet with 20 files needing minor correction. This worksheet was then exported into 3 different .csv files for the different types of files to be modified. These .csv files were then reviewed by Greg. Thomas wrote a script to parse the csv files and add the proper SPDX tag to the file, in the format that the file expected. This script was further refined by Greg based on the output to detect more types of files automatically and to distinguish between header and source .c files (which need different comment types.) Finally Greg ran the script using the .csv files to generate the patches. Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Philippe Ombredanne <pombredanne@nexb.com> Reviewed-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Lewisburg PCH supportAlexander Shishkin2017-09-221-0/+5
| | | | | | | | This adds Intel(R) Trace Hub PCI ID for Lewisburg PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* intel_th: pci: Add Cedar Fork PCH supportAlexander Shishkin2017-09-221-0/+5
| | | | | | | | This adds Intel(R) Trace Hub PCI ID for Cedar Fork PCH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* stm class: Fix a use-after-freeAlexander Shishkin2017-09-221-1/+1
| | | | | | | | | | | | | | | | | | | For reasons unknown, the stm_source removal path uses device_destroy() to kill the underlying device object. Because device_destroy() uses devt to look for the device to destroy and the fact that stm_source devices don't have one (or all have the same one), it just picks the first device in the class, which may well be the wrong one. That is, loading stm_console and stm_heartbeat and then removing both will die in dereferencing a freed object. Since this should have been device_unregister() in the first place, use it instead of device_destroy(). Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Fixes: 7bd1d4093c2 ("stm class: Introduce an abstraction for System Trace Module devices") Cc: stable@vger.kernel.org Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'stm-for-greg-20170825' of ↵Greg Kroah-Hartman2017-08-289-151/+561
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ash/stm into char-misc-next Alexander writes: stm class / intel_th: Updates for 4.14 Intel TH: * Updated subdevice management code to better fit host mode * Added support for Low Power Path (LPP) output type * Fixed memory allocation with IOMMU enabled (DMAR tables) * Added Cannon Lake PCH PCI IDs * Added a quirk to force time sync on devices that need it STM: * Fixed potential read overflow in ioctl() * Documented stm_ftrace source.
| * intel_th: Perform time resync on capture startAlexander Shishkin2017-08-255-9/+82
| | | | | | | | | | | | | | | | | | | | | | On some devices (TH 2.x devices at the moment), the internal time counter is initially not synchronized to the global crystal clock, so the time stamps it produces will not be useful. In this case, the driver needs to force the time counter resync. This applies the workaround to relevant devices. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Add global activate/deactivate callbacks for the glue layersAlexander Shishkin2017-08-252-4/+24
| | | | | | | | | | | | | | A glue layer may want to install its own hooks into trace capture start and stop paths to apply workarounds. This adds optional callbacks. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: pci: Use drvdata for quirksAlexander Shishkin2017-08-253-10/+26
| | | | | | | | | | | | Allow attaching miscellaneous quirk information to devices as drvdata. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: pci: Add Cannon Lake PCH-LP supportAlexander Shishkin2017-08-251-0/+5
| | | | | | | | | | | | | | This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-LP. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
| * intel_th: pci: Add Cannon Lake PCH-H supportAlexander Shishkin2017-08-251-0/+5
| | | | | | | | | | | | | | This adds Intel(R) Trace Hub PCI ID for Cannon Lake PCH-H. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: <stable@vger.kernel.org>
| * intel_th: pti: Support Low Power Path output port typeAlexander Shishkin2017-08-252-5/+118
| | | | | | | | | | | | | | | | | | The Low Power Path (LPP) output port type, looks mostly like PTI to the software, with a few additional bits in the control register. This extends the PTI driver to support LPP ports as well. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Enumerate Low Power Path output port typeAlexander Shishkin2017-08-252-1/+17
| | | | | | | | | | | | | | | | | | Trace Hub 2.x adds Low Power Path (LPP) output port type, which provides a low power mode trace path from sources to PTI or BSSB. This adds an output subdevice for the LPP port. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: msu: Use the real device in case of IOMMU domain allocationAlexander Shishkin2017-08-251-6/+6
| | | | | | | | | | | | | | When allocating DMA buffers for the MSU, use the real device instead of GTH. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Make the switch allocate its subdevicesAlexander Shishkin2017-08-253-88/+230
| | | | | | | | | | | | | | Instead of allocating devices for every possible output subdevice, allow the switch to allocate only the ones that it knows about. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Make SOURCE devices children of the root deviceAlexander Shishkin2017-08-252-18/+27
| | | | | | | | | | | | | | | | | | | | | | The switch (GTH) does not directly interact with SOURCE type devices and may not even be present (in host mode). To reflect this and avoid inconsistencies between target and host mode, make SOURCE devices descendant directly from the root (i.e. PCI) device. Their symlinks will no longer appear under the switch device, but they can still be found under intel_th bus. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Streamline the subdevice tree accessorsAlexander Shishkin2017-08-252-16/+24
| | | | | | | | | | | | Make to_intel_th*() accessors available from the main header file. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: Output devices without ports don't need assigningAlexander Shishkin2017-08-251-11/+12
| | | | | | | | | | | | | | | | Output subdevices that rely on other output subdevices (or otherwise don't directly talk to an output port on the switch) don't need to be assigned an output port either. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * intel_th: pci: Enable bus masteringAlexander Shishkin2017-08-251-0/+2
| | | | | | | | | | | | | | The driver forgets to enable bus mastering for the PCI device. Fix this. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
| * stm: Potential read overflow in stm_char_policy_set_ioctl()Dan Carpenter2017-08-251-1/+1
| | | | | | | | | | | | | | | | | | The "size" variable comes from the user so we need to verify that it's large enough to hold an stp_policy_id struct. Fixes: 7bd1d4093c2f ("stm class: Introduce an abstraction for System Trace Module devices") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
* | coresight: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: etb10: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: etm3x: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: etm4x: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: funnel: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: replicator: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: stm: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: tmc: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: tpiu: constify amba_idArvind Yadav2017-08-281-1/+1
| | | | | | | | | | | | | | | | amba_id are not supposed to change at runtime. All functions working with const amba_id. So mark the non-const structs as const. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: STM: Clean up __iomem type usageStephen Boyd2017-08-281-8/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The casting and other things here is odd, and causes sparse to complain: drivers/hwtracing/coresight/coresight-stm.c:279:35: warning: incorrect type in argument 1 (different address spaces) drivers/hwtracing/coresight/coresight-stm.c:279:35: expected void [noderef] <asn:2>*addr drivers/hwtracing/coresight/coresight-stm.c:279:35: got struct stm_drvdata *drvdata drivers/hwtracing/coresight/coresight-stm.c:327:17: warning: incorrect type in argument 2 (different address spaces) drivers/hwtracing/coresight/coresight-stm.c:327:17: expected void volatile [noderef] <asn:2>*addr drivers/hwtracing/coresight/coresight-stm.c:327:17: got void *addr drivers/hwtracing/coresight/coresight-stm.c:330:17: warning: incorrect type in argument 2 (different address spaces) drivers/hwtracing/coresight/coresight-stm.c:330:17: expected void volatile [noderef] <asn:2>*addr drivers/hwtracing/coresight/coresight-stm.c:330:17: got void *addr drivers/hwtracing/coresight/coresight-stm.c:333:17: warning: incorrect type in argument 2 (different address spaces) drivers/hwtracing/coresight/coresight-stm.c:333:17: expected void volatile [noderef] <asn:2>*addr drivers/hwtracing/coresight/coresight-stm.c:333:17: got void *addr >From what I can tell, we don't really need to treat ch_addr as anything besides a pointer, and we can just do pointer math instead of ORing in the bits of the offset and achieve the same thing. Also, we were passing a drvdata pointer to the coresight_timeout() function, but we really wanted to pass the address of the register base. Luckily the base is the first member of the structure, so everything works out, but this is quite unsafe if we ever change the structure layout. Clean this all up so sparse stops complaining on this code. Reported-by: Satyajit Desai <sadesai@codeaurora.org> Signed-off-by: Stephen Boyd <sboyd@codeaurora.org> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight: Add support for Coresight SoC 600 componentsSuzuki K Poulose2017-08-283-0/+15
| | | | | | | | | | | | | | | | | | | | Add the peripheral ids for the Coresight SoC 600 TPIU, replicator and funnel. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc: Add support for Coresight SoC 600 TMCSuzuki K Poulose2017-08-282-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The coresight SoC 600 supports ETR save-restore which allows us to restore a trace session by retaining the RRP/RWP/STS.Full values when the TMC leaves the Disabled state. However, the TMC doesn't have a scatter-gather unit in built. Also, TMCs have different PIDs in different configurations (ETF, ETB & ETR), unlike the previous generation. While the DEVID exposes some of the features/changes in the TMC, it doesn't explicitly advertises the new save-restore feature as described above. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc: Support for save-restore in ETRSuzuki K Poulose2017-08-282-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The Coresight SoC 600 TMC ETR supports save-restore feature, where the values of the RRP/RWP and STS.Full are retained when it leaves the Disabled state. Hence, we must program the RRP/RWP and STS.Full to a proper value. For now, set the RRP/RWP to the base address of the buffer and clear the STS.Full register. This can be later exploited for proper save-restore of ETR trace contexts (e.g, perf). Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc etr: Setup AXI cache encoding for read transfersSuzuki K Poulose2017-08-282-1/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | If the ETR supports split cache encoding (i.e, separate bits for read and write transfers) unlike the older version (where read and write transfers use the same encoding in AXICTL[2-5]). This feature is not advertised and has to be described by the static mask associated with the device id. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc etr: Cleanup AXICTL register handlingSuzuki K Poulose2017-08-282-8/+19
| | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up how we setup the AXICTL register on TMC ETR. At the moment we don't set the CacheCtrl bits, which drives the arcache and awcache bits on AXI bus specifying the cacheablitiy. Set this to Write-back Read and Write-allocate. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc etr: Detect address width at runtimeSuzuki K Poulose2017-08-282-3/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | TMC in Coresight SoC-600 advertises the AXI address width in the device configuration register. Bit 16 - AXIAW_VALID 0 - AXI Address Width not valid 1 - Valid AXI Address width in Bits[23-17] Bits [23-17] - AXIAW. If AXIAW_VALID = b01 then 0x20 - 32bit AXI address bus 0x28 - 40bit AXI address bus 0x2c - 44bit AXI address bus 0x30 - 48bit AXI address bus 0x34 - 52bit AXI address bus Use the address bits from the device configuration register, if available. Otherwise, default to 40bit. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc: Detect support for scatter gatherSuzuki K Poulose2017-08-282-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | The SG unit in the TMC has been removed in Coresight SoC-600. This is however advertised by DEVID:Bit 24 = 0b1. On the previous generation, the bit is RES0, hence we can rely on the DEVID to detect the support. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Cc: Mike Leach <mike.leach@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* | coresight tmc etr: Add capabilitiy informationSuzuki K Poulose2017-08-282-5/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With new version of TMC ETR, there are differing set of features supported by the TMC. Add the capability of a given TMC ETR for making safer decisions at runtime. The device configuration register of the TMC (DEVID) lists some of the capabilities. So, we can detect some of them at probe. However, some of the features (or changes in behavior) are not advertised and we have to depend on the PID to infer the features. So we use a static description of the "unadvertised" capabilities attached to the PID. Combining both, the static and the dynamic capabilities, we maintain a bitmask of the available features which can be later checked to take appropriate actions. Cc: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com> Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-22 21:34:05 +0100