linux - linux

	Commit message (Expand)	Author	Files	Lines
2016-05-06	clk: hisilicon: add CRG driver for hi3519 soc	Jiancheng Xue	5	-0/+226
2016-05-06	clk: hisilicon: export some hisilicon APIs to modules	Jiancheng Xue	2	-15/+22
2016-05-06	reset: hisilicon: add reset controller driver for hisilicon SOCs	Jiancheng Xue	4	-0/+178
2016-05-06	clk: bcm/kona: Do not use sizeof on pointer type	Vaishali Thakkar	1	-1/+2
2016-05-06	clk: qcom: msm8916: Fix crypto clock flags	Andy Gross	1	-0/+2
2016-05-06	clk: nxp: lpc18xx: Initialize clk_init_data::flags to 0	Stephen Boyd	1	-0/+1
2016-05-06	clk/axs10x: Add I2S PLL clock driver	Jose Abreu	4	-0/+255
2016-05-03	clk: imx7d: fix ahb clock mux 1	Stefan Agner	1	-1/+1
2016-05-03	clk: fix comment of devm_clk_hw_register()	Masahiro Yamada	1	-1/+1
2016-04-28	clk: tegra: dfll: Reformat CVB frequency table	Thierry Reding	1	-25/+25
2016-04-28	clk: tegra: dfll: Properly clean up on failure and removal	Thierry Reding	4	-4/+48
2016-04-28	clk: tegra: dfll: Make code more comprehensible	Thierry Reding	3	-41/+37
2016-04-28	clk: tegra: dfll: Reference CVB table instead of copying data	Thierry Reding	3	-27/+17
2016-04-28	clk: tegra: dfll: Update kerneldoc	Thierry Reding	1	-5/+5
2016-04-28	clk: tegra: Fix PLL_U post divider and initial rate on Tegra30	Lucas Stach	1	-5/+6
2016-04-28	clk: tegra: Initialize PLL_C to sane rate on Tegra30	Lucas Stach	1	-0/+1
2016-04-28	clk: tegra: Fix pllre Tegra210 and add pll_re_out1	Rhyland Klein	4	-3/+67
2016-04-28	clk: tegra: Add sor_safe clock	Thierry Reding	2	-0/+5
2016-04-28	clk: tegra: dpaux and dpaux1 are fixed factor clocks	Thierry Reding	3	-2/+12
2016-04-28	clk: tegra: Add dpaux1 clock	Thierry Reding	3	-0/+3
2016-04-28	clk: tegra: Use correct parent for dpaux clock	Thierry Reding	1	-1/+1
2016-04-28	clk: tegra: Add fixed factor peripheral clock type	Thierry Reding	3	-0/+138
2016-04-28	clk: tegra: Special-case mipi-cal parent on Tegra114	Thierry Reding	2	-2/+6
2016-04-28	clk: tegra: Remove trailing blank line	Thierry Reding	1	-1/+0
2016-04-28	clk: tegra: Constify peripheral clock registers	Thierry Reding	5	-7/+7
2016-04-28	clk: tegra: Add interface to enable hardware control of SATA/XUSB PLLs	Andrew Bresticker	2	-0/+63
2016-04-28	clk: renesas: cpg-mssr: Use always-on governor for Clock Domain	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: cpg-mssr: Postpone call to pm_genpd_init()	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: mstp: Use always-on governor for Clock Domain	Geert Uytterhoeven	1	-1/+1
2016-04-28	clk: renesas: mstp: Postpone call to pm_genpd_init()	Geert Uytterhoeven	1	-2/+1
2016-04-27	clk: imx: return correct frequency for Ethernet PLL	Stefan Agner	1	-1/+8
2016-04-26	clk: renesas: r8a7795: Add VIN clocks	Niklas Söderlund	1	-0/+8
2016-04-26	clk: renesas: r8a7795: Add CSI2 clocks	Niklas Söderlund	1	-0/+5
2016-04-25	clk: rockchip: fix the rk3399 cifout clock	Xing Zheng	1	-5/+6
2016-04-25	clk: rockchip: drop unnecessary CLK_IGNORE_UNUSED flags from rk3399	Xing Zheng	1	-157/+157
2016-04-25	clk: rockchip: add some frequencies on the rk3399 PLL table	Xing Zheng	1	-1/+10
2016-04-25	clk: rockchip: assign more necessary rk3399 clock ids	Xing Zheng	1	-6/+6
2016-04-25	clk: rockchip: export some necessary rk3399 clock ids	Xing Zheng	1	-0/+2
2016-04-25	clk: rockchip: rename rga clock-id on rk3399	Xing Zheng	1	-1/+1
2016-04-25	clk: rockchip: add general gpu soft-reset on rk3399	Xing Zheng	1	-0/+1
2016-04-25	clk: rockchip: fix the gate bit for i2c4 and i2c8 on rk3399	Xing Zheng	1	-2/+2
2016-04-25	clk: sunxi: Let divs clocks read the base factor clock name from devicetree	Jens Kuske	1	-11/+30
2016-04-25	clk: rockchip: fix of spelling mistake on unsuccessful in pll clock type	Colin Ian King	1	-2/+2
2016-04-22	clk: sunxi: Add TCON channel1 clock	Maxime Ripard	3	-0/+302
2016-04-22	clk: sunxi: Add PLL3 clock	Maxime Ripard	3	-0/+100
2016-04-22	dt-bindings: clk: sun5i: add DRAM gates compatible	Maxime Ripard	1	-0/+1
2016-04-22	clk: sunxi: Use resource_size	Vaishali Thakkar	1	-1/+1
2016-04-22	clk: sunxi: Add sun6i/8i display support	Jean-Francois Moine	2	-0/+39
2016-04-22	clk: sunxi: mod1 clock should modify it's parent	Andrea Venturi	1	-1/+1
2016-04-21	clk: composite: Add unregister function	Maxime Ripard	2	-0/+16