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* iommu/arm-smmu: Invalidate TLBs properlyRobin Murphy2015-12-171-3/+13
| | | | | | | | | | | | | | | | When invalidating an IOVA range potentially spanning multiple pages, such as when removing an entire intermediate-level table, we currently only issue an invalidation for the first IOVA of that range. Since the architecture specifies that address-based TLB maintenance operations target a single entry, an SMMU could feasibly retain live entries for subsequent pages within that unmapped range, which is not good. Make sure we hit every possible entry by iterating over the whole range at the granularity provided by the pagetable implementation. Signed-off-by: Robin Murphy <robin.murphy@arm.com> [will: added missing semicolons...] Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/io-pgtable: Indicate granule for TLB maintenanceRobin Murphy2015-12-171-1/+1
| | | | | | | | | | | | | | | | IOMMU hardware with range-based TLB maintenance commands can work happily with the iova and size arguments passed via the tlb_add_flush callback, but for IOMMUs which require separate commands per entry in the range, it is not straightforward to infer the necessary granularity when it comes to issuing the actual commands. Add an additional argument indicating the granularity for the benefit of drivers needing to know, and update the ARM LPAE code appropriately (for non-leaf invalidations we currently just assume the worst-case page granularity rather than walking the table to check). Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Correct group reference countPeng Fan2015-12-171-0/+1
| | | | | | | | | | | | | | | | | | | | | | The basic flow for add a device: arm_smmu_add_device |->iommu_group_get_for_dev |->iommu_group_get return group; (1) |->ops->device_group : Init/increase reference count to/by 1. |->iommu_group_add_device : Increase reference count by 1. return group (2) |->return 0; Since we are adding one device, the flow is (2) and the group reference count will be increased by 2. So, we need to add iommu_group_put at the end of arm_smmu_add_device to decrease the count by 1. Also take the failure path into consideration when fail to add a device. Signed-off-by: Peng Fan <van.freenix@gmail.com> Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Delete an unnecessary check before free_io_pgtable_ops()Markus Elfring2015-12-171-3/+1
| | | | | | | | | | The free_io_pgtable_ops() function tests whether its argument is NULL and then returns immediately. Thus the test around the call is not needed. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Will Deacon <will.deacon@arm.com>
*-. Merge branches 'x86/vt-d', 'arm/omap', 'arm/smmu', 's390', 'core' and ↵Joerg Roedel2015-11-021-57/+75
|\ \ | | | | | | | | | | | | | | | | | | 'x86/amd' into next Conflicts: drivers/iommu/amd_iommu_types.h
| | * iommu/arm-smmu: Switch to device_group call-backJoerg Roedel2015-10-221-31/+46
| |/ |/| | | | | | | | | | | | | This converts the ARM SMMU and the SMMUv3 driver to use the new device_group call-back. Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| * iommu/arm-smmu: Remove redundant calculation of gr0 base addressWill Deacon2015-10-151-2/+1
| | | | | | | | | | | | | | | | Since commit 1463fe44fd0f ("iommu/arm-smmu: Don't use VMIDs for stage-1 translations"), we don't need the GR0 base address when initialising a context bank, so remove the useless local variable and its init code. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * iommu/arm-smmu: ThunderX mis-extends 64bit registersTirumalesh Chalamarla2015-10-141-23/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMMU architecture defines two different behaviors when 64-bit registers are written with 32-bit writes. The first behavior causes zero extension into the upper 32-bits. The second behavior splits a 64-bit register into "normal" 32-bit register pairs. On some buggy implementations, registers incorrectly zero extended when they should instead behave as normal 32-bit register pairs. Signed-off-by: Tirumalesh Chalamarla <tchalamarla@caviumnetworks.com> [will: removed redundant macro parameters] Signed-off-by: Will Deacon <will.deacon@arm.com>
| * iommu/arm-smmu: Remove unneeded '0x' annotationFabio Estevam2015-10-141-1/+1
|/ | | | | | | | '%pad' automatically prints with '0x', so remove the explicit '0x' annotation. Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Remove arm_smmu_flush_pgtable()Robin Murphy2015-08-061-13/+0
| | | | | | | | | With the io-pgtable code now enforcing its own appropriate sync points, the vestigial flush_pgtable callback becomes entirely redundant, so remove it altogether. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Clean up DMA API usageRobin Murphy2015-08-061-16/+6
| | | | | | | | With the correct DMA API calls now integrated into the io-pgtable code, let that handle the flushing of non-coherent page table updates. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Sort out coherencyRobin Murphy2015-07-311-3/+17
| | | | | | | | | | | | | | | | Currently, we detect whether the SMMU has coherent page table walk capability from the IDR0.CTTW field, and base our cache maintenance decisions on that. In preparation for fixing the bogus DMA API usage, however, we need to ensure that the DMA API agrees about this, which necessitates deferring to the dma-coherent property in the device tree for the final say. As an added bonus, since systems exist where an external CTTW signal has been tied off incorrectly at integration, allowing DT to override it offers a neat workaround for coherency issues with such SMMUs. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: Fix broken ATOS checkWill Deacon2015-06-291-1/+1
| | | | | | | | | | | | | | Commit 83a60ed8f0b5 ("iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS condition") accidentally negated the ID0_ATOSNS predicate in the ATOS feature check, causing the driver to attempt ATOS requests on SMMUv2 hardware without the ATOS feature implemented. This patch restores the predicate to the correct value. Cc: <stable@vger.kernel.org> # 4.0+ Reported-by: Varun Sethi <varun.sethi@freescale.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: Make force_stage module param read-only in sysfsWill Deacon2015-05-291-1/+1
| | | | | | | | | | | Changing force_stage dynamically isn't supported by the driver and it also doesn't make a whole lot of sense to change it once the SMMU is up and running. This patch makes the sysfs entry for the parameter read-only. Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: Fix ATS1* register writesRobin Murphy2015-05-291-11/+10
| | | | | | | | | | | | | | | | The ATS1* address translation registers only support being written atomically - in SMMUv2 where they are 64 bits wide, 32-bit writes to the lower half are automatically zero-extended, whilst 32-bit writes to the upper half are ignored. Thus, the current logic of performing 64-bit writes as two 32-bit accesses is wrong. Since we already limit IOVAs to 32 bits on 32-bit ARM, the lack of a suitable writeq() implementation there is not an issue, and we only need a little preprocessor ugliness to safely hide the 64-bit case. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: Fix sign-extension of upstream bus addresses at stage 1Will Deacon2015-05-111-28/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stage 1 translation is controlled by two sets of page tables (TTBR0 and TTBR1) which grow up and down from zero respectively in the ARMv8 translation regime. For the SMMU, we only care about TTBR0 and, in the case of a 48-bit virtual space, we expect to map virtual addresses 0x0 through to 0xffff_ffff_ffff. Given that some masters may be incapable of emitting virtual addresses targetting TTBR1 (e.g. because they sit on a 48-bit bus), the SMMU architecture allows bit 47 to be sign-extended, halving the virtual range of TTBR0 but allowing TTBR1 to be used. This is controlled by the SEP field in TTBCR2. The SMMU driver incorrectly enables this sign-extension feature, which causes problems when userspace addresses are programmed into a master device with the SMMU expecting to map the incoming transactions via TTBR0; if the top bit of address is set, we will instead get a translation fault since TTBR1 walks are disabled in the TTBCR. This patch fixes the issue by disabling sign-extension of a fixed virtual address bit and instead basing the behaviour on the upstream bus size: the incoming address is zero extended unless the upstream bus is only 49 bits wide, in which case bit 48 is used as the sign bit and is replicated to the upper bits. Cc: <stable@vger.kernel.org> # v4.0+ Reported-by: Varun Sethi <varun.sethi@freescale.com> Signed-off-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
*---. Merge branches 'iommu/fixes', 'x86/vt-d', 'x86/amd', 'arm/smmu', 'arm/tegra' ↵Joerg Roedel2015-04-021-64/+107
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and 'core' into next Conflicts: drivers/iommu/amd_iommu.c drivers/iommu/tegra-gart.c drivers/iommu/tegra-smmu.c
| | | * iommu/arm-smmu: Make use of domain_alloc and domain_freeJoerg Roedel2015-03-311-19/+27
| | |/ | |/| | | | | | | | | | | | | | | | | | | Implement domain_alloc and domain_free iommu-ops as a replacement for domain_init/domain_destroy. Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | * iommu/arm-smmu: handle multi-alias IOMMU groups for PCI devicesWill Deacon2015-03-271-35/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IOMMU groups for PCI devices can correspond to multiple DMA aliases due to things like ACS and PCI quirks. This patch extends the ARM SMMU ->add_device callback so that we consider all of the DMA aliases for a PCI IOMMU group, rather than creating a separate group for each Requester ID. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: set a more appropriate DMA maskRobin Murphy2015-03-271-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since we use dma_map_page() as an architecture-independent means of making page table updates visible to non-coherent SMMUs, we need to have a suitable DMA mask set to discourage the DMA mapping layer from creating bounce buffers and flushing those instead, if said page tables happen to lie outside the default 32-bit mask. Tested-by: Mitchel Humpherys <mitchelh@codeaurora.org> Signed-off-by: Robin Murphy <robin.murphy@arm.com> [will: added error checking] Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: ensure CBA2R is initialised before CBAR on SMMUv2Will Deacon2015-03-271-10/+14
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | The VMID16 (8.1) extension to SMMUv2 added a 16-bit VMID16 field to the CBA2R registers. Unfortunately, if software writes this field as zero after setting an 8-bit VMID in a stage-2 CBAR, then the VMID may also be overwritten with zero on some early implementations (the architecture was later updated to fix this issue). This patch ensures that we initialise CBA2R before CBAR, therefore ensuring that the VMID is set correctly. Tested-by: Manish Jaggi <mjaggi@caviumnetworks.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
* / iommu/arm-smmu: fix ARM_SMMU_FEAT_TRANS_OPS conditionBaptiste Reynal2015-03-231-3/+6
|/ | | | | | | | | | | | This patch is a fix to "iommu/arm-smmu: add support for iova_to_phys through ATS1PR". According to ARM documentation, translation registers are optional even in SMMUv1, so ID0_S1TS needs to be checked to verify their presence. Also, we check that the domain is a stage-1 domain. Signed-off-by: Baptiste Reynal <b.reynal@virtualopensystems.com> Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: Avoid build warningArnd Bergmann2015-02-031-1/+1
| | | | | | | | | | | | | | | ARM allmodconfig gained a new warning when dma_addr_t is 32-bit wide: drivers/iommu/arm-smmu.c: In function 'arm_smmu_iova_to_phys_hard': drivers/iommu/arm-smmu.c:1255:3: warning: right shift count >= width of type This changes the calculation so that the effective type is always 64-bit. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Fixes: 859a732e4f713 ("iommu/arm-smmu: add support for iova_to_phys through ATS1PR") Acked-by: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/arm-smmu: add support for iova_to_phys through ATS1PRMitchel Humpherys2015-01-191-2/+67
| | | | | | | | | | | | | | | | Currently, we provide the iommu_ops.iova_to_phys service by doing a table walk in software to translate IO virtual addresses to physical addresses. On SMMUs that support it, it can be useful to ask the SMMU itself to do the translation. This can be used to warm the TLBs for an SMMU. It can also be useful for testing and hardware validation. Since the address translation registers are optional on SMMUv2, only enable hardware translations when using SMMUv1 or when SMMU_IDR0.S1TS=1 and SMMU_IDR0.ATOSNS=0, as described in the ARM SMMU v1-v2 spec. Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> [will: reworked on top of generic iopgtbl changes] Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: don't touch the secure STLBIALL registerMitchel Humpherys2015-01-191-2/+0
| | | | | | | | | Currently we do a STLBIALL when we initialize the SMMU. However, in some configurations that register is not supposed to be touched and is marked as "Secure only" in the spec. Rip it out. Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* iommu/arm-smmu: make use of generic LPAE allocatorWill Deacon2015-01-191-623/+263
| | | | | | | The ARM SMMU can walk LPAE page tables, so make use of the generic allocator. Signed-off-by: Will Deacon <will.deacon@arm.com>
* Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-151-1/+0
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * iommu: drop owner assignment from platform_driversWolfram Sang2014-10-201-1/+0
| | | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
| |
| \
*-. \ Merge branches 'arm/omap', 'arm/msm', 'arm/rockchip', 'arm/renesas', ↵Joerg Roedel2014-12-021-24/+110
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | 'arm/smmu', 'x86/vt-d', 'x86/amd' and 'core' into next Conflicts: drivers/iommu/arm-smmu.c
| | * iommu: Add iommu_map_sg() functionOlav Haugan2014-11-041-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mapping and unmapping are more often than not in the critical path. map_sg allows IOMMU driver implementations to optimize the process of mapping buffers into the IOMMU page tables. Instead of mapping a buffer one page at a time and requiring potentially expensive TLB operations for each page, this function allows the driver to map all pages in one go and defer TLB maintenance until after all pages have been mapped. Additionally, the mapping operation would be faster in general since clients does not have to keep calling map API over and over again for each physically contiguous chunk of memory that needs to be mapped to a virtually contiguous region. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| * iommu/arm-smmu: add support for DOMAIN_ATTR_NESTING attributeWill Deacon2014-11-141-20/+90
| | | | | | | | | | | | | | | | | | | | | | | | When domains are set with the DOMAIN_ATTR_NESTING flag, we must ensure that we allocate them to stage-2 context banks if the hardware permits it. This patch adds support for the attribute to the ARM SMMU driver, with the actual stage being determined depending on the features supported by the hardware. Signed-off-by: Will Deacon <will.deacon@arm.com>
| * iommu/arm-smmu: Play nice on non-ARM/SMMU systemsThierry Reding2014-11-141-0/+12
| | | | | | | | | | | | | | | | | | | | Currently the driver registers IOMMU bus operations for all busses even if no ARM SMMU is present on a system. Depending on the driver probing order this prevents the driver for the real IOMMU to register itself as the bus-wide IOMMU. Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * iommu/arm-smmu: add IOMMU_CAP_NOEXEC to the ARM SMMU driverAntonios Motakis2014-11-141-0/+2
| | | | | | | | | | | | | | | | The ARM SMMU supports the IOMMU_NOEXEC protection flag. Add the corresponding IOMMU capability. Signed-off-by: Antonios Motakis <a.motakis@virtualopensystems.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| * iommu/arm-smmu: change IOMMU_EXEC to IOMMU_NOEXECAntonios Motakis2014-11-141-4/+5
|/ | | | | | | | | | Exposing the XN flag of the SMMU driver as IOMMU_NOEXEC instead of IOMMU_EXEC makes it enforceable, since for IOMMUs that don't support the XN flag pages will always be executable. Signed-off-by: Antonios Motakis <a.motakis@virtualopensystems.com> Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Will Deacon <will.deacon@arm.com>
*---. Merge branches 'arm/exynos', 'arm/omap', 'arm/smmu', 'x86/vt-d', 'x86/amd' ↵Joerg Roedel2014-10-021-91/+129
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | and 'core' into next Conflicts: drivers/iommu/arm-smmu.c
| | | * iommu: Make of_device_id array constKiran Padwal2014-09-251-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Make of_device_id array const, because all OF functions handle it as const. Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | | * iommu/arm-smmu: Convert to iommu_capable() API functionJoerg Roedel2014-09-251-10/+9
| |_|/ |/| | | | | | | | | | | Cc: Will Deacon <will.deacon@arm.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
| | * iommu/arm-smmu: fix bug in pmd constructionMitchel Humpherys2014-09-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We are using the same pfn for every pte we create while constructing the pmd. Fix this by actually updating the pfn on each iteration of the pmd construction loop. It's not clear if we can actually hit this bug right now since iommu_map splits up the calls to .map based on the page size, so we only ever seem to iterate this loop once. However, things might change in the future that might cause us to hit this. Signed-off-by: Mitchel Humpherys <mitchelh@codeaurora.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: support MMU-401Robin Murphy2014-09-161-0/+1
| | | | | | | | | | | | | | | | | | | | | MMU-401 is similar to MMU-400, but updated with limited ARMv8 support. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: fix architecture version detectionRobin Murphy2014-09-161-22/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The SMMU driver was relying on a quirk of MMU-500 r2px to identify the correct architecture version. Since this does not apply to other implementations, make the architecture version for each supported implementation explicit. While we're at it, remove the unnecessary #ifdef since the dependencies for CONFIG_ARM_SMMU already imply CONFIG_OF. Signed-off-by: Robin Murphy <robin.murphy@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: don't bother truncating the s1 output size to VA_BITSWill Deacon2014-09-161-23/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order for nested translation to work correctly, we need to ensure that the maximum output address size from stage-1 is <= the maximum supported input address size to stage-2. The latter is currently defined by VA_BITS, since we make use of the CPU page table functions for allocating out tables and so the driver currently enforces this restriction by truncating the stage-1 output size during probe. In reality, this doesn't make a lot of sense; the guest OS is responsible for managing the stage-1 page tables, so we actually just need to ensure that the ID registers of the virtual SMMU interface only advertise the supported stage-2 input size. This patch fixes the problem by treating the stage-1 and stage-2 input address sizes separately. Reported-by: Tirumalesh Chalamarla <tchalamarla@cavium.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: use page shift instead of page size to avoid divisionWill Deacon2014-09-161-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Arbitrary integer division is not available in all ARM CPUs, so the GCC may spit out calls to helper functions which are not implemented in the kernel. This patch avoids these problems in the SMMU driver by using page shift instead of page size, so that divisions by the page size (as required by the vSMMU code) can be expressed as a simple right shift. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: put iommu_domain pointer in dev->archdata.iommuWill Deacon2014-09-161-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | In preparation for nested translation support, stick a pointer to the iommu_domain in dev->archdata.iommu. This makes it much easier to grab hold of the physical group configuration (e.g. cbndx) when dealing with vSMMU accesses from a guest. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: add support for multi-master iommu groupsWill Deacon2014-09-161-26/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Whilst the driver currently creates one IOMMU group per device, this will soon change when we start supporting non-transparent PCI bridges which require all upstream masters to be assigned to the same address space. This patch reworks our IOMMU group code so that we can easily support multi-master groups. The master configuration (streamids and smrs) is stored as private iommudata on the group, whilst the low-level attach/detach code is updated to avoid double alloc/free when dealing with multiple masters sharing the same SMMU configuration. This unifies device handling, regardless of whether the device sits on the platform or pci bus. Signed-off-by: Will Deacon <will.deacon@arm.com>
| | * iommu/arm-smmu: allow translation stage to be forced on the cmdlineWill Deacon2014-09-161-2/+13
| |/ |/| | | | | | | | | | | | | | | | | | | | | When debugging and testing code on an SMMU that supports nested translation, it can be useful to restrict the driver to a particular stage of translation. This patch adds a module parameter to the ARM SMMU driver to allow this by restricting the ability of the probe() code to detect support for only the specified stage. Signed-off-by: Will Deacon <will.deacon@arm.com>
* | iommu/arm-smmu: fix corner cases in address size calculationsWill Deacon2014-09-021-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Working out the usable address sizes for the SMMU is surprisingly tricky. We must take into account both the limitations of the hardware for VA, IPA and PA sizes but also any restrictions imposed by the Linux page table code, particularly when dealing with nested translation (where the IPA size is limited by the input address size at stage-2). This patch fixes a few corner cases in our address size handling so that we correctly deal with 40-bit addresses in TTBCR2 and restrict the IPA size differently depending on whether or not we have support for nested translation. Signed-off-by: Will Deacon <will.deacon@arm.com>
* | iommu/arm-smmu: fix decimal printf format specifiers prefixed with 0xHans Wennborg2014-09-021-1/+1
| | | | | | | | | | | | | | | | | | | | The prefix suggests the number should be printed in hex, so use the %x specifier to do that. Found by using regex suggested by Joe Perches. Signed-off-by: Hans Wennborg <hans@hanshq.net> Signed-off-by: Will Deacon <will.deacon@arm.com>
* | iommu/arm-smmu: Do not access non-existing S2CR registersOlav Haugan2014-09-021-7/+21
| | | | | | | | | | | | | | | | | | | | The number of S2CR registers is not properly set when stream matching is not supported. Fix this and add check that we do not try to access outside of the number of S2CR regisrers. Signed-off-by: Olav Haugan <ohaugan@codeaurora.org> [will: added missing NUMSIDB_* definitions] Signed-off-by: Will Deacon <will.deacon@arm.com>
* | iommu/arm-smmu: fix s2cr and smr teardown on device detach from domainWill Deacon2014-09-021-15/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we attach a device to a domain, we configure the SMRs (if we have any) to match the Stream IDs for the corresponding SMMU master and program the s2crs accordingly. However, on detach we tear down the s2crs assuming stream-indexing (as opposed to stream-matching) and SMRs assuming they are present. This patch fixes the device detach code so that it operates as a converse of the attach code. Cc: <stable@vger.kernel.org> Signed-off-by: Will Deacon <will.deacon@arm.com>
* | iommu/arm-smmu: remove pgtable_page_{c,d}tor()Vladimir Murzin2014-09-011-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If split page table lock for PTE tables is enabled (CONFIG_SPLIT_PTLOCK_CPUS <=NR_CPUS) pgtable_page_ctor() leads to non-atomic allocation for ptlock with a spinlock held, resulting in: ------------[ cut here ]------------ WARNING: CPU: 0 PID: 466 at kernel/locking/lockdep.c:2742 lockdep_trace_alloc+0xd8/0xf4() DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) Modules linked in: CPU: 0 PID: 466 Comm: dma0chan0-copy0 Not tainted 3.16.0-3d47efb-clean-pl330-dma_test-ve-a15-a32-slr-m c-on-3+ #55 [<80014748>] (unwind_backtrace) from [<80011640>] (show_stack+0x10/0x14) [<80011640>] (show_stack) from [<802bf864>] (dump_stack+0x80/0xb4) [<802bf864>] (dump_stack) from [<8002385c>] (warn_slowpath_common+0x64/0x88) [<8002385c>] (warn_slowpath_common) from [<80023914>] (warn_slowpath_fmt+0x30/0x40) [<80023914>] (warn_slowpath_fmt) from [<8005d818>] (lockdep_trace_alloc+0xd8/0xf4) [<8005d818>] (lockdep_trace_alloc) from [<800d3d78>] (kmem_cache_alloc+0x24/0x144) [<800d3d78>] (kmem_cache_alloc) from [<800bfae4>] (ptlock_alloc+0x18/0x2c) [<800bfae4>] (ptlock_alloc) from [<802b1ec0>] (arm_smmu_handle_mapping+0x4c0/0x690) [<802b1ec0>] (arm_smmu_handle_mapping) from [<802b0cd8>] (iommu_map+0xe0/0x148) [<802b0cd8>] (iommu_map) from [<80019098>] (arm_coherent_iommu_map_page+0x160/0x278) [<80019098>] (arm_coherent_iommu_map_page) from [<801f4d78>] (dmatest_func+0x60c/0x1098) [<801f4d78>] (dmatest_func) from [<8003f8ac>] (kthread+0xcc/0xe8) [<8003f8ac>] (kthread) from [<8000e868>] (ret_from_fork+0x14/0x2c) ---[ end trace ce0d27e6f434acf8 ]-- Split page tables lock is not used in the driver. In fact, page tables are guarded with domain lock, so remove calls to pgtable_page_{c,d}tor(). Cc: <stable@vger.kernel.org> Signed-off-by: Vladimir Murzin <vladimir.murzin@arm.com> Signed-off-by: Will Deacon <will.deacon@arm.com>
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