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* irqchip/bcm2836: Make bcm2836_smp_boot_secondary staticBen Dooks2016-06-131-2/+2
| | | | | | | | | | | The bcm2836_smp_boot_secondary() is not declared or used elsewhere so make it static to fix the following warning: drivers/irqchip/irq-bcm2836.c:227:12: warning: symbol 'bcm2836_smp_boot_secondary' was not declared. Should it be static? Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk> Link: https://lkml.kernel.org/r/1465407697-8116-1-git-send-email-ben.dooks@codethink.co.uk Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip/bcm2836: Use a more generic memory barrier callEric Anholt2016-05-111-1/+1
| | | | | | | | | | | | dsb() requires an argument on arm64, so we needed to add "sy". Instead, take this opportunity to switch to the same smp_wmb() call that gic uses for its IPIs. This is a less strong barrier than we were doing before (dmb(ishst) compared to dsb(sy)), but it seems to be the correct one. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/bcm2836: Fix compiler warning on 64-bit buildEric Anholt2016-05-111-1/+1
| | | | | | Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/bcm2836: Drop smp_set_ops on arm64 buildsEric Anholt2016-05-111-1/+5
| | | | | | | | | For arm64, the bootloader will instead be implementing the spin-table enable method. Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/bcm2836: Drop extra memory barrier in SMP boot.Eric Anholt2016-02-181-1/+0
| | | | | | | | The writel() immediately after this has a barrier, anyway. Signed-off-by: Eric Anholt <eric@anholt.net> Link: https://lkml.kernel.org/r/1454620468-31303-1-git-send-email-eric@anholt.net Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* irqchip/bcm2836: Make code more readableAndrea Merello2015-12-291-1/+1
| | | | | | | | | | | | | | | | | | Avoid using hardcoded magics. We have a #define for this number. No functional changes. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net> Cc: linux-arm-kernel@lists.infradead.org Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-rpi-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1451166444-11044-5-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/bcm2836: Tolerate IRQs while no flag is set in ISRAndrea Merello2015-12-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | On my RPi2 I got a lot of: unexpected IRQ trap at vector 00 This happens because bcm2836_arm_irqchip_handle_irq() is sometimes invoked even if the ISR is clear, and this case is not handled. This patch explicitly handle this case, fixing the kernel complaints about the bad IRQ lookup. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Reviewed-by: Eric Anholt <eric@anholt.net> Signed-off-by: Eric Anholt <eric@anholt.net> Cc: linux-arm-kernel@lists.infradead.org Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-rpi-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1451166444-11044-4-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/bcm2836: Add SMP support for the 2836Andrea Merello2015-12-291-2/+23
| | | | | | | | | | | | | | | | | | | | The firmware sets the secondaries spinning waiting for a non-NULL value to show up in the last IPI mailbox. The original SMP port from the downstream tree was done by Andrea, and Eric cleaned it up/rewrote it a few times from there. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Cc: linux-arm-kernel@lists.infradead.org Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-rpi-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1451166444-11044-3-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip/bcm2836: Fix initialization of the LOCAL_IRQ_CNT timersEric Anholt2015-12-291-0/+26
| | | | | | | | | | | | | | | | | The irqchip's register area includes the the setup for the timer's scaling factors, and for the platform we want a fixed configuration of these registers. Signed-off-by: Eric Anholt <eric@anholt.net> Cc: linux-arm-kernel@lists.infradead.org Cc: Stephen Warren <swarren@wwwdotorg.org> Cc: Lee Jones <lee@kernel.org> Cc: Florian Fainelli <f.fainelli@gmail.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-rpi-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1451166444-11044-2-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* irqchip: Add bcm2836 interrupt controller for Raspberry Pi 2Eric Anholt2015-08-201-0/+275
This interrupt controller is the new root interrupt controller with the timer, PMU events, and IPIs, and the bcm2835's interrupt controller is chained off of it to handle the peripherals. I wrote the interrupt chip support, while Andrea Merello wrote the IPI code. Signed-off-by: Andrea Merello <andrea.merello@gmail.com> Signed-off-by: Eric Anholt <eric@anholt.net> Acked-by: Stephen Warren <swarren@wwwdotorg.org> Cc: linux-rpi-kernel@lists.infradead.org Cc: Lee Jones <lee@kernel.org> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Link: http://lkml.kernel.org/r/1438902033-31477-5-git-send-email-eric@anholt.net Signed-off-by: Thomas Gleixner <tglx@linutronix.de>