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* irqchip/gic: Add support to device tree based quirksSrinivas Kandagatla2018-12-133-0/+22
| | | | | | | | This patch adds support to device tree based quirks based on device tree compatible string. Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sun4i: Add support for Allwinner ARMv5 F1C100sMesih Kilinc2018-12-131-10/+37
| | | | | | | | | This patch adds support for suniv Allwinner ARMv5 F1C100s SoC which has stripped version of interrupt controller that found in A10/A13. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sun4i: Move IC specific register offsets to structMesih Kilinc2018-12-131-12/+21
| | | | | | | | | This patch moves IC specific register offsets to sun4i_irq_chip_data struct in order to support different chips. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/sun4i: Add a struct to hold global variablesMesih Kilinc2018-12-131-26/+38
| | | | | | | | | | In order to support different chips, IC specific data should be hold in a struct. This patch moves irq_base and irq_domain global variables to struct. Signed-off-by: Mesih Kilinc <mesihkilinc@gmail.com> Acked-by: Maxime Ripard <maxime.ripard@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip: Add RDA8810PL interrupt driverManivannan Sadhasivam2018-12-133-0/+112
| | | | | | | | | Add interrupt driver for RDA Micro RDA8810PL SoC. Signed-off-by: Andreas Färber <afaerber@suse.de> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchhip: Convert to using %pOFn instead of device_node.nameYangtao Li2018-12-133-11/+11
| | | | | | | | In preparation to remove the node name pointer from struct device_node, convert printf users to use the %pOFn format specifier. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Add support for i.MX8MQAndrey Smirnov2018-12-131-2/+29
| | | | | | | | | | | | | | | | | | Add code needed to support i.MX8MQ. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Make error messages more consistentAndrey Smirnov2018-12-131-2/+2
| | | | | | | | | | | | | | | | | | | Make error messages more consistent by making sure each starts with "%pOF:". Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Make use of BIT() macroAndrey Smirnov2018-12-131-3/+3
| | | | | | | | | | | | | | | | | | | Convert all instances of 1 << x to BIT(x) for consistency with other kernel code. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Share reg offset calculation codeAndrey Smirnov2018-12-131-8/+10
| | | | | | | | | | | | | | | | | | | Move identical offset calculation code into a small helper function and make use of it in the rest of the code. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-imx-gpcv2: Remove unused codeAndrey Smirnov2018-12-131-2/+0
| | | | | | | | | | | | | | | | | | Varaible 'reg' in imx_gpcv2_irq_set_wake() has no users. Remove it. Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: cphealy@gmail.com Cc: l.stach@pengutronix.de Cc: Leonard Crestez <leonard.crestez@nxp.com> Cc: "A.s. Dong" <aisheng.dong@nxp.com> Cc: Richard Zhu <hongxing.zhu@nxp.com> Cc: linux-imx@nxp.com Cc: linux-arm-kernel@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-renesas-intc-irqpin: Convert to SPDX identifiersKuninori Morimoto2018-12-131-13/+1
| | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-renesas-irqc: Convert to SPDX identifiersKuninori Morimoto2018-12-131-13/+1
| | | | | | | | | This patch updates license to use SPDX-License-Identifier instead of verbose license text. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Reviewed-by: Simon Horman <horms+renesas@verge.net.au> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip: bcm283x: Switch to SPDX identifierStefan Wahren2018-12-132-20/+2
| | | | | | | | | | Adopt the SPDX license identifier headers to ease license compliance management. Cc: Simon Arlott <simon@arlott.org> Cc: Eric Anholt <eric@anholt.net> Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/irq-mvebu-sei: Fix a NULL vs IS_ERR() bug in probe functionDan Carpenter2018-11-011-2/+2
| | | | | | | | | | | | | | | | | | | The devm_ioremap_resource() function never returns NULL, it returns error pointers. Fixes: 61ce8d8d8a81 ("irqchip/irq-mvebu-sei: Add new driver for Marvell SEI") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Andrew Lunn <andrew@lunn.ch> Cc: Gregory Clement <gregory.clement@bootlin.com> Cc: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Cc: Marc Zyngier <marc.zyngier@arm.com> Cc: linux-arm-kernel@lists.infradead.org Cc: kernel-janitors@vger.kernel.org Link: https://lkml.kernel.org/r/20181013102246.GD16086@mwanda
* Merge tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linuxLinus Torvalds2018-10-294-0/+491
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull C-SKY architecture port from Guo Ren: "This contains the Linux port for C-SKY(csky) based on linux-4.19 Release, which has been through 10 rounds of review on mailing list. More information: http://en.c-sky.com The development repo: https://github.com/c-sky/csky-linux ABI Documentation: https://github.com/c-sky/csky-doc Here is the pre-built cross compiler for fast test from our CI: https://gitlab.com/c-sky/buildroot/-/jobs/101608095/artifacts/file/output/images/csky_toolchain_qemu_csky_ck807f_4.18_glibc_defconfig_482b221e52908be1c9b2ccb444255e1562bb7025.tar.xz We use buildroot as our CI-test enviornment. "LTP, Lmbench ..." will be tested for every commit. See here for more details: https://gitlab.com/c-sky/buildroot/pipelines We'll continouslly improve csky subsystem in future" Arnd acks, and adds the following notes: "I did a thorough review of the ABI, which as usual mainly consists of spotting any files that don't use the asm-generic ABI itself, and having it changed to it matches exactly what we do on other new architectures. I also looked at every other patch and commented on maybe half of them where I saw something that did not quite seem right. Others have reviewed specific patches in greater depth. I'm sure that one could fine more of the minor details, but as long as they are not ABI relevant, they can be fixed later. The only patch that is part of the ABI and that nobody reviewed is the signal handling. This is one of the areas I never worked on in much detail. I did not see anything wrong with it, but I also don't know what the problems with the other architectures are here, and we seem to be hitting issues occasionally, and we never managed to generalize this enough for new architectures to have a trivial implementation. I was originally hoping that we could have the 64-bit time_t interfaces ready in time to completely drop the 32-bit ones, but that did not happen. We might still remove them in the next merge window depending on whether the libc upstream people prefer to keep them or not. One more general comment: I think this may well be the last new CPU architecture we ever add to the kernel. Both nds32 and c-sky are made by companies that also work on risc-v, and generally speaking risc-v seems to be killing off any of the minor licensable instruction set projects, just like ARM has mostly killed off the custom vendor-specific instruction sets already. If we add another architecture in the future, it may instead be something like the LLVM bitcode or WebAssembly, who knows?" To which Geert Uytterhoeven pipes in about another architecture still in the pipeline: Kalray MPPA. * tag 'csky-for-linus-4.20' of https://github.com/c-sky/csky-linux: (24 commits) dt-bindings: interrupt-controller: C-SKY APB intc irqchip: add C-SKY APB bus interrupt controller dt-bindings: interrupt-controller: C-SKY SMP intc irqchip: add C-SKY SMP interrupt controller MAINTAINERS: Add csky dt-bindings: Add vendor prefix for csky dt-bindings: csky CPU Bindings csky: Misc headers csky: SMP support csky: Debug and Ptrace GDB csky: User access csky: Library functions csky: ELF and module probe csky: Atomic operations csky: IRQ handling csky: VDSO and rt_sigreturn csky: Process management and Signal csky: MMU and page table management csky: Cache and TLB routines csky: System Call ...
| * irqchip: add C-SKY APB bus interrupt controllerGuo Ren2018-10-253-0/+283
| | | | | | | | | | | | | | | | | | | | | | | | The driver is for C-SKY APB bus interrupt controller. It's a simple interrupt controller which use pending reg to detect the irq and use enable/disable reg to mask/unmask interrupt sources. A lot of SOCs based on C-SKY CPU use the interrupt controller as root controller. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Mark Rutland <mark.rutland@arm.com>
| * irqchip: add C-SKY SMP interrupt controllerGuo Ren2018-10-253-0/+208
| | | | | | | | | | | | | | | | | | | | | | The driver is for C-SKY SMP interrupt controller. It support 16 soft-irqs, 16 private-irqs, and 992 max external-irqs, a total of 1024 interrupts. C-SKY CPU 807/810/860 SMP/non-SMP could use it. Signed-off-by: Guo Ren <ren_guo@c-sky.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
* | Merge tag 'riscv-for-linus-4.20-mw0' of ↵Linus Torvalds2018-10-261-4/+6
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux Pull RISC-V updates from Palmer Dabbelt: "This patch set contains a lot (at least, for me) of improvements to the RISC-V kernel port: - The removal of some cacheinfo values that were bogus. - On systems with F but without D the kernel will not show the F extension to userspace, as it isn't actually supported. - Support for futexes. - Removal of some unused code. - Cleanup of some menuconfig entries. - Support for systems without a floating-point unit, and for building kernels that will never use the floating-point unit. - More fixes to the RV32I port, which regressed again. It's really time to get this into a regression test somewhere so I stop breaking it. Thanks to Zong for resurrecting it again! - Various fixes that resulted from a year old review of our original patch set that I finally got around to. - Various improvements to SMP support, largely based around having switched to logical hart numbering, as well as some interrupt improvements. This one is in the same patch set as above, thanks to Atish for sheparding everything though as my patch set was a bit of a mess. I'm pretty sure this is our largest patch set since the original kernel contribution, and it's certainly the one with the most contributors. While I don't have anything else I know I'm going to submit for the merge window, I would be somewhat surprised if I didn't screw anything up. Thanks for the help, everyone!" * tag 'riscv-for-linus-4.20-mw0' of git://git.kernel.org/pub/scm/linux/kernel/git/palmer/riscv-linux: (31 commits) RISC-V: Cosmetic menuconfig changes riscv: move GCC version check for ARCH_SUPPORTS_INT128 to Kconfig RISC-V: remove the unused return_to_handler export RISC-V: Add futex support. RISC-V: Add FP register ptrace support for gdb. RISC-V: Mask out the F extension on systems without D RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} RISC-V: Show IPI stats RISC-V: Show CPU ID and Hart ID separately in /proc/cpuinfo RISC-V: Use Linux logical CPU number instead of hartid RISC-V: Add logical CPU indexing for RISC-V RISC-V: Use WRITE_ONCE instead of direct access RISC-V: Use mmgrab() RISC-V: Rename im_okay_therefore_i_am to found_boot_cpu RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartid RISC-V: Provide a cleaner raw_smp_processor_id() RISC-V: Disable preemption before enabling interrupts RISC-V: Comment on the TLB flush in smp_callin() RISC-V: Filter ISA and MMU values in cpuinfo RISC-V: Don't set cacheinfo.{physical_line_partition,attributes} ...
| * | RISC-V: Use Linux logical CPU number instead of hartidAtish Patra2018-10-231-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Setup the cpu_logical_map during boot. Moreover, every SBI call and PLIC context are based on the physical hartid. Use the logical CPU to hartid mapping to pass correct hartid to respective functions. Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Anup Patel <anup@brainfault.org> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
| * | RISC-V: Rename riscv_of_processor_hart to riscv_of_processor_hartidPalmer Dabbelt2018-10-231-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | It's a bit confusing exactly what this function does: it actually returns the hartid of an OF processor node, failing with -1 on invalid nodes. I've changed the name to _hartid() in order to make that a bit more clear, as well as adding a comment. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> [Atish: code comment formatting update] Signed-off-by: Atish Patra <atish.patra@wdc.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
* | irqchip/gic: Unify GIC priority definitionsJulien Thierry2018-10-031-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | LPIs use the same priority value as other GIC interrupts. Make the GIC default priority definition visible to ITS implementation and use this same definition for LPI priorities. Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3: Remove acknowledge loopJulien Thierry2018-10-031-34/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Multiple interrupts pending for a CPU is actually rare. Doing an acknowledge loop does not give much better performance or even can deteriorate them. Do not loop when an interrupt has been acknowledged, just return from interrupt and wait for another one to be raised. Tested-by: Daniel Thompson <daniel.thompson@linaro.org> Signed-off-by: Julien Thierry <julien.thierry@arm.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Jason Cooper <jason@lakedaemon.net> Cc: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-icu: Add support for System Error Interrupts (SEI)Miquel Raynal2018-10-021-34/+105
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the ICU only handled NSR interrupts through GICP. An SEI driver provides an MSI domain through which it is possible to raise SEI, so let's add SEI support to the ICU driver. Handle the NSR probe function in a more generic way to support other type of interrupts. Each interrupt domain is a tree domain to avoid allocation the 207 entries each time. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-sei: Add new driver for Marvell SEIMiquel Raynal2018-10-023-0/+511
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is a cascaded interrupt controller in the AP806 GIC that collapses SEIs (System Error Interrupt) coming from the AP and the CPs (through the ICU). The SEI handles up to 64 interrupts. The first 21 interrupts are wired from the AP. The next 43 interrupts are from the CPs and are triggered through MSI messages. To handle this complexity, the driver has to declare to the upper layer: one IRQ domain for the wired interrupts, one IRQ domain for the MSIs; and acts as a MSI controller ('parent') by declaring an MSI domain. Suggested-by: Haim Boot <hayim@marvell.com> Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-icu: Support ICU subnodesMiquel Raynal2018-10-021-16/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ICU can handle several type of interrupt, each of them being handled differently on AP side. On CP side, the ICU should be able to make the distinction between each interrupt group by pointing to the right parent. This is done through the introduction of new bindings, presenting the ICU node as the parent of multiple ICU sub-nodes, each of them being an interrupt type with a different interrupt parent. ICU interrupt 'clients' now directly point to the right sub-node, avoiding the need for the extra ICU_GRP_* parameter. ICU subnodes are probed automatically with devm_platform_populate(). If the node as no child, the probe function for NSRs will still be called 'manually' in order to preserve backward compatibility with DT using the old binding. Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-icu: Disociate ICU and NSRMiquel Raynal2018-10-021-25/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | NSR (non-secure interrupts) are handled in the ICU driver like if there was only this type of interrupt in the ICU. Change this behavior to prepare the introduction of SEI (System Error Interrupts) support by moving the NSR code in a separate function. This is done under the form of a 'probe' function to ease future migration to NSR/SEI being platform devices part of the ICU. The 'icu' structure is passed as driver data and not as a parameter for the same reason. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-icu: Clarify the reset operation of configured interruptsMiquel Raynal2018-10-021-2/+6
| | | | | | | | | | | | | | | | | | | | Rewrite a small section to clarify the reset operation of interrupts already configured by ATF that we want to handle in the driver. This will simplify the introduction of System Error Interrupts support. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/irq-mvebu-icu: Fix wrong private data retrievalMiquel Raynal2018-10-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The irq_domain structure has an host_data pointer that just stores private data. It is meant to not be touched by the IRQ core. However, when it comes to MSI, the MSI layer adds its own private data there with a structure that also has a host_data pointer. Because this IRQ domain is an MSI domain, to access private data we should do a d->host_data->host_data, also wrapped as 'platform_msi_get_host_data()'. This bug was lying there silently because the 'icu' structure retrieved this way was just called by dev_err(), only producing a '(NULL device *):' output on the console. Reviewed-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/pdc: Setup all edge interrupts as rising edge at GICLina Iyer2018-10-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | The PDC irqchp can convert a falling edge or level low interrupt to a rising edge or level high interrupt at the GIC. We just need to setup the GIC correctly. Set up the interrupt type for the IRQ_TYPE_EDGE_BOTH as IRQ_TYPE_EDGE_RISING at the GIC. Fixes: f55c73aef890 ("irqchip/pdc: Add PDC interrupt controller for QCOM SoCs") Reported-by: Evan Green <evgreen@chromium.org> Reviewed-by: Evan Green <evgreen@chromium.org> Signed-off-by: Lina Iyer <ilina@codeaurora.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Allow use of LPI tables in reserved memoryMarc Zyngier2018-10-021-5/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | If the LPI tables have been reserved with the EFI reservation mechanism, we assume that these tables are safe to use even when we find the redistributors to have LPIs enabled at boot time, meaning that kexec can now work with GICv3. You're welcome. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Register LPI tables with EFI config tableMarc Zyngier2018-10-021-0/+12
| | | | | | | | | | | | | | | | | | | | Upon enabling a redistributor, let's register the allocated tables with the EFI table that tracks the memory reservations. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Check that all RDs have the same property tableMarc Zyngier2018-10-021-0/+9
| | | | | | | | | | | | | | | | | | | | If booting with LPIs enabled, all the redistributors must have the exact same property table. No ifs, no buts. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Use pre-programmed redistributor tables with kdump kernelsMarc Zyngier2018-10-021-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | If using a kdump kernel, and that we cannot disable LPIs to install our own tables, let's switch to using the already allocated tables. This means that we'll change some of the initial kernel's memory, but at least we'll be able to have LPIs in this secondary kernel. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Allow use of pre-programmed LPI tablesMarc Zyngier2018-10-021-12/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In order to cope with kexec and GICv3, let's try and spot when we're booting with LPIs already enabled, and the tables already programmed into the redistributors. This code is currently guarded by a predicate that is always false, meaning this is not functionnal just yet. Reviewed-by: Julien Thierry <julien.thierry@arm.com> Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Keep track of property table's PA and VAMarc Zyngier2018-10-021-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | We're currently only tracking the page allocated to contain the property table by its struct page. In the future, it is going to be convenient to track both PA and VA for that page instead. Let's do that. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Move pending table allocation to init timeMarc Zyngier2018-10-021-28/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pending tables for the redistributors are currently allocated one at a time as each CPU boots. This is causing some grief for Linux/RT (allocation from within a CPU hotplug notifier is frown upon). Let's move this allocation to take place at init time, when we only have a single CPU. It means we're allocating memory for CPUs that are not online yet, but most system will boot all of their CPUs anyway, so that's not completely wasted. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Split property table clearing from allocationMarc Zyngier2018-10-021-7/+10
| | | | | | | | | | | | | | | | | | | | | | As we're going to reuse some pre-allocated memory for the property table, split out the zeroing of that table into a separate function for later use. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Simplify LPI_PENDBASE_SZ usageMarc Zyngier2018-10-021-7/+3
| | | | | | | | | | | | | | | | | | | | | | LPI_PENDING_SZ is always used in conjunction with a max(), which doesn't make much sense, since we're guaranteed that LPI_PENDING_SZ is already aligned to 64K. Let's remove it. Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | irqchip/gic-v3-its: Change initialization ordering for LPIsMarc Zyngier2018-10-021-8/+12
|/ | | | | | | | | | | | | | | We currently initialize the LPIs (and the ITS) fairly early, even before the SMP support and the CPU interface. This is a bit odd (as LPIs are not exactly crutial for the early boot process), and is going to cause issues when reorganizing the probing code. Let's move this initialization later. Reviewed-by: Julien Thierry <julien.thierry@arm.com> Tested-by: Jeremy Linton <jeremy.linton@arm.com> Tested-by: Bhupesh Sharma <bhsharma@redhat.com> Tested-by: Lei Zhang <zhang.lei@jp.fujitsu.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* irqchip/gic-v3-its: Cap lpi_id_bits to reduce memory footprintJia He2018-09-061-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit fe8e93504ce8 ("irqchip/gic-v3-its: Use full range of LPIs"), removes the cap for lpi_id_bits, which causes the following warning to trigger on a QDF2400 server: WARNING: CPU: 0 PID: 0 at mm/page_alloc.c:4066 __alloc_pages_nodemask ... Call trace: __alloc_pages_nodemask+0x2d8/0x1188 alloc_pages_current+0x8c/0xd8 its_allocate_prop_table+0x5c/0xb8 its_init+0x220/0x3c0 gic_init_bases+0x250/0x380 gic_acpi_init+0x16c/0x2a4 In its_alloc_lpi_tables(), lpi_id_bits is 24 in QDF2400. The allocation in allocate_prop_table() tries therefore to allocate 16M (order 12 if pagesize=4k), which triggers the warning. As said by MarcL Capping lpi_id_bits at 16 (which is what we had before) is plenty, will save a some memory, and gives some margin before we need to push it up again. Bring the upper limit of lpi_id_bits back to prevent Fixes: fe8e93504ce8 ("irqchip/gic-v3-its: Use full range of LPIs") Suggested-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Jia He <jia.he@hxt-semitech.com> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Acked-by: Marc Zyngier <marc.zyngier@arm.com> Tested-by: Olof Johansson <olof@lixom.net> Cc: Jason Cooper <jason@lakedaemon.net> Cc: linux-arm-kernel@lists.infradead.org Link: https://lkml.kernel.org/r/1535432006-2304-1-git-send-email-jia.he@hxt-semitech.com
* Merge branch 'irq-urgent-for-linus' of ↵Linus Torvalds2018-08-265-17/+25
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip Pull irq update from Thomas Gleixner: "A small set of updats/fixes for the irq subsystem: - Allow GICv3 interrupts to be configured as wake-up sources to enable wakeup from suspend - Make the error handling of the STM32 irqchip init function work - A set of small cleanups and improvements" * 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: irqchip/gic-v3: Allow interrupt to be configured as wake-up sources irqchip/tango: Set irq handler and data in one go dt-bindings: irqchip: renesas-irqc: Document r8a774a1 support irqchip/s3c24xx: Remove unneeded comparison of unsigned long to 0 irqchip/stm32: Fix init error handling irqchip/bcm7038-l1: Hide cpu offline callback when building for !SMP
| * Merge tag 'irqchip-4.19-2' of ↵Thomas Gleixner2018-08-245-17/+25
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into irq/urgent Pull irqchip updates for 4.19, take #2 from Marc Zyngier: - bcm7038: compilation fix for !SMP - stm32: fix teardown on probe error - s3c24xx: fix compilation warning - renesas-irqc: r8a774a1 support - tango: chained irq setup simplification - gic-v3: allow wake-up sources
| | * irqchip/gic-v3: Allow interrupt to be configured as wake-up sourcesMarc Zyngier2018-08-201-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although GICv3 doesn't directly offers support for wake-up interrupts and relies on external HW for this, it shouldn't prevent the driver for such HW from doing it work. Let's set the required flags on the irq_chip structures. Reported-by: Lina Iyer <ilina@codeaurora.org> Tested-by: Lina Iyer <ilina@codeaurora.org> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| | * irqchip/tango: Set irq handler and data in one goMartin Kaiser2018-08-201-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | Replace the two separate calls for setting the irq handler and data with a single irq_set_chained_handler_and_data() call. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| | * irqchip/s3c24xx: Remove unneeded comparison of unsigned long to 0Krzysztof Kozlowski2018-08-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | irq_data->hwirq is unsigned long. This fixes GCC warning: drivers/irqchip/irq-s3c24xx.c: In function 's3c_irqext0_type': drivers/irqchip/irq-s3c24xx.c:253:19: warning: comparison of unsigned expression >= 0 is always true [-Wtype-limits] if ((data->hwirq >= 0) && (data->hwirq <= 3)) { ^~ Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| | * irqchip/stm32: Fix init error handlingDan Carpenter2018-08-131-12/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there are any errors in stm32_exti_host_init() then it leads to a NULL dereference in the callers. The function should clean up after itself. Fixes: f9fc1745501e ("irqchip/stm32: Add host and driver data structures") Reviewed-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
| | * irqchip/bcm7038-l1: Hide cpu offline callback when building for !SMPJonas Gorski2018-08-131-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When compiling bmips with SMP disabled, the build fails with: drivers/irqchip/irq-bcm7038-l1.o: In function `bcm7038_l1_cpu_offline': drivers/irqchip/irq-bcm7038-l1.c:242: undefined reference to `irq_set_affinity_locked' make[5]: *** [vmlinux] Error 1 Fix this by adding and setting bcm7038_l1_cpu_offline only when actually compiling for SMP. It wouldn't have been used anyway, as it requires CPU_HOTPLUG, which in turn requires SMP. Fixes: 34c535793bcb ("irqchip/bcm7038-l1: Implement irq_cpu_offline() callback") Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
* | | Merge tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensaLinus Torvalds2018-08-222-4/+0
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull Xtensa updates from Max Filippov: - switch xtensa arch to the generic noncoherent direct mapping operations - add support for DMA_ATTR_NO_KERNEL_MAPPING attribute - clean up users of platform/hardware.h in generic Xtensa code - fix assembly cache maintenance code for long cache lines - rework noMMU cache attributes initialization - add big-endian HiFi2 test_kc705_be CPU variant * tag 'xtensa-20180820' of git://github.com/jcmvbkbc/linux-xtensa: xtensa: add test_kc705_be variant xtensa: clean up boot-elf/bootstrap.S xtensa: make bootparam parsing optional xtensa: drop variant IRQ support xtensa: drop unneeded platform/hardware.h headers xtensa: move PLATFORM_NR_IRQS to Kconfig xtensa: rework {CONFIG,PLATFORM}_DEFAULT_MEM_START xtensa: drop unused {CONFIG,PLATFORM}_DEFAULT_MEM_SIZE xtensa: rework noMMU cache attributes initialization xtensa: increase ranges in ___invalidate_{i,d}cache_all xtensa: limit offsets in __loop_cache_{all,page} xtensa: platform-specific handling of coherent memory xtensa: support DMA_ATTR_NO_KERNEL_MAPPING attribute xtensa: use generic dma_noncoherent_ops
| * | | xtensa: drop variant IRQ supportMax Filippov2018-08-202-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If an xtensa core provides an additional IRQ controller it should be treated as a separate piece of hardware and be driven by an irqchip driver. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-02-05 00:41:24 +0100