summaryrefslogtreecommitdiffstats
path: root/drivers/leds/leds-pca9532.c (unfollow)
Commit message (Expand)AuthorFilesLines
2014-08-08drm/i915: No busy-loop wait_for in the ring init codeDaniel Vetter1-2/+2
2014-08-08drm/i915: Add sprite watermark programming for VLV and CHVGajanan Bhat2-6/+36
2014-08-08drm/i915: Round-up clock and limit drain latencyGajanan Bhat1-1/+4
2014-08-08drm/i915: Generalize drain latency computationGajanan Bhat2-37/+51
2014-08-08drm/i915: Free pending page flip events at .preclose()Ville Syrjälä3-0/+26
2014-08-08drm/i915: clean up PPGTT checking logicJesse Barnes3-14/+2
2014-08-08drm/i915: Polish the chv cmnlane resrt macrosVille Syrjälä2-9/+6
2014-08-08drm/i915: Hack to tie both common lanes together on chvVille Syrjälä1-2/+12
2014-08-08drm/i915: Add cherryview_update_wm()Ville Syrjälä1-1/+80
2014-08-08drm/i915: Update DDL only for current CRTCGajanan Bhat1-16/+9
2014-08-08drm/i915: Parametrize VLV_DDL registersVille Syrjälä2-70/+36
2014-08-08drm/i915: Fill out the FWx watermark register definesVille Syrjälä2-19/+130
2014-08-08drm: Resetting rotation propertySonika Jindal1-1/+8
2014-08-08drm/i915: Add rotation property for spritesVille Syrjälä1-1/+40
2014-08-08drm: Add rotation_property to mode_configSonika Jindal1-0/+1
2014-08-08drm/i915: Make intel_plane_restore() return an errorVille Syrjälä2-8/+8
2014-08-08drm/i915: Add 180 degree sprite rotation supportVille Syrjälä3-0/+42
2014-08-08drm/i915: Introduce a for_each_intel_encoder() macroDamien Lespiau6-49/+31
2014-08-08drm/i915: Demote the DRRS messages to debug messagesDamien Lespiau1-3/+3
2014-08-08drm/i915: remove duplicate register definesPaulo Zanoni1-2/+0
2014-08-08drm/i915: Remove now useless comments about the translation valuesDamien Lespiau1-5/+5
2014-08-08drm/i915/bdw: Remove the HDMI/DVI entry from the DP/eDP/FDI tablesDamien Lespiau1-3/+0
2014-08-08drm/i915/bdw: Provide the BDW specific HDMI buffer translation tableDamien Lespiau1-5/+23
2014-08-08drm/i915: Gather the HDMI level shifter logic into one placeDamien Lespiau3-9/+24
2014-08-08drm/i915: Introduce FBC False Color for debug purposes.Rodrigo Vivi4-0/+48
2014-08-08drm/i915: Align intel_dsi*.c files a bitDaniel Vetter3-17/+17
2014-08-08drm/i915: Add support for Video Burst Mode for MIPI DSIShobhit Kumar5-17/+57
2014-08-08drm/i915: Clarify CHV swing margin/deemph bitsVille Syrjälä3-6/+10
2014-08-08drm/i915: Call intel_{dp, hdmi}_prepare for chvVille Syrjälä2-0/+4
2014-08-08drm/i915: Split chv_update_pll() apartVille Syrjälä1-11/+19
2014-08-08drm/i915: Leave DPLL ref clocks onVille Syrjälä1-1/+1
2014-08-08drm/i915: Disable cdclk changes for chv until Punit is readyVille Syrjälä1-0/+8
2014-08-08drm/i915: Add cdclk change support for chvVille Syrjälä2-2/+52
2014-08-08d rm/i915: freeze display before the interrupts and GTPaulo Zanoni1-1/+1
2014-08-08drm/i915: Make ddi_clock_gate() HSW/BDW specificDaniel Vetter1-3/+9
2014-08-08drm/i915: Split the CDCLK retrieval per-platformDamien Lespiau1-17/+38
2014-08-08drm/i915: Make intel_ddi_calculate_wrpll() HSW/BDW specificDamien Lespiau1-7/+8
2014-08-08drm/i915: Split the BDW/HSW specific shared pll selectionDamien Lespiau1-16/+23
2014-08-08drm/i915: Fix stale comment for intel_ddi_pll_select()Damien Lespiau1-4/+5
2014-08-08drm/i915: Restrict hsw_dp_set_ddi_pll_sel() to HSW/BDWDamien Lespiau1-1/+1
2014-08-08drm/i915: Extract the HSW/BDW shared dpll init codeDamien Lespiau1-3/+9
2014-08-08drm/i915: Extract the HSW DDI selection code into its own functionDamien Lespiau1-10/+17
2014-08-08drm/i915: Add a space to the shared DPLL debug messageDamien Lespiau1-1/+1
2014-08-08drm/i915: Specify when the PLL hw state fields are validDamien Lespiau1-0/+3
2014-08-08drm/i915: Add DP training pattern 3 for CHVVille Syrjälä2-4/+16
2014-08-08drm/i915: Split a few long debug printsVille Syrjälä1-2/+4
2014-08-08drm/i915: Fix read back of plane stride registerRafael Barbalho1-2/+2
2014-08-08drm/i915: Add chv port D TX wellsVille Syrjälä2-0/+27
2014-08-08drm/i915: Add chv port B and C TX wellsVille Syrjälä1-0/+30
2014-08-08drm/i915: Add per-pipe power wells for chvVille Syrjälä2-0/+138
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-07 09:58:23 +0100