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* mailbox: imx: use device name in interrupt namePeng Fan2024-09-231-3/+3
| | | | | | | | | | There are several MUs for different usage, SCMI MU, ELE MU, RemotePROC MU. Using "imx_mu_chan" in interrupt name would be hard to identify which MU triggers interrupt, so use device name to make it easy to know which MU triggers which interrupt. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: fix TXDB_V2 channel race conditionPeng Fan2024-07-101-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Two TXDB_V2 channels are used between Linux and System Manager(SM). Channel0 for normal TX, Channel 1 for notification completion. The TXDB_V2 trigger logic is using imx_mu_xcr_rmw which uses read/modify/update logic. Note: clear MUB GSR BITs, the MUA side GCR BITs will also got cleared per hardware design. Channel0 Linux read GCR->modify GCR->write GCR->M33 SM->read GSR----->clear GSR |-(1)-| Channel1 Linux start in time slot(1) read GCR->modify GCR->write GCR->M33 SM->read GSR->clear GSR So Channel1 read GCR will read back the GCR that Channel0 wrote, because M33 has not finish clear GSR, this means Channel1 GCR writing will trigger Channel1 and Channel0 interrupt both which is wrong. Channel0 will be freed(SCMI channel status set to FREE) in M33 SM when processing the 1st Channel0 interrupt. So when 2nd interrupt trigger (channel 0/1 trigger together), SM will see a freed Channel0, and report protocol error. To address the issue, not using read/modify/update logic, just use write, because write 0 to GCR will be ignored. And after write MUA GCR, wait the SM to clear MUB GSR by looping MUA GCR value. Fixes: 5bfe4067d350 ("mailbox: imx: support channel type tx doorbell v2") Reviewed-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: Convert from tasklet to BH workqueueAllen Pais2024-05-201-8/+8
| | | | | | | | | | | | | | The only generic interface to execute asynchronously in the BH context is tasklet; however, it's marked deprecated and has some design flaws. To replace tasklets, BH workqueue support was recently added. A BH workqueue behaves similarly to regular workqueues except that the queued work items are executed in the BH context. Based on the work done by Tejun Heo <tj@kernel.org> Branch: https://git.kernel.org/pub/scm/linux/kernel/git/tj/wq.git for-6.10 Signed-off-by: Allen Pais <allen.lkml@gmail.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: support i.MX95 Generic/ELE/V2X MUPeng Fan2024-03-111-0/+3
| | | | | | | | | | | Add i.MX95 Generic/ELE/V2X MU support, its register layout is same as i.MX8ULP, but the Parameter registers would show different TR/RR. Since the driver already supports get TR/RR from Parameter registers, not hardcoding the number, this patch just add the compatible entry to reuse i.MX8ULP S4 cfg data. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: populate sub-nodesPeng Fan2024-03-111-0/+3
| | | | | | | | Some MUs such as i.MX95 MU, have internal SRAM which could be used for SCMI shared memory, so populate the sub-nodes to use the SRAM. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: get RR/TR registers num from Parameter registerPeng Fan2024-03-111-11/+36
| | | | | | | | | | | | | | | | i.MX8ULP, i.MX93 MU has a Parameter register encoded as below: BIT: 15 --- 8 | 7 --- 0 RR_NUM TR_NUM So to make driver easy to support more variants, get the RR/TR registers number from Parameter register. The patch only adds support the specific MU, such as ELE MU. For generic MU, not add support for number larger than 4. Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: support return value of initPeng Fan2024-03-111-11/+24
| | | | | | | | | There will be changes that init may fail, so adding return value for init function. Reviewed-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jassisinghbrar@gmail.com>
* mailbox: imx: Convert to platform remove callback returning voidUwe Kleine-König2024-01-141-4/+2
| | | | | | | | | | | | | | | | | | The .remove() callback for a platform driver returns an int which makes many driver authors wrongly assume it's possible to do error handling by returning an error code. However the value returned is ignored (apart from emitting a warning) and this typically results in resource leaks. To improve here there is a quest to make the remove callback return void. In the first step of this quest all drivers are converted to .remove_new(), which already returns void. Eventually after all drivers are converted, .remove_new() will be renamed to .remove(). Trivially convert this driver from always returning zero in the remove callback to the void returning variant. Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: support channel type tx doorbell v2Peng Fan2023-10-151-3/+29
| | | | | | | | | | | | | | | The Message Unit(MU) General Purpose Control registers are used for TX doorbell, but there is no hardware ACK support. The current TX doorbell channel is using tasklet to emulate hardware ACK support to kick the TX tick from controller driver side. The new added TX doorbell channel V2 not using tasklet to emulate the hardware ACK support. The behavior for the channel is just writing the GCR register, and no else. This will be used for SCMI mailbox. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Explicitly include correct DT includesRob Herring2023-09-051-1/+2
| | | | | | | | | | | | | | The DT of_device.h and of_platform.h date back to the separate of_platform_bus_type before it as merged into the regular platform bus. As part of that merge prepping Arm DT support 13 years ago, they "temporarily" include each other. They also include platform_device.h and of.h. As a result, there's a pretty much random mix of those include files used throughout the tree. In order to detangle these headers and replace the implicit includes with struct declarations, users need to explicitly include the correct includes. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: fix RST channel supportPeng Fan2022-10-061-5/+5
| | | | | | | | | | | Because IMX_MU_xCR_MAX was increased to 5, some mu cfgs were not updated to include the CR register. Add the missed CR register to xcr array. Fixes: 82ab513baed5 ("mailbox: imx: support RST channel") Reported-by: Liu Ying <victor.liu@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Tested-by: Liu Ying <victor.liu@nxp.com> # i.MX8qm/qxp MEK boards boot Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: clear pending interruptsPeng Fan2022-08-031-0/+11
| | | | | | | | | | | During MU initialization, there maybe pending GSR and RSR pending interrupt, clear them to avoid unexpected kernel dump when requesting mailbox channel Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: support RST channelPeng Fan2022-08-021-6/+23
| | | | | | | | | | | | | i.MX generic MU supports MU-A/B reset feature. When stop/start remotecore, MU is not reset. So when Linux stop remotecore, the MU-B side BCR may contain valid configuration, because MU-B is not reset. So when linux start Mcore again and notify Mcore, Mcore is not ready to handle MU interrupt and cause issues. So need reset MU when stop Mcore. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox:imx: using pm_runtime_resume_and_getran jianping2022-05-211-4/+2
| | | | | | | | | | Using pm_runtime_resume_and_get() to replace pm_runtime_get_sync and pm_runtime_put_noidle. This change is just to simplify the code, no actual functional changes. Reported-by: Zeal Robot <zealci@zte.com.cn> Signed-off-by: ran jianping <ran.jianping@zte.com.cn> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: remove redundant initializerTom Rix2022-05-211-1/+0
| | | | | | | | | | | | | Smatch reports this issue imx-mailbox.c:887:10: warning: Initializer entry defined twice imx-mailbox.c:889:10: also defined here .rxdb = imx_mu_generic_rxdb, Is listed twice, so remove one. Signed-off-by: Tom Rix <trix@redhat.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: support i.MX93 S401 MUPeng Fan2022-03-131-0/+12
| | | | | | | Add i.MX93 S401 MU cfg Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: support dual interruptsPeng Fan2022-03-131-15/+30
| | | | | | | | | | i.MX93 S401 MU support two interrupts: tx empty and rx full. - Introduce a new flag IMX_MU_V2_IRQ for the dual interrupt case - Update Copyright Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: extend irq to an arrayPeng Fan2022-03-131-7/+7
| | | | | | | | To i.MX93 S401 MU, there are two interrupts: rx full and tx empty. So extend irq to an array to prepare i.MX93 S401 MU support. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: add i.MX8 SECO MU supportFranck LENORMAND2022-03-131-1/+212
| | | | | | | | | | | | | | | | | | | i.MX8/8X SECO firmware IPC is an implementation of passing messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX, four RX and a TXDB to support IPC to SECO firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SECO MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg of any size, limited by hardcoded value of 30. Signed-off-by: Franck LENORMAND <franck.lenormand@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: introduce rxdb callbackPeng Fan2022-03-131-3/+17
| | | | | | | | Add a rxdb callback to prepare for i.MX8 SECO MU rxdb which has a different logic. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: enlarge timeout while reading/writing messages to SCFWRanjani Vaidyanathan2022-03-131-2/+3
| | | | | | | | | | | | | | | | | | Mailbox driver needs to wait and read all the words in response to a SCFW API call, else the protocol gets messed up and results in kernel hang. When the responses are longer than 3 words its possible that SCFW will take some time to fill up the rest of the words in the MU, a timeout of 100us is arbritrary and too short. While waiting for Linux to consume the first 3 words of the response SCFW can be busy doing other stuff and hence Linux needs to wait for the rest of the words. Similar restriction applies when writing messages that are longer than 3 words. This patch increases the timeout to 5secs while waiting for response or writing long messages to SCFW. Signed-off-by: Ranjani Vaidyanathan <ranjani.vaidyanathan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: fix crash in resume on i.mx8ulpRobin Gong2022-03-131-1/+1
| | | | | | | | | | | check 'priv->clk' before 'imx_mu_read()' otherwise crash happens on i.mx8ulp, since clock not enabled. Fixes: 4f0b776ef5831 ("mailbox: imx-mailbox: support i.MX8ULP MU") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: fix wakeup failure from freeze modeRobin Gong2022-03-131-0/+9
| | | | | | | | | | | | | Since IRQF_NO_SUSPEND used for imx mailbox driver, that means this irq can't be used for wakeup source so that can't wakeup from freeze mode. Add pm_system_wakeup() to wakeup from freeze mode. Fixes: b7b2796b9b31e("mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flag") Reviewed-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Robin Gong <yibin.gong@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Fix an IS_ERR() vs NULL bugDan Carpenter2022-01-121-2/+2
| | | | | | | | | | The devm_kzalloc() function does not return error pointers, it returns NULL on failure. Fixes: 97961f78e8bc ("mailbox: imx: support i.MX8ULP S4 MU") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: support i.MX8ULP S4 MUPeng Fan2021-10-301-37/+87
| | | | | | | | | | | | | | Like i.MX8 SCU, i.MX8ULP S4 also has vendor specific protocol. - bind SCU/S4 MU part to share one tx/rx/init API to make code simple. - S4 msg max size is very large, so alloc the space at driver probe, not use local on stack variable. - S4 MU has 8 TR and 4 RR which is different with i.MX8 MU, so adapt code to reflect this. Tested on i.MX8MP, i.MX8ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Avoid using val uninitialized in imx_mu_isr()Nathan Chancellor2021-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns: drivers/mailbox/imx-mailbox.c:284:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/mailbox/imx-mailbox.c:288:7: note: uninitialized use occurs here if (!val) ^~~ drivers/mailbox/imx-mailbox.c:263:9: note: initialize the variable 'val' to silence this warning u32 val, ctrl; ^ = 0 1 warning generated. Prior to commit 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array"), val was always initialized in imx_mu_isr() but now, it is not initialized in the default case. Return IRQ_NONE like the statement below does and add a message that there is an unhandled type for this switch statement so that it can be updated. Fixes: 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array") Link: https://github.com/ClangBuiltLinux/linux/issues/1404 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx-mailbox: support i.MX8ULP MUPeng Fan2021-06-261-41/+63
| | | | | | | | | | | | | i.MX8ULP MU has different register layout and bit layout compared with i.MX6SX/7ULP/8. So add enum imx_mu_type to show it is IMX_MU_V2 or IMX_MU_V1. For IMX_MU_V2 mu hardware, check it when calculating bit offset to get the correct offset. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: add xSR/xCR register arrayPeng Fan2021-06-261-35/+61
| | | | | | | | | We are going to add a new platform which has 4 status registers(SR, TSR, RSR, GSR) and 4 control registers(CR, TCR, RCR, GCR), so extend xSR and xCR to register array and adapt code to use it. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: replace the xTR/xRR array with single registerPeng Fan2021-06-261-14/+14
| | | | | | | | | The xTR/xRR registers are using 4 bytes stride and continuous. Considering we will support more TR and RR registers, use base + idx * 4 method to calculate register address, not hardcoding in driver. Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Mark PM functions as __maybe_unusedNathan Chancellor2020-08-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PM and CONFIG_PM_SLEEP are unset, the following warnings occur: drivers/mailbox/imx-mailbox.c:638:12: warning: 'imx_mu_runtime_resume' defined but not used [-Wunused-function] 638 | static int imx_mu_runtime_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:629:12: warning: 'imx_mu_runtime_suspend' defined but not used [-Wunused-function] 629 | static int imx_mu_runtime_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:611:12: warning: 'imx_mu_resume_noirq' defined but not used [-Wunused-function] 611 | static int imx_mu_resume_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:601:12: warning: 'imx_mu_suspend_noirq' defined but not used [-Wunused-function] 601 | static int imx_mu_suspend_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ Mark these functions as __maybe_unused, which is the standard procedure for PM functions. Fixes: bb2b2624dbe2 ("mailbox: imx: Add runtime PM callback to handle MU clocks") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flagAnson Huang2020-06-071-2/+7
| | | | | | | | | | | | | | | | | | IPC MU has no power domain assigned and there could be IPC during noirq suspend phase, so IRQF_NO_SUSPEND flag is needed for IPC MU. However, for other MUs, they have power domain assigned and their power will be turned off during noirq suspend phase, but with IRQF_NO_SUSPEND set, their interrupts are NOT disabled even after their power turned off, it will cause system crash when mailbox driver trys to handle pending interrupts but the MU power is already turned off. So, IRQF_NO_SUSPEND flag should ONLY be added to IPC MU which has power domain managed by SCU, then all other MUs' pending interrupts after noirq suspend phase will be handled after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add runtime PM callback to handle MU clocksAnson Huang2020-06-071-3/+29
| | | | | | | | | | | | | | | | | | | | | | Some of i.MX8M SoCs have MU clock, they need to be managed in runtime to make sure the MU clock can be off in runtime, add runtime PM callback to handle MU clock. And on i.MX8MP, the MU clock is combined with power domain and runtime PM is enabled for the clock driver, during noirq suspend/resume phase, runtime PM is disabled by device suspend, but the MU context save/restore needs to enable MU clock for register access, calling clock prepare/enable will trigger runtime resume failure and lead to system suspend failed. Actually, the MU context save/restore is ONLY necessary for SCU IPC MU, other MUs especially on i.MX8MP platforms which have MU clock assigned, they need to runtime request/free mailbox channel in the consumer driver, so no need to save/restore MU context for them, hence it can avoid this issue, so the MU context save/restore is ONLY applied to i.MX platforms MU instance without clock present. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add context save/restore for suspend/resumeDong Aisheng2020-06-071-0/+35
| | | | | | | | | | | | | | | | | For "mem" mode suspend on i.MX8 SoCs, MU settings could be lost because its power is off, so save/restore is needed for MU settings during suspend/resume. However, the restore can ONLY be done when MU settings are actually lost, for the scenario of settings NOT lost in "freeze" mode suspend, since there could be still IPC going on multiple CPUs, restoring the MU settings could overwrite the TIE by mistake and cause system freeze, so need to make sure ONLY restore the MU settings when it is powered off, Anson fixes this by checking whether restore is actually needed when resume. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx-mailbox: fix scu msg header size checkPeng Fan2020-05-311-5/+9
| | | | | | | | | | | | The i.MX8 SCU message header size is the number of "u32" elements, not "u8", so fix the check. Reported-by: coverity-bot <keescook+coverity-bot@chromium.org> Addresses-Coverity-ID: 1461658 ("Memory - corruptions") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Disable the clock on devm_mbox_controller_register() failureFabio Estevam2020-05-311-1/+3
| | | | | | | | | | | | devm_mbox_controller_register() may fail, and in the case of failure the priv->clk clock that was previously enabled, should be disabled. Fixes: 2bb7005696e2 ("mailbox: Add support for i.MX messaging unit") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> [Jassi: fixed merge/am conflict] Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Fix return in imx_mu_scu_xlate()Dan Carpenter2020-05-301-1/+1
| | | | | | | | | This called from mbox_request_channel(). The caller is expecting error pointers and not NULL so this "return NULL;" will lead to an Oops. Fixes: 0a67003b1985 ("mailbox: imx: add SCU MU support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Support runtime PMAnson Huang2020-05-301-1/+26
| | | | | | | | | | | | | | | | | | | | | Some power hungry sub-systems like VPU has its own MUs which also use mailbox driver, current mailbox driver uses platform driver model and MU's power will be ON after driver probed and left ON there, it may cause the whole sub-system can NOT enter lower power mode, take VPU driver for example, it has runtime PM support, but due to its MU always ON, the VPU sub-system will be always ON and consume many power during kernel idle. To save power in kernel idle, mailbox driver needs to support runtime PM in order to power off MU when it is unused. However, the runtime suspend/resume can ONLY be implemented in mailbox's .shutdown/.startup callback, so its consumer needs to call mbox_request_channel()/mbox_free_channel() in consumer driver's runtime PM callback, then the MU's power will be ON/OFF along with consumer's runtime PM status. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: add SCU MU supportPeng Fan2020-03-201-0/+155
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | i.MX8/8X SCU MU is dedicated for communication between SCU and Cortex-A cores from hardware design, and could not be reused for other purpose. Per i.MX8/8X Reference mannual, Chapter "12.9.2.3.2 Messaging Examples", Passing short messages: Transmit register(s) can be used to pass short messages from one to four words in length. For example, when a four-word message is desired, only one of the registers needs to have its corresponding interrupt enable bit set at the receiver side; the message’s first three words are written to the registers whose interrupt is masked, and the fourth word is written to the other register (which triggers an interrupt at the receiver side). i.MX8/8X SCU firmware IPC is an implementation of passing short messages. But current imx-mailbox driver only support one word message, i.MX8/8X linux side firmware has to request four TX and four RX to support IPC to SCU firmware. This is low efficent and more interrupts triggered compared with one TX and one RX. To make SCU MU work, - parse the size of msg. - Only enable TR0/RR0 interrupt for transmit/receive message. - For TX/RX, only support one TX channel and one RX channel - For RX, support receive msg larger than 4 u32 words. - Support 6 channels, TX0/RX0/RXDB[0-3], not support TXDB. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: restructure code to make easy for new MUPeng Fan2020-03-201-54/+83
| | | | | | | | | | | | | | | | Add imx_mu_generic_tx for data send and imx_mu_generic_rx for interrupt data receive. Pack original mu chans related code into imx_mu_init_generic Add tx/rx/init hooks into imx_mu_dcfg With these, it will be a bit easy to introduce i.MX8/8X SCU type MU dedicated to communicate with SCU. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: add support for imx v1 muRichard Zhu2019-12-011-17/+38
| | | | | | | | | | | | | | | | There is a version 1.0 MU on i.MX7ULP platform. One new version ID register is added, and it's offset is 0. TRn registers are defined at the offset 0x20 ~ 0x2C. RRn registers are defined at the offset 0x40 ~ 0x4C. SR/CR registers are defined at 0x60/0x64. Extend this driver to support it. Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Clear the right interrupts at shutdownDaniel Baluta2019-12-011-2/+13
| | | | | | | | | | | Make sure to only clear enabled interrupts keeping count of the connection type. Suggested-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Fix Tx doorbell shutdown pathDaniel Baluta2019-12-011-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tx doorbell is handled by txdb_tasklet and doesn't have an associated IRQ. Anyhow, imx_mu_shutdown ignores this and tries to free an IRQ that wasn't requested for Tx DB resulting in the following warning: [ 1.967644] Trying to free already-free IRQ 26 [ 1.972108] WARNING: CPU: 2 PID: 157 at kernel/irq/manage.c:1708 __free_irq+0xc0/0x358 [ 1.980024] Modules linked in: [ 1.983088] CPU: 2 PID: 157 Comm: kworker/2:1 Tainted: G [ 1.993524] Hardware name: Freescale i.MX8QXP MEK (DT) [ 1.998668] Workqueue: events deferred_probe_work_func [ 2.003812] pstate: 60000085 (nZCv daIf -PAN -UAO) [ 2.008607] pc : __free_irq+0xc0/0x358 [ 2.012364] lr : __free_irq+0xc0/0x358 [ 2.016111] sp : ffff00001179b7e0 [ 2.019422] x29: ffff00001179b7e0 x28: 0000000000000018 [ 2.024736] x27: ffff000011233000 x26: 0000000000000004 [ 2.030053] x25: 000000000000001a x24: ffff80083bec74d4 [ 2.035369] x23: 0000000000000000 x22: ffff80083bec7588 [ 2.040686] x21: ffff80083b1fe8d8 x20: ffff80083bec7400 [ 2.046003] x19: 0000000000000000 x18: ffffffffffffffff [ 2.051320] x17: 0000000000000000 x16: 0000000000000000 [ 2.056637] x15: ffff0000111296c8 x14: ffff00009179b517 [ 2.061953] x13: ffff00001179b525 x12: ffff000011142000 [ 2.067270] x11: ffff000011129f20 x10: ffff0000105da970 [ 2.072587] x9 : 00000000ffffffd0 x8 : 0000000000000194 [ 2.077903] x7 : 612065657266206f x6 : ffff0000111e7b09 [ 2.083220] x5 : 0000000000000003 x4 : 0000000000000000 [ 2.088537] x3 : 0000000000000000 x2 : 00000000ffffffff [ 2.093854] x1 : 28b70f0a2b60a500 x0 : 0000000000000000 [ 2.099173] Call trace: [ 2.101618] __free_irq+0xc0/0x358 [ 2.105021] free_irq+0x38/0x98 [ 2.108170] imx_mu_shutdown+0x90/0xb0 [ 2.111921] mbox_free_channel.part.2+0x24/0xb8 [ 2.116453] mbox_free_channel+0x18/0x28 This bug is present from the beginning of times. Cc: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Signed-off-by: Richard Zhu <hongxing.zhu@nxp.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Clear GIEn bit at shutdownDaniel Baluta2019-07-111-2/+2
| | | | | | | | | | GIEn is enabled at startup for RX doorbell mailboxes so we need to clear the bit at shutdown in order to avoid leaving the interrupt line enabled. Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com> Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: use devm_platform_ioremap_resource() to simplify codeAnson Huang2019-05-091-3/+1
| | | | | | | | | | Use the new helper devm_platform_ioremap_resource() which wraps the platform_get_resource() and devm_ioremap_resource() together, to simplify the code. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Reviewed-by: Mukesh Ojha <mojha@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: keep MU irq working during suspend/resumeAnson Huang2019-03-111-2/+2
| | | | | | | | | | | | | | | | | | | | During noirq suspend phase, mailbox MU irq will be masked but many drivers still need to communicate with system controller firmware via mailbox, if MU irq is masked, it will cause RPC timeout as below: [ 23.372103] imx-scu scu: RPC send msg timeout Setting MU irq to be wakeup source is NOT working as GIC driver does NOT have .irq_set_wake implemented, so to support suspend/resume, just make imx mailbox driver NOT suspend, since MU is always a wakeup source on i.MX platforms with system controller inside, and its power/clock is maintained by system controller, mailbox driver no need to manage them. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Use device-managed registration APIThierry Reding2018-12-211-2/+1
| | | | | | | | | Get rid of some boilerplate driver removal code by using the newly added device-managed registration API. Reviewed-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Thierry Reding <treding@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Add support for i.MX messaging unitOleksij Rempel2018-08-151-0/+358
The i.MX Messaging Unit is a two side block which allows applications implement communication over this sides. The MU includes the following features: - Messaging control by interrupts or by polling - Four general-purpose interrupt requests reflected to the other side - Three general-purpose flags reflected to the other side - Four receive registers with maskable interrupt - Four transmit registers with maskable interrupt Reviewed-by: Vladimir Zapolskiy <vz@mleia.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 02:49:05 +0100