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* mailbox: imx: support i.MX8ULP S4 MUPeng Fan2021-10-301-37/+87
| | | | | | | | | | | | | | Like i.MX8 SCU, i.MX8ULP S4 also has vendor specific protocol. - bind SCU/S4 MU part to share one tx/rx/init API to make code simple. - S4 msg max size is very large, so alloc the space at driver probe, not use local on stack variable. - S4 MU has 8 TR and 4 RR which is different with i.MX8 MU, so adapt code to reflect this. Tested on i.MX8MP, i.MX8ULP Signed-off-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Move bulk of PCCT parsing into pcc_mbox_probeSudeep Holla2021-10-301-58/+66
| | | | | | | | | Move the PCCT subspace parsing and allocation into pcc_mbox_probe so that we can get rid of global PCC channel and mailbox controller data. It also helps to make use of devm_* APIs for all the allocations. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Add support for PCCT extended PCC subspaces(type 3/4)Sudeep Holla2021-10-301-17/+109
| | | | | | | | | With all the plumbing in place to avoid accessing PCCT type and other fields directly from the PCCT table all the time, let us now add the support for extended PCC subspaces(type 3 and 4). Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Drop handling invalid bit-width in {read,write}_registerSudeep Holla2021-10-301-20/+4
| | | | | | | | | | | pcc_chan_reg_init now checks if the register bit width is within the list [8, 16, 32, 64] and flags error if that is not the case. Therefore there is no need to handling invalid bit-width in both read_register and write_register. We can drop that along with the return values for these 2 functions. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Avoid accessing PCCT table in pcc_send_data and pcc_mbox_irqSudeep Holla2021-10-301-87/+32
| | | | | | | | | | | | | | | Now that the con_priv is availvale solely for PCC mailbox controller driver, let us use the same to save the channel specific information in it so that we can it whenever required instead of parsing the PCCT table entries every time in both pcc_send_data and pcc_mbox_irq. We can now use the newly introduces PCC register bundle to simplify both saving of channel specific information and accessing them without repeated checks for the subspace type. Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Add PCC register bundle and associated accessor functionsSudeep Holla2021-10-301-0/+90
| | | | | | | | | | | | | | | | | Extended PCC subspaces introduces more registers into the PCCT. In order to consolidate access to these registers and to keep all the details contained in one place, let us introduce PCC register bundle that holds the ACPI Generic Address Structure as well as the virtual address for the same if it is mapped in the OS. It also contains the various masks used to access the register and the associated read, write and read-modify-write accessors. We can also clean up the initialisations by having a helper function for the same. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Rename doorbell ack to platform interrupt ack registerSudeep Holla2021-10-301-16/+17
| | | | | | | | | The specification refers this register and associated bitmask as platform interrupt acknowledge register. Let us rename it so that it is easier to map and understand. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Use PCC mailbox channel pointer instead of standardSudeep Holla2021-10-301-45/+18
| | | | | | | | | | | | | | | | | | | | | | Now that we have all the shared memory region information populated in the pcc_mbox_chan, let us propagate the pointer to the same as the return value to pcc_mbox_request channel. This eliminates the need for the individual users of PCC mailbox to parse the PCCT subspace entries and fetch the shmem information. This also eliminates the need for PCC mailbox controller to set con_priv to PCCT subspace entries. This is required as con_priv is private to the controller driver to attach private data associated with the channel and not meant to be used by the mailbox client/users. Let us convert all the users of pcc_mbox_{request,free}_channel to use new interface. Cc: Jean Delvare <jdelvare@suse.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Wolfram Sang <wsa@kernel.org> Acked-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Add pcc_mbox_chan structure to hold shared memory region infoSudeep Holla2021-10-301-0/+27
| | | | | | | | | | | | | | | | | | | | | | Currently PCC mailbox controller sets con_priv in each channel to hold the pointer to pcct subspace entry it corresponds to. The mailbox user will then fetch this pointer from the channel descriptor they get when they request for the channel. Using that pointer they then parse the pcct entry again to fetch all the information about shared memory region. In order to remove individual users of PCC mailbox parsing the PCCT subspace entries to fetch same information, let us consolidate the same in pcc mailbox controller by parsing all the shared memory region information into a structure that can also hold the mbox_chan pointer it represent. This can then be used as main PCC mailbox channel pointer that we can return as part of pcc_mbox_request_channel instead of standard mailbox channel pointer. Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Consolidate subspace doorbell register parsingSudeep Holla2021-10-301-8/+23
| | | | | | | | | | | | | Extended PCC subspaces(Type 3 and 4) differ from generic(Type 0) and HW-Reduced Communication(Type 1 and 2) subspace structures. However some fields share same offsets and same type of structure can be use to extract the fields. In order to simplify that, let us move all the doorbell register parsing into pcc_parse_subspace_db_reg and consolidate there. It will be easier to extend it if required within the same. Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Consolidate subspace interrupt information parsingSudeep Holla2021-10-301-19/+19
| | | | | | | | | | | | | Extended PCC subspaces(Type 3 and 4) differ from generic(Type 0) and HW-Reduced Communication(Type 1 and 2) subspace structures. However some fields share same offsets and same type of structure can be use to extract the fields. In order to simplify that, let us move all the IRQ related information parsing into pcc_parse_subspace_irq and consolidate there. It will be easier to extend it if required within the same. Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Refactor all PCC channel information into a structureSudeep Holla2021-10-301-53/+54
| | | | | | | | | | | | | | | Currently all the PCC channel specific information are stored/maintained in global individual arrays for each of those information. It is not scalable and not clean if we have to stash more channel specific information. Couple of reasons to stash more information are to extend the support to Type 3/4 PCCT subspace and also to avoid accessing the PCCT table entries themselves each time we need the information. This patch moves all those PCC channel specific information into a separate structure pcc_chan_info. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Fix kernel doc warningsSudeep Holla2021-10-301-1/+5
| | | | | | | | | | | | | | | | | Kernel doc validation script is unhappy and complains with the below set of warnings. | drivers/mailbox/pcc.c:179: warning: Function parameter or member 'irq' | not described in 'pcc_mbox_irq' | drivers/mailbox/pcc.c:179: warning: Function parameter or member 'p' | not described in 'pcc_mbox_irq' | drivers/mailbox/pcc.c:378: warning: expecting prototype for | parse_pcc_subspaces(). Prototype was for parse_pcc_subspace() instead Fix it. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: apple: Add driver for Apple mailboxesSven Peter2021-10-303-0/+398
| | | | | | | | | Apple SoCs such as the M1 come with various co-processors. Mailboxes are used to communicate with those. This driver adds support for two variants of those mailboxes. Signed-off-by: Sven Peter <sven@svenpeter.dev> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Fix local clock ID usageFei Shao2021-10-191-5/+3
| | | | | | | | | | | | | | In the probe function, the clock IDs were pointed to local variables which should only be used in the same code block, and any access to them after the probing stage becomes an use-after-free case. Since there are only limited variants of the gce clock names so far, we can just declare them as static constants to fix the issue. Fixes: 85dfdbfc13ea ("mailbox: cmdq: add multi-gce clocks support for mt8195") Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@google.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Validate alias_id on probeFei Shao2021-10-191-1/+1
| | | | | | | | | | | of_alias_get_id() may return -ENODEV which leads to illegal access to the cmdq->clocks array. Adding a check over alias_id to prevent the unexpected behavior. Fixes: 85dfdbfc13ea ("mailbox: cmdq: add multi-gce clocks support for mt8195") Signed-off-by: Fei Shao <fshao@chromium.org> Reviewed-by: Tzung-Bi Shih <tzungbi@google.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Remove WARN_ON for async_cb.cb in cmdq_exec_donejason-jh.lin2021-10-161-1/+0
| | | | | | | | | | | | | Because mtk_drm_crtc_update_config is not using cmdq_pkt_flush_async, it won't have pkt->async_cb.cb anymore. So remove the WARN_ON check of pkt->async_cb.cb at cmdq_exec_done. Fixes: 1b6b0ce2240e ("mailbox: mtk-cmdq: Use mailbox rx_callback") Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Tested-by: Enric Balletbo i Serra <enric.balletbo@collabora.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-apcs-ipc: Add QCM2290 APCS IPC supportShawn Guo2021-10-161-0/+1
| | | | | | | | Enable QCM2290 APCS IPC support by adding the compatible. It reuses msm8994_apcs_data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-apcs-ipc: Consolidate msm8994 type apcs_dataShawn Guo2021-10-161-21/+5
| | | | | | | | | The msm8994 type of apcs_data is defined multiple times with different SoC name encoded. Consolidate them on msm8994 and remove the data duplication. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: xgene-slimpro: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sun6i: Make use of the helper function devm_platform_ioremap_resource()Cai Huoqing2021-10-161-8/+1
| | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sti: Make use of the helper function devm_platform_ioremap_resource()Cai Huoqing2021-10-161-3/+1
| | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-apcs-ipc: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: platform-mhu: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: omap: Make use of the helper function devm_platform_ioremap_resource()Cai Huoqing2021-10-161-3/+1
| | | | | | | | | Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: hi6220: Make use of the helper function ↵Cai Huoqing2021-10-161-5/+2
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: hi3660: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: bcm2835: Make use of the helper function ↵Cai Huoqing2021-10-161-3/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: altera: Make use of the helper function ↵Cai Huoqing2021-10-161-4/+1
| | | | | | | | | | | devm_platform_ioremap_resource() Use the devm_platform_ioremap_resource() helper instead of calling platform_get_resource() and devm_ioremap_resource() separately Signed-off-by: Cai Huoqing <caihuoqing@baidu.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: add multi-gce clocks support for mt8195jason-jh.lin2021-09-011-22/+79
| | | | | | | | | | | | | | | | For the design of GCE hardware event signal transportation, evnet rx will send the event signal to all GCE event merges after receiving the event signal from the other hardware. Because GCE event merges need to response to event rx, their clocks must be enabled at that time. To make sure all the gce clock is enabled while receiving the hardware event, each cmdq mailbox should enable or disable the others gce clk at the same time. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: add mediatek mailbox support for mt8195jason-jh.lin2021-09-011-0/+1
| | | | | | | Add mt8195 compatible name in the driver data of cmdq mailbox driver. Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-apcs-ipc: Add compatible for MSM8953 SoCVladimir Lypak2021-08-301-0/+1
| | | | | | | | | MSM8953 has an APCS block similar to MSM8916 but with different clocks which are spread over 2MB IO region next to it. Signed-off-by: Vladimir Lypak <junak.pub@gmail.com> Signed-off-by: Sireesh Kodali <sireeshkodali@protonmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add support for SM6115 APCS IPCIskren Chernev2021-08-301-0/+1
| | | | | | | | Qcom SM4250/6115, have APCS mailbox setup similar to msm8998 and msm8916. Signed-off-by: Iskren Chernev <iskren.chernev@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* soc: mediatek: cmdq: add address shift in jumpYongqiang Niu2021-08-301-1/+2
| | | | | | | | | | Add address shift when compose jump instruction to compatible with 35bit format. Fixes: 0858fde496f8 ("mailbox: cmdq: variablize address shift in platform") Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-by: Nicolas Boichat <drinkcat@chromium.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: add mt8192 supportYongqiang Niu2021-08-301-0/+10
| | | | | | | | add mt8192 support Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Hsin-Yi Wang <hsinyi@chromium.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-ipcc: Enable loading QCOM_IPCC as a moduleAmit Pundir2021-08-302-1/+2
| | | | | | | | | | | | | | This patch enables the qcom_ipcc driver to be loaded as a module. IPCC is fairly core to system, so as such it should never be unloaded. It registers as a mailbox + irq controller and the irq controller drivers in kernel are not supposed to be unloaded as they don't have the visibility over the clients consuming the irqs. Hence adding supress_bind_attrs to disable bind/unbind via sysfs. Signed-off-by: Amit Pundir <amit.pundir@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sti: quieten kernel-doc warningsRandy Dunlap2021-08-301-8/+8
| | | | | | | | | | | | | | | | | | | | | | Use kernel-doc struct notation for the mailbox structs to prevent these kernel-doc warnings: drivers/mailbox/mailbox-sti.c:39: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox device data drivers/mailbox/mailbox-sti.c:63: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox platform specific configuration drivers/mailbox/mailbox-sti.c:74: warning: This comment starts with '/**', but isn't a kernel-doc comment. Refer Documentation/doc-guide/kernel-doc.rst * STi Mailbox allocated channel information Also move the field descriptions ahead of the function description as is expected in kernel-doc. This prevents another kernel-doc warning. Fixes: 9ef4546cbd7e ("mailbox: Add support for ST's Mailbox IP") Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Reported-by: kernel test robot <lkp@intel.com> Cc: Aditya Srivastava <yashsri421@gmail.com> Cc: Lee Jones <lee.jones@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mbox: add polarfire soc system controller mailboxConor Dooley2021-06-263-0/+265
| | | | | | | | This driver adds support for the single mailbox channel of the MSS system controller on the Microchip PolarFire SoC. Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Avoid using val uninitialized in imx_mu_isr()Nathan Chancellor2021-06-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clang warns: drivers/mailbox/imx-mailbox.c:284:2: warning: variable 'val' is used uninitialized whenever switch default is taken [-Wsometimes-uninitialized] default: ^~~~~~~ drivers/mailbox/imx-mailbox.c:288:7: note: uninitialized use occurs here if (!val) ^~~ drivers/mailbox/imx-mailbox.c:263:9: note: initialize the variable 'val' to silence this warning u32 val, ctrl; ^ = 0 1 warning generated. Prior to commit 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array"), val was always initialized in imx_mu_isr() but now, it is not initialized in the default case. Return IRQ_NONE like the statement below does and add a message that there is an unhandled type for this switch statement so that it can be updated. Fixes: 91c8c1fbe498 ("mailbox: imx: add xSR/xCR register array") Link: https://github.com/ClangBuiltLinux/linux/issues/1404 Signed-off-by: Nathan Chancellor <nathan@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add MSM8939 APCS supportShawn Guo2021-06-261-0/+1
| | | | | | | | Enable MSM8939 APCS support by adding the compatible. It reuses msm8916_apcs_data. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Use PLATFORM_DEVID_AUTO to register platform deviceShawn Guo2021-06-261-1/+1
| | | | | | | | | | | | | | | | | | | | | In adding APCS clock support for MSM8939, the second clock registration fails due to duplicate device name like below. [ 0.519657] sysfs: cannot create duplicate filename '/bus/platform/devices/qcom-apcs-msm8916-clk' ... [ 0.661158] qcom_apcs_ipc b111000.mailbox: failed to register APCS clk This is because MSM8939 has 3 APCS instances for Cluster0 (little cores), Cluster1 (big cores) and CCI (Cache Coherent Interconnect). Although only APCS of Cluster0 and Cluster1 have IPC bits, each of 3 APCS has A53PLL clock control bits. That said, 3 'qcom-apcs-msm8916-clk' devices need to be registered to instantiate all 3 clocks. Use PLATFORM_DEVID_AUTO rather than PLATFORM_DEVID_NONE for platform_device_register_data() call to fix the issue above. Signed-off-by: Shawn Guo <shawn.guo@linaro.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-apcs: Add SM6125 compatibleMartin Botka2021-06-261-0/+5
| | | | | | | This commit adds compatible for the SM6125 SoC Signed-off-by: Martin Botka <martin.botka@somainline.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Fix uninitialized variable in cmdq_mbox_flush()Dan Carpenter2021-06-261-1/+1
| | | | | | | | | The "cb" pointer needs to be initialized before can assign "data.data = cb->data;". Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: bcm-flexrm-mailbox: Remove redundant dev_err call in ↵Zhihao Cheng2021-06-261-1/+0
| | | | | | | | | | | | flexrm_mbox_probe() There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: bcm2835: Remove redundant dev_err call in bcm2835_mbox_probe()Zhihao Cheng2021-06-261-1/+0
| | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Zhihao Cheng <chengzhihao1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom-ipcc: Fix IPCC mbox channel exhaustionSibi Sankar2021-06-261-0/+6
| | | | | | | | | | | | | | | | | Fix IPCC (Inter-Processor Communication Controller) channel exhaustion by setting the channel private data to NULL on mbox shutdown. Err Logs: remoteproc: MBA booted without debug policy, loading mpss remoteproc: glink-edge: failed to acquire IPC channel remoteproc: failed to probe subdevices for remoteproc: -16 Fixes: fa74a0257f45 ("mailbox: Add support for Qualcomm IPCC") Signed-off-by: Sibi Sankar <sibis@codeaurora.org> Cc: stable@vger.kernel.org Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Add struct cmdq_pkt in struct cmdq_cb_dataChun-Kuang Hu2021-06-261-0/+2
| | | | | | | | | | Current client use 'struct cmdq_pkt' as callback data, so change 'void *data' to 'struct cmdq_pkt *pkt'. Keep data until client use pkt instead of data. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: mtk-cmdq: Use mailbox rx_callbackChun-Kuang Hu2021-06-261-5/+9
| | | | | | | | | | | | rx_callback is a standard mailbox callback mechanism and could cover the function of proprietary cmdq_task_cb, so use the standard one instead of the proprietary one. But the client driver has already used cmdq_task_cb, so keep cmdq_task_cb until all client driver use rx_callback instead of cmdq_task_cb. Signed-off-by: Chun-Kuang Hu <chunkuang.hu@kernel.org> Reviewed-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 04:57:33 +0100