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* Merge tag 'mailbox-v5.13' of ↵Linus Torvalds2021-04-299-53/+119
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/landing-teams/working/fujitsu/integration Pull mailbox updates from Jassi Brar: "qcom: - enable support for SM8350 and SC7280 sprd: - refcount channel usage - specify interrupt names in dt - support sc9863a arm: - drop redundant print ti: - convert dt-bindings to json schema and misc spelling fixes" * tag 'mailbox-v5.13' of git://git.linaro.org/landing-teams/working/fujitsu/integration: dt-bindings: mailbox: qcom-ipcc: Add compatible for SC7280 dt-bindings: mailbox: ti,secure-proxy: Convert to json schema mailbox: arm_mhu_db: Remove redundant dev_err call in mhu_db_probe() mailbox: sprd: Add supplementary inbox support dt-bindings: mailbox: Add interrupt-names to SPRD mailbox mailbox: sprd: Introduce refcnt when clients requests/free channels MAINTAINERS: Add DT bindings directory to mailbox mailbox: fix various typos in comments mailbox: pcc: fix platform_no_drv_owner.cocci warnings dt-bindings: mailbox: Add compatible for SM8350 IPCC
| * mailbox: arm_mhu_db: Remove redundant dev_err call in mhu_db_probe()Qiheng Lin2021-04-141-3/+1
| | | | | | | | | | | | | | | | | | | | There is a error message within devm_ioremap_resource already, so remove the dev_err call to avoid redundant error message. Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Qiheng Lin <linqiheng@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: sprd: Add supplementary inbox supportOrson Zhai2021-04-141-17/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some sensors connected to Unisoc mailbox will send data very frequently. This makes channel 0 very busy and the messages from other remote cores not able to be handled as soon as possible. It's a trick (un-documented) from Unisoc ASIC designers to resolve this special requirement that an inbox assigned to one of the remote cores before was modified to be exposed to host cpu core. Then from host side, a supplementary inbox is added for transferring mass but not emergency messages from the remote cores, such as step counting sensor, with an independent FIFO and interrupt which is as same as channel 0. Meanwihle, inbox part of this channel is still kept for original remote core to use. Signed-off-by: Orson Zhai <orson.zhai@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: sprd: Introduce refcnt when clients requests/free channelsOrson Zhai2021-04-141-14/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unisoc mailbox has no way to be enabled/disabled for any single channel. They can only be set to startup or shutdown as a whole device at same time. Add a variable to count references to avoid mailbox FIFO being reset unexpectedly when clients are requesting or freeing channels. Also add a lock to dismiss possible conflicts from register r/w in different startup or shutdown threads. And fix the crash problem when early interrupts come from channel which has not been requested by client yet. Fixes: ca27fc26cd22 ("mailbox: sprd: Add Spreadtrum mailbox driver") Signed-off-by: Orson Zhai <orson.zhai@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: fix various typos in commentsTom Saeger2021-04-148-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix trivial typos in mailbox driver comments. s/Intergrated/Integrated/ s/extenstion/extension/ s/atleast/at least/ s/commnunication/communication/ s/assgined/assigned/ s/commnunication/communication/ s/recevied/received/ s/succeded/succeeded/ s/implmentation/implementation/ s/definiation/definition/ s/traget/target/ s/wont/won't/ Cc: trivial@kernel.org Signed-off-by: Tom Saeger <tom.saeger@oracle.com> Reviewed-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
| * mailbox: pcc: fix platform_no_drv_owner.cocci warningsYang Li2021-04-141-1/+0
| | | | | | | | | | | | | | | | | | | | | | ./drivers/mailbox/pcc.c:580:3-8: No need to set .owner here. The core will do it. Remove .owner field if calls are used which set it automatically Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Yang Li <yang.lee@linux.alibaba.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | treewide: change my e-mail address, fix my nameMarek Behún2021-04-091-2/+2
|/ | | | | | | | | | | | | | | Change my e-mail address to kabel@kernel.org, and fix my name in non-code parts (add diacritical mark). Link: https://lkml.kernel.org/r/20210325171123.28093-2-kabel@kernel.org Signed-off-by: Marek Behún <kabel@kernel.org> Cc: Bartosz Golaszewski <bgolaszewski@baylibre.com> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Cc: Jassi Brar <jassisinghbrar@gmail.com> Cc: Linus Walleij <linus.walleij@linaro.org> Cc: Pavel Machek <pavel@ucw.cz> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mailbox: arm_mhuv2: Skip calling kfree() with invalid pointerViresh Kumar2021-02-221-1/+3
| | | | | | | | | | | | | It is possible that 'data' passed to kfree() is set to a error value instead of allocated space. Make sure it doesn't get called with invalid pointer. Fixes: 5a6338cce9f4 ("mailbox: arm_mhuv2: Add driver") Cc: v5.11 <stable@vger.kernel.org> # v5.11 Reported-by: kernel test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: tegra-hsp: Set lockdep class dynamicallyMikko Perttunen2021-02-151-0/+15
| | | | | | | | | | On Tegra194, due to both BPMP and TCU using mailboxes, we get a lockdep spew at boot. Both are using different instances of HSP, so this is harmless. As such give each HSP instance a different lockdep class. Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sprd: correct definition of SPRD_OUTBOX_FIFO_FULLMagnum Shan2021-02-151-1/+1
| | | | | | | | | | | According to the specification, bit[2] represents SPRD_OUTBOX_FIFO_FULL, not bit[0], so correct it. Fixes: ca27fc26cd22 ("mailbox: sprd: Add Spreadtrum mailbox driver") Signed-off-by: Magnum Shan <magnum.shan@unisoc.com> Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com> Reviewed-by: Baolin Wang <baolin.wang7@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: arm_mhuv2: make remove callback return voidUwe Kleine-König2021-02-151-3/+1
| | | | | | | | | | | | My build tests failed to catch that amba driver that would have needed adaption in commit 3fd269e74f2f ("amba: Make the remove callback return void"). Change the remove function to make the driver build again. Reported-by: kernel test robot <lkp@intel.com> Fixes: 3fd269e74f2f ("amba: Make the remove callback return void") Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de> Acked-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: arm_mhuv2: Fix sparse warningsViresh Kumar2021-02-151-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a bunch of sparse warnings in the newly added arm_mhuv2 driver. drivers/mailbox/arm_mhuv2.c:506:24: warning: incorrect type in argument 1 (different address spaces) drivers/mailbox/arm_mhuv2.c:506:24: expected void const volatile [noderef] __iomem *addr drivers/mailbox/arm_mhuv2.c:506:24: got unsigned int [usertype] * drivers/mailbox/arm_mhuv2.c:547:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:547:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:547:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:625:42: warning: incorrect type in argument 2 (different address spaces) drivers/mailbox/arm_mhuv2.c:625:42: expected unsigned int [usertype] *reg drivers/mailbox/arm_mhuv2.c:625:42: got unsigned int [noderef] __iomem * drivers/mailbox/arm_mhuv2.c:972:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:973:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:993:25: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1026:24: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1027:22: warning: dereference of noderef expression drivers/mailbox/arm_mhuv2.c:1048:17: warning: dereference of noderef expression Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add support for SDX55 APCS IPCManivannan Sadhasivam2021-02-151-1/+6
| | | | | | | | | In SDX55, the IPC bits are located in the APCS GCC block. Also, this block can provide clock functionality. Hence, add support for IPC with correct offset and name of the clock provider. Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: omap: Add support for K3 AM64x SoCsSuman Anna2021-02-151-1/+5
| | | | | | | | | | | | | | | | The AM64x SoC contains a Mailbox IP instance with multiple clusters in the MAIN domain, and is a variant of the IP on current AM65x and J721E SoCs. The AM64x SoC has only 8 clusters with no interrupts routed to the A53 core on the first 2 clusters. The interrupt outputs from the IP do not go through any Interrupt Routers and are hard-wired to each processor, with only couple of interrupts from each cluster reaching the A53 core. The IP is also not built with the K3 safety feature in hardware. Add the support for this IP through a new compatible. Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add SC8180X apcs compatibleBjorn Andersson2021-02-151-0/+1
| | | | | | | | The Qualcomm SC8180X platform has a APSS block exposing the usual IPC bits, add a compatible for this. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: arm_mhuv2: Add driverViresh Kumar2020-12-103-0/+1145
| | | | | | | | | | | | | | | | | | | This adds driver for the ARM MHUv2 (Message Handling Unit) mailbox controller. This is based on the accepted DT bindings of the controller and supports combination of both transport protocols, i.e. doorbell and data-transfer. Transmitting and receiving data through the mailbox framework is done through struct arm_mhuv2_mbox_msg. Based on the initial work done by Morten Borup Petersen from ARM. Co-developed-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Signed-off-by: Tushar Khandelwal <tushar.khandelwal@arm.com> Tested-by: Usama Arif <usama.arif@arm.com> Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: cast void pointers to unsigned longMartin Kaiser2020-12-021-6/+6
| | | | | | | | | | | | | | | | | | | | Now that the driver can be enabled by COMPILE_TEST, we see warnings on 64bit platforms when void pointers are cast to unsigned int (and vice versa). warning: cast to smaller integer type 'unsigned int' from 'void *' unsigned int chan = (unsigned int)link->con_priv; ... warning: cast to 'void *' from smaller integer type 'unsigned int' ipcc->controller.chans[i].con_priv = (void *)i; Update these casts to use unsigned long variables, which are the same size as pointers on all platforms. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: remove duplicate error messageMartin Kaiser2020-12-021-3/+0
| | | | | | | | | platform_get_irq_byname already prints an error message if the requested irq was not found. Don't print another message in the driver. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: stm32-ipcc: add COMPILE_TEST dependencyMartin Kaiser2020-12-021-1/+1
| | | | | | | | | This allows compiling the driver on architectures where the hardware is not available. Most other mailbox drivers support this as well. Signed-off-by: Martin Kaiser <martin@kaiser.cx> Reviewed-by: Fabien Dessenne <fabien.dessenne@st.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: arm_mhu_db: Fix mhu_db_shutdown by replacing kfree with devm_kfreeSudeep Holla2020-12-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mhu_db_channel info is allocated per channel using devm_kzalloc from mhu_db_mbox_xlate which gets called from mbox_request_channel. However we are releasing the allocated mhu_db_channel info using plain kfree from mhu_db_shutdown which is called from mbox_free_channel. This leads to random crashes when the channel is freed like below one: Unable to handle kernel paging request at virtual address 0080000400000008 [0080000400000008] address between user and kernel address ranges Internal error: Oops: 96000044 [#1] PREEMPT SMP Modules linked in: scmi_module(-) CPU: 1 PID: 2212 Comm: rmmod Not tainted 5.10.0-rc5 #31 Hardware name: ARM LTD ARM Juno Development Platform/ARM Juno Development Platform, BIOS EDK II Nov 19 2020 pstate: 20000085 (nzCv daIf -PAN -UAO -TCO BTYPE=--) pc : release_nodes+0x74/0x230 lr : devres_release_all+0x40/0x68 Call trace: release_nodes+0x74/0x230 devres_release_all+0x40/0x68 device_release_driver_internal+0x12c/0x1f8 driver_detach+0x58/0xe8 bus_remove_driver+0x64/0xe0 driver_unregister+0x38/0x68 platform_driver_unregister+0x1c/0x28 scmi_driver_exit+0x38/0x44 [scmi_module] __arm64_sys_delete_module+0x188/0x260 el0_svc_common.constprop.0+0x80/0x1a8 do_el0_svc+0x2c/0x98 el0_sync_handler+0x160/0x168 el0_sync+0x174/0x180 Code: 1400000d eb07009f 54000460 f9400486 (f90004a6) ---[ end trace c55ffd306c140233 ]--- Fix it by replacing kfree with devm_kfree as required. Fixes: 7002ca237b21 ("mailbox: arm_mhu: Add ARM MHU doorbell driver") Reported-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Cristian Marussi <cristian.marussi@arm.com> Reviewed-by: Cristian Marussi <cristian.marussi@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2020-10-241-1/+8
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC-related driver updates from Olof Johansson: "Various driver updates for platforms. A bulk of this is smaller fixes or cleanups, but some of the new material this time around is: - Support for Nvidia Tegra234 SoC - Ring accelerator support for TI AM65x - PRUSS driver for TI platforms - Renesas support for R-Car V3U SoC - Reset support for Cortex-M4 processor on i.MX8MQ There are also new socinfo entries for a handful of different SoCs and platforms" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (131 commits) drm/mediatek: reduce clear event soc: mediatek: cmdq: add clear option in cmdq_pkt_wfe api soc: mediatek: cmdq: add jump function soc: mediatek: cmdq: add write_s_mask value function soc: mediatek: cmdq: add write_s value function soc: mediatek: cmdq: add read_s function soc: mediatek: cmdq: add write_s_mask function soc: mediatek: cmdq: add write_s function soc: mediatek: cmdq: add address shift in jump soc: mediatek: mtk-infracfg: Fix kerneldoc soc: amlogic: pm-domains: use always-on flag reset: sti: reset-syscfg: fix struct description warnings reset: imx7: add the cm4 reset for i.MX8MQ dt-bindings: reset: imx8mq: add m4 reset reset: Fix and extend kerneldoc reset: reset-zynqmp: Added support for Versal platform dt-bindings: reset: Updated binding for Versal reset driver reset: imx7: Support module build soc: fsl: qe: Remove unnessesary check in ucc_set_tdm_rxtx_clk soc: fsl: qman: convert to use be32_add_cpu() ...
| * firmware: tegra: Enable BPMP support on Tegra234Thierry Reding2020-09-181-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable support for the BPMP on Tegra234 to avoid relying on Tegra194 being enabled to pull in the needed OF device ID table entry. On simulation platforms the BPMP hasn't booted up yet by the time we probe the BPMP driver and the BPMP hasn't had a chance to mark the doorbell as ringable by the CCPLEX. This corresponding check in the BPMP driver will therefore fail. Work around this by disabling the check on simulation platforms. Reviewed-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | mailbox: avoid timer start from callbackJassi Brar2020-10-171-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the txdone is done by polling, it is possible for msg_submit() to start the timer while txdone_hrtimer() callback is running. If the timer needs recheduling, it could already be enqueued by the time hrtimer_forward_now() is called, leading hrtimer to loudly complain. WARNING: CPU: 3 PID: 74 at kernel/time/hrtimer.c:932 hrtimer_forward+0xc4/0x110 CPU: 3 PID: 74 Comm: kworker/u8:1 Not tainted 5.9.0-rc2-00236-gd3520067d01c-dirty #5 Hardware name: Libre Computer AML-S805X-AC (DT) Workqueue: events_freezable_power_ thermal_zone_device_check pstate: 20000085 (nzCv daIf -PAN -UAO BTYPE=--) pc : hrtimer_forward+0xc4/0x110 lr : txdone_hrtimer+0xf8/0x118 [...] This can be fixed by not starting the timer from the callback path. Which requires the timer reloading as long as any message is queued on the channel, and not just when current tx is not done yet. Fixes: 0cc67945ea59 ("mailbox: switch to hrtimer for tx_complete polling") Reported-by: Da Xue <da@libre.computer> Reviewed-by: Sudeep Holla <sudeep.holla@arm.com> Tested-by: Sudeep Holla <sudeep.holla@arm.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Tested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | maiblox: mediatek: Fix handling of platform_get_irq() errorKrzysztof Kozlowski2020-10-131-5/+3
| | | | | | | | | | | | | | | | | | platform_get_irq() returns -ERRNO on error. In such case casting to u32 and comparing to 0 would pass the check. Fixes: 623a6143a845 ("mailbox: mediatek: Add Mediatek CMDQ driver") Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: arm_mhu: Add ARM MHU doorbell driverSudeep Holla2020-10-132-1/+355
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MHU drives the signal using a 32-bit register, with all 32 bits logically ORed together. The MHU provides a set of registers to enable software to set, clear, and check the status of each of the bits of this register independently. The use of 32 bits for each interrupt line enables software to provide more information about the source of the interrupt. For example, each bit of the register can be associated with a type of event that can contribute to raising the interrupt. This patch adds a separate the MHU controller driver for doorbel mode of operation using the extended DT binding to add support the same. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: arm_mhu: Match only if compatible is "arm,mhu"Sudeep Holla2020-10-131-0/+3
| | | | | | | | | | | | | | | | | | | | | | Since we will be soon adding a separate driver based on this ARM MHU driver to support doorbell mode, let us add explicit check to match the default compatible for this driver. This is needed as the probe and match reuses the AMBA device ids currently and don't have any explicit compatible check. Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* | mailbox: bcm: convert tasklets to use new tasklet_setup() APIAllen Pais2020-10-131-3/+3
|/ | | | | | | | | | | In preparation for unconditionally passing the struct tasklet_struct pointer to all tasklet callbacks, switch to using the new tasklet_setup() and from_tasklet() to pass the tasklet pointer explicitly. Signed-off-by: Romain Perier <romain.perier@gmail.com> Signed-off-by: Allen Pais <allen.lkml@gmail.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* iomap: constify ioreadX() iomem argument (as in generic implementation)Krzysztof Kozlowski2020-08-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Patch series "iomap: Constify ioreadX() iomem argument", v3. The ioread8/16/32() and others have inconsistent interface among the architectures: some taking address as const, some not. It seems there is nothing really stopping all of them to take pointer to const. This patch (of 4): The ioreadX() and ioreadX_rep() helpers have inconsistent interface. On some architectures void *__iomem address argument is a pointer to const, on some not. Implementations of ioreadX() do not modify the memory under the address so they can be converted to a "const" version for const-safety and consistency among architectures. [krzk@kernel.org: sh: clk: fix assignment from incompatible pointer type for ioreadX()] Link: http://lkml.kernel.org/r/20200723082017.24053-1-krzk@kernel.org [akpm@linux-foundation.org: fix drivers/mailbox/bcm-pdc-mailbox.c] Link: http://lkml.kernel.org/r/202007132209.Rxmv4QyS%25lkp@intel.com Suggested-by: Geert Uytterhoeven <geert@linux-m68k.org> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Reviewed-by: Arnd Bergmann <arnd@arndb.de> Cc: Richard Henderson <rth@twiddle.net> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Matt Turner <mattst88@gmail.com> Cc: "James E.J. Bottomley" <James.Bottomley@HansenPartnership.com> Cc: Helge Deller <deller@gmx.de> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Paul Mackerras <paulus@samba.org> Cc: Yoshinori Sato <ysato@users.sourceforge.jp> Cc: Rich Felker <dalias@libc.org> Cc: Kalle Valo <kvalo@codeaurora.org> Cc: "David S. Miller" <davem@davemloft.net> Cc: Jakub Kicinski <kuba@kernel.org> Cc: Dave Jiang <dave.jiang@intel.com> Cc: Jon Mason <jdmason@kudzu.us> Cc: Allen Hubbe <allenbh@gmail.com> Cc: "Michael S. Tsirkin" <mst@redhat.com> Cc: Jason Wang <jasowang@redhat.com> Link: http://lkml.kernel.org/r/20200709072837.5869-1-krzk@kernel.org Link: http://lkml.kernel.org/r/20200709072837.5869-2-krzk@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* mailbox: mediatek: cmdq: clear task in channel before shutdownDennis YC Hsieh2020-08-041-0/+38
| | | | | | | | | | Do success callback in channel when shutdown. For those task not finish, callback with error code thus client has chance to cleanup or reset. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: support mt6779 gce platform definitionDennis YC Hsieh2020-08-041-0/+2
| | | | | | | | | | Add gce v4 hardware support with different thread number and shift. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Reviewed-by: CK Hu <ck.hu@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Bibby Hsieh <bibby.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: cmdq: variablize address shift in platformDennis YC Hsieh2020-08-041-13/+44
| | | | | | | | | | Some gce hardware shift pc and end address in register to support large dram addressing. Implement gce address shift when write or read pc and end register. And add shift bit in platform definition. Signed-off-by: Dennis YC Hsieh <dennis-yc.hsieh@mediatek.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add msm8994 apcs compatibleKonrad Dybcio2020-08-041-0/+5
| | | | | | | | | | | MSM8994 has an APCS block similar to 8916, but with a different clock driver due to the former one having 2 clusters. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Acked-by: Rob Herring <robh@kernel.org> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add sdm660 hmss compatibleKonrad Dybcio2020-08-041-0/+5
| | | | | | | | | | The Qualcomm SDM660 platform has a APCS HMSS GLOBAL block, add the compatible for this. Signed-off-by: Konrad Dybcio <konradybcio@gmail.com> Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Mark PM functions as __maybe_unusedNathan Chancellor2020-08-041-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When CONFIG_PM and CONFIG_PM_SLEEP are unset, the following warnings occur: drivers/mailbox/imx-mailbox.c:638:12: warning: 'imx_mu_runtime_resume' defined but not used [-Wunused-function] 638 | static int imx_mu_runtime_resume(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:629:12: warning: 'imx_mu_runtime_suspend' defined but not used [-Wunused-function] 629 | static int imx_mu_runtime_suspend(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:611:12: warning: 'imx_mu_resume_noirq' defined but not used [-Wunused-function] 611 | static int imx_mu_resume_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~ drivers/mailbox/imx-mailbox.c:601:12: warning: 'imx_mu_suspend_noirq' defined but not used [-Wunused-function] 601 | static int imx_mu_suspend_noirq(struct device *dev) | ^~~~~~~~~~~~~~~~~~~~ Mark these functions as __maybe_unused, which is the standard procedure for PM functions. Fixes: bb2b2624dbe2 ("mailbox: imx: Add runtime PM callback to handle MU clocks") Signed-off-by: Nathan Chancellor <natechancellor@gmail.com> Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: Put the PCCT table for error pathHanjun Guo2020-08-041-2/+7
| | | | | | | | | | | | | The acpi_get_table() should be coupled with acpi_put_table() if the mapped table is not used at runtime to release the table mapping. In acpi_pcc_probe(), the PCCT table entries will be used as private data for communication chan at runtime, but the table should be put for error path. Signed-off-by: Hanjun Guo <guohanjun@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Replace HTTP links with HTTPS onesAlexander A. Klimov2020-08-042-2/+2
| | | | | | | | | | | | | | | | | | | | Rationale: Reduces attack surface on kernel devs opening the links for MITM as HTTPS traffic is much harder to manipulate. Deterministic algorithm: For each file: If not .svg: For each line: If doesn't contain `\bxmlns\b`: For each link, `\bhttp://[^# \t\r\n]*(?:\w|/)`: If neither `\bgnu\.org/license`, nor `\bmozilla\.org/MPL\b`: If both the HTTP and HTTPS versions return 200 OK and serve the same content: Replace HTTP with HTTPS. Signed-off-by: Alexander A. Klimov <grandmaster@al2klimov.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add ipq6018 apcs compatibleSivaprakash Murugesan2020-06-111-0/+5
| | | | | | | | | | | | The Qualcomm ipq6018 has apcs block, add compatible for the same. Also, the ipq6018 apcs provides a clock functionality similar to msm8916 but the clock driver is different. Create a child device based on the apcs compatible for the clock controller functionality. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: qcom: Add clock driver name in apcs mailbox driver dataSivaprakash Murugesan2020-06-111-18/+38
| | | | | | | | | | | | | | | Some apcs mailbox devices supports a clock driver, the compatible strings of devices supporting clock driver along with the clock driver name are maintained in a separate structure within the mailbox driver. And the clock driver is added based on device match. With increase in number of devices supporting the clock feature move the clock driver name inside the driver data. so that we can use a single API to get the register offset of mailbox driver and clock driver name together, and the clock driver will be added based on the driver data. Signed-off-by: Sivaprakash Murugesan <sivaprak@codeaurora.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: ONLY IPC MU needs IRQF_NO_SUSPEND flagAnson Huang2020-06-071-2/+7
| | | | | | | | | | | | | | | | | | IPC MU has no power domain assigned and there could be IPC during noirq suspend phase, so IRQF_NO_SUSPEND flag is needed for IPC MU. However, for other MUs, they have power domain assigned and their power will be turned off during noirq suspend phase, but with IRQF_NO_SUSPEND set, their interrupts are NOT disabled even after their power turned off, it will cause system crash when mailbox driver trys to handle pending interrupts but the MU power is already turned off. So, IRQF_NO_SUSPEND flag should ONLY be added to IPC MU which has power domain managed by SCU, then all other MUs' pending interrupts after noirq suspend phase will be handled after system resume. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add runtime PM callback to handle MU clocksAnson Huang2020-06-071-3/+29
| | | | | | | | | | | | | | | | | | | | | | Some of i.MX8M SoCs have MU clock, they need to be managed in runtime to make sure the MU clock can be off in runtime, add runtime PM callback to handle MU clock. And on i.MX8MP, the MU clock is combined with power domain and runtime PM is enabled for the clock driver, during noirq suspend/resume phase, runtime PM is disabled by device suspend, but the MU context save/restore needs to enable MU clock for register access, calling clock prepare/enable will trigger runtime resume failure and lead to system suspend failed. Actually, the MU context save/restore is ONLY necessary for SCU IPC MU, other MUs especially on i.MX8MP platforms which have MU clock assigned, they need to runtime request/free mailbox channel in the consumer driver, so no need to save/restore MU context for them, hence it can avoid this issue, so the MU context save/restore is ONLY applied to i.MX platforms MU instance without clock present. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Add context save/restore for suspend/resumeDong Aisheng2020-06-071-0/+35
| | | | | | | | | | | | | | | | | For "mem" mode suspend on i.MX8 SoCs, MU settings could be lost because its power is off, so save/restore is needed for MU settings during suspend/resume. However, the restore can ONLY be done when MU settings are actually lost, for the scenario of settings NOT lost in "freeze" mode suspend, since there could be still IPC going on multiple CPUs, restoring the MU settings could overwrite the TIE by mistake and cause system freeze, so need to make sure ONLY restore the MU settings when it is powered off, Anson fixes this by checking whether restore is actually needed when resume. Signed-off-by: Dong Aisheng <aisheng.dong@nxp.com> Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: Add support for Qualcomm IPCCManivannan Sadhasivam2020-05-313-0/+298
| | | | | | | | | | | | | | | | | | | | | | Add support for the Inter-Processor Communication Controller (IPCC) block from Qualcomm that coordinates the interrupts (inbound & outbound) for Multiprocessor (MPROC), COMPUTE-Level0 (COMPUTE-L0) & COMPUTE-Level1 (COMPUTE-L1) protocols for the Application Processor Subsystem (APSS). This driver is modeled as an irqchip+mailbox driver. The irqchip part helps in receiving the interrupts from the IPCC clients such as modems, DSPs, PCI-E etc... and forwards them to respective entities in APSS. On the other hand, the mailbox part is used to send interrupts to the IPCC clients from the entities of APSS. Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Raghavendra Rao Ananta <rananta@codeaurora.org> Signed-off-by: Venkata Narendra Kumar Gutta <vnkgutta@codeaurora.org> Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> [mani: moved to mailbox, added static mbox channels and cleanups] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: zynqmp-ipi: Fix NULL vs IS_ERR() check in zynqmp_ipi_mbox_probe()Wei Yongjun2020-05-311-12/+8
| | | | | | | | | | In case of error, the function devm_ioremap() returns NULL pointer not ERR_PTR(). So we should check whether the return value of devm_ioremap() is NULL instead of IS_ERR. Fixes: 4981b82ba2ff ("mailbox: ZynqMP IPI mailbox controller") Signed-off-by: Wei Yongjun <weiyongjun1@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx-mailbox: fix scu msg header size checkPeng Fan2020-05-311-5/+9
| | | | | | | | | | | | The i.MX8 SCU message header size is the number of "u32" elements, not "u8", so fix the check. Reported-by: coverity-bot <keescook+coverity-bot@chromium.org> Addresses-Coverity-ID: 1461658 ("Memory - corruptions") Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: sprd: Add Spreadtrum mailbox driverBaolin Wang2020-05-313-0/+371
| | | | | | | | | The Spreadtrum mailbox controller supports 8 channels to communicate with MCUs, and it contains 2 different parts: inbox and outbox, which are used to send and receive messages by IRQ mode. Signed-off-by: Baolin Wang <baolin.wang@unisoc.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: ZynqMP IPI: Delete an error message in zynqmp_ipi_probe()Markus Elfring2020-05-311-3/+2
| | | | | | | | | | | The function platform_get_irq can log an error already. Thus omit a redundant message for the exception handling in the calling function. This issue was detected by using the Coccinelle software. Signed-off-by: Markus Elfring <elfring@users.sourceforge.net> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Disable the clock on devm_mbox_controller_register() failureFabio Estevam2020-05-311-1/+3
| | | | | | | | | | | | devm_mbox_controller_register() may fail, and in the case of failure the priv->clk clock that was previously enabled, should be disabled. Fixes: 2bb7005696e2 ("mailbox: Add support for i.MX messaging unit") Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Oleksij Rempel <o.rempel@pengutronix.de> [Jassi: fixed merge/am conflict] Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Fix return in imx_mu_scu_xlate()Dan Carpenter2020-05-301-1/+1
| | | | | | | | | This called from mbox_request_channel(). The caller is expecting error pointers and not NULL so this "return NULL;" will lead to an Oops. Fixes: 0a67003b1985 ("mailbox: imx: add SCU MU support") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: imx: Support runtime PMAnson Huang2020-05-301-1/+26
| | | | | | | | | | | | | | | | | | | | | Some power hungry sub-systems like VPU has its own MUs which also use mailbox driver, current mailbox driver uses platform driver model and MU's power will be ON after driver probed and left ON there, it may cause the whole sub-system can NOT enter lower power mode, take VPU driver for example, it has runtime PM support, but due to its MU always ON, the VPU sub-system will be always ON and consume many power during kernel idle. To save power in kernel idle, mailbox driver needs to support runtime PM in order to power off MU when it is unused. However, the runtime suspend/resume can ONLY be implemented in mailbox's .shutdown/.startup callback, so its consumer needs to call mbox_request_channel()/mbox_free_channel() in consumer driver's runtime PM callback, then the MU's power will be ON/OFF along with consumer's runtime PM status. Signed-off-by: Anson Huang <Anson.Huang@nxp.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
* mailbox: pcc: make pcc_mbox_driver staticJason Yan2020-05-301-1/+1
| | | | | | | | | | | Fix the following sparse warning: drivers/mailbox/pcc.c:571:24: warning: symbol 'pcc_mbox_driver' was not declared. Should it be static? Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Jason Yan <yanaijie@huawei.com> Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-17 04:55:45 +0100