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* memory: mtk-smi: Degrade SMI init to module_initYong Wu2017-08-221-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The initialization of MediaTek power manager(SCPSYS) is builtin_platform_driver, and SMI must depend on power-domain. Thus, currently subsys_initcall for SMI is unnecessary, SMI will be always probe defered by power-domain. Degrade it to module_init. In addition, there are two small changes about the probe sequence: 1) Delete this two lines. if (!dev->pm_domain) return -EPROBE_DEFER; This is not helpful. the platform driver framework guarantee this. The "dev_pm_domain_attach" in the "platform_drv_probe" will return EPROBE_DEFER if its powerdomain is not ready. 2) Add the probe-defer for the smi-larb device should waiting for smi-common. In mt2712, there are 2 smi-commons, 10 smi-larbs. All will be probe-defered by the power-domain, there is seldom case that smi-larb probe done before smi-common. then it will hang like this: Unable to handle kernel NULL pointer dereference at virtual address 00000000 pgd = ffffff800a4e0000 [00000000] *pgd=00000000beffe003[ 17.610026] , *pud=00000000beffe003 ... [<ffffff800897fe04>] mtk_smi_enable+0x1c/0xd0 [<ffffff800897fee8>] mtk_smi_larb_get+0x30/0x98 [<ffffff80088edfa8>] mtk_mipicsi0_resume+0x38/0x1b8 [<ffffff8008634f44>] pm_generic_runtime_resume+0x3c/0x58 [<ffffff8008644ff8>] __genpd_runtime_resume+0x38/0x98 [<ffffff8008647434>] genpd_runtime_resume+0x164/0x220 [<ffffff80086372f8>] __rpm_callback+0x78/0xa0 [<ffffff8008637358>] rpm_callback+0x38/0xa0 [<ffffff8008638a4c>] rpm_resume+0x4a4/0x6f8 [<ffffff8008638d04>] __pm_runtime_resume+0x64/0xa0 [<ffffff80088ed05c>] mtk_mipicsi0_probe+0x40c/0xb70 [<ffffff800862cdc0>] platform_drv_probe+0x58/0xc0 [<ffffff800862a514>] driver_probe_device+0x284/0x438 [<ffffff800862a8ac>] __device_attach_driver+0xb4/0x160 [<ffffff8008627d58>] bus_for_each_drv+0x68/0xa8 [<ffffff800862a0a4>] __device_attach+0xd4/0x168 [<ffffff800862a9d4>] device_initial_probe+0x24/0x30 [<ffffff80086291d8>] bus_probe_device+0xa0/0xa8 [<ffffff8008629784>] deferred_probe_work_func+0x94/0xf0 [<ffffff80080f03a8>] process_one_work+0x1d8/0x6e0 Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* iommu/mediatek: Add mt2712 IOMMU supportYong Wu2017-08-221-3/+51
| | | | | | | | | | | | | | | | The M4U IP blocks in mt2712 is MTK's generation2 M4U which use the ARM Short-descriptor like mt8173, and most of the HW registers are the same. The difference is that there are 2 M4U HWs in mt2712 while there's only one in mt8173. The purpose of 2 M4U HWs is for balance the bandwidth. Normally if there are 2 M4U HWs, there should be 2 iommu domains, each M4U has a iommu domain. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: mtk-smi: Handle return value of clk_prepare_enableArvind Yadav2017-08-151-1/+4
| | | | | | | clk_prepare_enable() can fail here and we must check its return value. Signed-off-by: Arvind Yadav <arvind.yadav.cs@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: mtk-smi: add larbid handle routineHonghui Zhang2017-08-041-0/+12
| | | | | | | | | | | | In the commit 3c8f4ad85c4b ("memory/mediatek: add support for mt2701"), the larb->larbid was added but not initialized. Mediatek's gen1 smi need this hardware larbid information to get the register offset which controls whether enable iommu for this larb. This patch add the initialize routine for larbid. Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: mtk-smi: Use of_device_get_match_data helperHonghui Zhang2017-08-041-12/+2
| | | | | | | Replace custom code with generic helper to retrieve driver data. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory/mediatek: add support for mt2701Honghui Zhang2016-06-211-18/+149
| | | | | | | | | | | | | | | | | | | Mediatek SMI has two generations of HW architecture, mt8173 uses the second generation of SMI HW while mt2701 uses the first generation HW of SMI. There's slight differences between the two generations, for generation 2, the register which control the iommu port access PA or IOVA is at each larb's register base. But for generation 1, the register is at smi ao base(smi always on register base). Besides that, the smi async clock should be prepared and enabled for SMI generation 1 HW to transform the smi clock into emi clock domain, but is not needed for SMI generation 2. This patch add SMI driver for mt2701 which use generation 1 SMI HW. Signed-off-by: Honghui Zhang <honghui.zhang@mediatek.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>
* memory: mtk-smi: export mtk_smi_larb_get/putPhilipp Zabel2016-05-061-0/+2
| | | | | | | | To allow building mediatek-drm.ko as a module, the mtk_smi_larb_get and mtk_smi_larb_put symbols have to be exported. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
* memory: mediatek: Add SMI driverYong Wu2016-02-251-0/+273
This patch add SMI(Smart Multimedia Interface) driver. This driver is responsible to enable/disable iommu and control the power domain and clocks of each local arbiter. Signed-off-by: Yong Wu <yong.wu@mediatek.com> Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: Daniel Kurtz <djkurtz@chromium.org> Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Joerg Roedel <jroedel@suse.de>