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* Merge tag 'armsoc-drivers' of ↵Linus Torvalds2015-04-221-69/+289
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC driver updates from Olof Johansson: "Driver updates for v4.1. Some of these are for drivers/soc, where we find more and more SoC-specific drivers these days. Some are for other driver subsystems where we have received acks from the appropriate maintainers. The larger parts of this branch are: - MediaTek support for their PMIC wrapper interface, a high-level interface for talking to the system PMIC over a dedicated I2C interface. - Qualcomm SCM driver has been moved to drivers/firmware. It's used for CPU up/down and needs to be in a shared location for arm/arm64 common code. - cleanup of ARM-CCI PMU code. - another set of cleanusp to the OMAP GPMC code" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (43 commits) soc/mediatek: Remove unused variables clocksource: atmel-st: select MFD_SYSCON soc: mediatek: Add PMIC wrapper for MT8135 and MT8173 SoCs arm-cci: Fix CCI PMU event validation arm-cci: Split the code for PMU vs driver support arm-cci: Get rid of secure transactions for PMU driver arm-cci: Abstract the CCI400 PMU specific definitions arm-cci: Rearrange code for splitting PMU vs driver code drivers: cci: reject groups spanning multiple HW PMUs ARM: at91: remove useless include clocksource: atmel-st: remove mach/hardware dependency clocksource: atmel-st: use syscon/regmap ARM: at91: time: move the system timer driver to drivers/clocksource ARM: at91: properly initialize timer ARM: at91: at91rm9200: remove deprecated arm_pm_restart watchdog: at91rm9200: implement restart handler watchdog: at91rm9200: use the system timer syscon mfd: syscon: Add atmel system timer registers definition ARM: at91/dt: declare atmel,at91rm9200-st as a syscon soc: qcom: gsbi: Add support for ADM CRCI muxing ...
| * ARM OMAP2+ GPMC: fix programming/showing reserved timing parametersRobert ABEL2015-03-061-23/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | GPMC_CONFIG1_i parameters CLKACTIVATIONTIME and WAITMONITORINGTIME have reserved values. Raise an error if calculated timings try to program reserved values. GPMC_CONFIG1_i ATTACHEDDEVICEPAGELENGTH and DEVICESIZE were already checked when parsing the DT. Explicitly comment invalid values on gpmc_cs_show_timings for -CLKACTIVATIONTIME -WAITMONITORINGTIME -DEVICESIZE -ATTACHEDDEVICEPAGELENGTH Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: fix WAITMONITORINGTIME divider bugRobert ABEL2015-03-061-27/+103
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. This patch correctly computes WAITMONITORINGTIME in GPMC_CLK cycles instead of GPMC_FCLK cycles, both during programming (gpmc_cs_set_timings) and during retrieval (gpmc_cs_show_timings). Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: calculate GPMCFCLKDIVIDER based on WAITMONITORINGTIMERobert ABEL2015-03-061-7/+79
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Calculate GPMCFCLKDIVIDER independent of gpmc,sync-clk-ps in DT for pure asynchronous accesses, i.e. both read and write asynchronous. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: always program GPMCFCLKDIVIDERRobert ABEL2015-03-061-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | The WAITMONITORINGTIME is expressed as a number of GPMC_CLK clock cycles, even though the access is defined as asynchronous, and no GPMC_CLK clock is provided to the external device. Still, GPMCFCLKDIVIDER is used as a divider for the GPMC clock, so it must be programmed to define the correct WAITMONITORINGTIME delay. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: change get_gpmc_timing_reg output for DTSRobert ABEL2015-03-061-10/+28
| | | | | | | | | | | | | | | | | | | | DTS output was formatted to require additional work when copy-pasting into DTS. Nano-second timings were replaced with interval of values that produce the same number of clock ticks. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: fix debug output alignmentRobert ABEL2015-03-061-1/+1
| | | | | | | | | | | | | | | | | | | | GPMC debug output is aligned to 10 characters for field names. However, some fields have bigger names, screwing up the alignment. Consequently, alignment was changed to longest field name (17 chars) for now. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: add bus childrenRobert ABEL2015-03-061-2/+16
| | | | | | | | | | | | | | | | This patch adds support for spawning buses as children of the GPMC. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM OMAP2+ GPMC: don't undef DEBUGRobert ABEL2015-03-061-2/+0
| | | | | | | | | | | | | | | | | | OMAP2+ GPMC driver undefines DEBUG, which makes it unnecessarily hard to turn DEBUG on. Remove the offending lines. Signed-off-by: Robert ABEL <rabel@cit-ec.uni-bielefeld.de> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM: OMAP2+: gpmc: make gpmc_cs_get_name() staticSemen Protsenko2015-02-251-1/+1
| | | | | | | | | | | | | | | | | | Fix sparse warning: warning: symbol 'gpmc_cs_get_name' was not declared. Should it be static? Signed-off-by: Semen Protsenko <semen.protsenko@globallogic.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
| * ARM: OMAP2+: gpmc: Fix writing in gpmc_cs_set_memconfSemen Protsenko2015-02-251-4/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some GPMC_CONFIG7 register bits marked as "RESERVED", means they shouldn't be overwritten. A typical approach to handle such bits called "Read-Modify-Write". Writing procedure used in gpmc_cs_set_memconf() utilizes RMW technique, but implemented incorrectly. Due to obvious typo in code read register value is being rewritten by another value, which leads to loss of read RESERVED bits. This patch fixes this. While at it, replace magic numbers with named constants to improve code readability. Signed-off-by: Semen Protsenko <semen.protsenko@globallogic.com> Acked-by: Tony Lindgren <tony@atomide.com> Signed-off-by: Roger Quadros <rogerq@ti.com>
* | memory: jz4780-nemc: driver for the NEMC on JZ4780 SoCsAlex Smith2015-03-263-0/+401
|/ | | | | | | | | | | | | | | | Add a driver for the NAND/External Memory Controller (NEMC) on JZ4780 and later SoCs. The primary function of this driver is to configure parameters, such as timings, for external memory devices using data supplied in the device tree. Devices connected to the NEMC are represented in the DT as children of the NEMC node, the driver uses optional properties specified in these child nodes to configure the parameters of each bank. Signed-off-by: Alex Smith <alex@alex-smith.me.uk> Signed-off-by: Zubair Lutfullah Kakakhel <Zubair.Kakakhel@imgtec.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory/fsl-corenet-cf: Add t1040 supportScott Wood2015-01-301-2/+34
| | | | | | | | | | | | | | | | | | | T1040 has a different version of corenet-cf, despite being incorrectly labelled with a fsl,corenet2-cf compatible. The t1040 version of corenet-cf has a version register that can be read to distinguish. The t4240/b4860 version officially does not, but testing shows that it does and has a different value, so use that. If somehow this ends up not being reliable and we treat a t4240/b4860 as a t1040 (the reverse should not happen, as t1040's version register is official), currently the worst that should happen is writing to reserved bits to enable events that don't exist. The changes to the t1040 version of corenet-cf that this driver cares about are the addition of two new error events. There are also changes to the format of cecar2, which is printed, but not interpreted, by this driver. Signed-off-by: Scott Wood <scottwood@freescale.com>
* Merge tag 'for-linus-20141215' of git://git.infradead.org/linux-mtdLinus Torvalds2014-12-171-2/+11
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Brian Norris: "Summary: - Add device tree support for DoC3 - SPI NOR: Refactoring, for better layering between spi-nor.c and its driver users (e.g., m25p80.c) New flash device support Support 6-byte ID strings - NAND: New NAND driver for Allwinner SoC's (sunxi) GPMI NAND: add support for raw (no ECC) access, for testing purposes Add ATO manufacturer ID A few odd driver fixes - MTD tests: Allow testers to compensate for OOB bitflips in oobtest Fix a torturetest regression - nandsim: Support longer ID byte strings And more" * tag 'for-linus-20141215' of git://git.infradead.org/linux-mtd: (63 commits) mtd: tests: abort torturetest on erase errors mtd: physmap_of: fix potential NULL dereference mtd: spi-nor: allow NULL as chip name and try to auto detect it mtd: nand: gpmi: add raw oob access functions mtd: nand: gpmi: add proper raw access support mtd: nand: gpmi: add gpmi_copy_bits function mtd: spi-nor: factor out write_enable() for erase commands mtd: spi-nor: add support for s25fl128s mtd: spi-nor: remove the jedec_id/ext_id mtd: spi-nor: add id/id_len for flash_info{} mtd: nand: correct the comment of function nand_block_isreserved() jffs2: Drop bogus if in comment mtd: atmel_nand: replace memcpy32_toio/memcpy32_fromio with memcpy mtd: cafe_nand: drop duplicate .write_page implementation mtd: m25p80: Add support for serial flash Spansion S25FL132K MTD: m25p80: fix inconsistency in m25p_ids compared to spi_nor_ids mtd: spi-nor: improve wait-till-ready timeout loop mtd: delete unnecessary checks before two function calls mtd: nand: omap: Fix NAND enumeration on 3430 LDP mtd: nand: add ATO manufacturer info ...
| * fsl_ifc: Support all 8 IFC chip selectsAaron Sierra2014-11-051-2/+11
| | | | | | | | | | | | | | | | | | Freescale's QorIQ T Series processors support 8 IFC chip selects within a memory map backward compatible with previous P Series processors which supported only 4 chip selects. Signed-off-by: Aaron Sierra <asierra@xes-inc.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* | Merge tag 'driver-core-3.19-rc1' of ↵Linus Torvalds2014-12-156-6/+0
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core Pull driver core update from Greg KH: "Here's the set of driver core patches for 3.19-rc1. They are dominated by the removal of the .owner field in platform drivers. They touch a lot of files, but they are "simple" changes, just removing a line in a structure. Other than that, a few minor driver core and debugfs changes. There are some ath9k patches coming in through this tree that have been acked by the wireless maintainers as they relied on the debugfs changes. Everything has been in linux-next for a while" * tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits) Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries" fs: debugfs: add forward declaration for struct device type firmware class: Deletion of an unnecessary check before the function call "vunmap" firmware loader: fix hung task warning dump devcoredump: provide a one-way disable function device: Add dev_<level>_once variants ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries ath: use seq_file api for ath9k debugfs files debugfs: add helper function to create device related seq_file drivers/base: cacheinfo: remove noisy error boot message Revert "core: platform: add warning if driver has no owner" drivers: base: support cpu cache information interface to userspace via sysfs drivers: base: add cpu_device_create to support per-cpu devices topology: replace custom attribute macros with standard DEVICE_ATTR* cpumask: factor out show_cpumap into separate helper function driver core: Fix unbalanced device reference in drivers_probe driver core: fix race with userland in device_add() sysfs/kernfs: make read requests on pre-alloc files use the buffer. sysfs/kernfs: allow attributes to request write buffer be pre-allocated. fs: sysfs: return EGBIG on write if offset is larger than file size ...
| * | memory: drop owner assignment from platform_driversWolfram Sang2014-10-206-6/+0
| |/ | | | | | | | | | | | | A platform_driver does not need to set an owner, it will be populated by the driver core. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | Merge tag 'omap-gpmc-for-linus' of ↵Linus Torvalds2014-12-103-0/+2101
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC/OMAP GPMC driver cleanup and move from Arnd Bergmann: "The GPMC driver has traditionally been considered a part of the OMAP platform code and tightly interweaved with some of the boards. With this cleanup, it has finally come to the point where it makes sense to move it out of arch/arm into drivers/memory, where we already have other drivers for similar hardware. The cleanups are still ongoing, with the goal of eventually having a standalone driver that does not require an interface to architecture code. This is a separate branch because of dependencies on multiple other branches, and to keep the drivers changes separate from the normal cleanups" * tag 'omap-gpmc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: memory: gpmc: Move omap gpmc code to live under drivers ARM: OMAP2+: Move GPMC initcall to devices.c ARM: OMAP2+: Prepare to move GPMC to drivers by platform data header ARM: OMAP2+: Remove unnecesary include in GPMC driver ARM: OMAP2+: Drop board file for 3430sdp ARM: OMAP2+: Drop board file for ti8168evm ARM: OMAP2+: Drop legacy code for gpmc-smc91x.c ARM: OMAP2+: Require proper GPMC timings for devices ARM: OMAP2+: Show bootloader GPMC timings to allow configuring the .dts file ARM: OMAP2+: Fix support for multiple devices on a GPMC chip select ARM: OMAP2+: gpmc: Sanity check GPMC fck on probe ARM: OMAP2+: gpmc: Keep Chip Select disabled while configuring it ARM: OMAP2+: gpmc: Always enable A26-A11 for non NAND devices ARM: OMAP2+: gpmc: Error out if timings fail in gpmc_probe_generic_child() ARM: OMAP2+: gpmc: Print error message in set_gpmc_timing_reg()
| * | memory: gpmc: Move omap gpmc code to live under driversTony Lindgren2014-11-283-0/+2103
| |/ | | | | | | | | | | | | | | | | | | | | | | Just move to drivers as further clean-up can now happen there finally. Let's also add Roger and me to the MAINTAINERS so we get notified for any patches related to GPMC. Cc: Arnd Bergmann <arnd@arndb.de> Acked-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Tony Lindgren <tony@atomide.com>
* / memory: Add NVIDIA Tegra memory controller supportThierry Reding2014-12-0410-389/+3272
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory controller on NVIDIA Tegra exposes various knobs that can be used to tune the behaviour of the clients attached to it. Currently this driver sets up the latency allowance registers to the HW defaults. Eventually an API should be exported by this driver (via a custom API or a generic subsystem) to allow clients to register latency requirements. This driver also registers an IOMMU (SMMU) that's implemented by the memory controller. It is supported on Tegra30, Tegra114 and Tegra124 currently. Tegra20 has a GART instead. The Tegra SMMU operates on memory clients and SWGROUPs. A memory client is a unidirectional, special-purpose DMA master. A SWGROUP represents a set of memory clients that form a logical functional unit corresponding to a single device. Typically a device has two clients: one client for read transactions and one client for write transactions, but there are also devices that have only read clients, but many of them (such as the display controllers). Because there is no 1:1 relationship between memory clients and devices the driver keeps a table of memory clients and the SWGROUPs that they belong to per SoC. Note that this is an exception and due to the fact that the SMMU is tightly integrated with the rest of the Tegra SoC. The use of these tables is discouraged in drivers for generic IOMMU devices such as the ARM SMMU because the same IOMMU could be used in any number of SoCs and keeping such tables for each SoC would not scale. Acked-by: Joerg Roedel <jroedel@suse.de> Signed-off-by: Thierry Reding <treding@nvidia.com>
* Merge tag 'at91-drivers-for-3.17' of ↵Nicolas Ferre2014-08-253-0/+109
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux Pull AT91 reset, poweroff and ram drivers from Maxime Ripard: "This tag holds the various new drivers introduced to move code that used to be in mach-at91 over to the proper frameworks. These files are the reboot and poweroff code for all AT91 SoCs but the RM9200, and the ram controller driver is not doing much at the time, except for grabing the RAM clock in order to leave it always enabled." Conflicts: arch/arm/mach-at91/Kconfig
| * memory: add a driver for atmel ram controllersAlexandre Belloni2014-07-153-0/+109
| | | | | | | | | | | | | | | | | | | | Atmel SoCs have one or multiple RAM controllers that need one or multiple clocks to run. This driver handle those clocks. Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
* | memory: Freescale CoreNet Coherency Fabric error reporting driverScott Wood2014-07-303-0/+262
|/ | | | | | | | | | | The CoreNet Coherency Fabric is part of the memory subsystem on some Freescale QorIQ chips. It can report coherency violations (e.g. due to misusing memory that is mapped noncoherent) as well as transactions that do not hit any local access window, or which hit a local access window with an invalid target ID. Signed-off-by: Scott Wood <scottwood@freescale.com> Reviewed-by: Bharat Bhushan <bharat.bhushan@freescale.com>
* memory: mvebu-devbus: add a devbus, keep-config propertyThomas Petazzoni2014-04-291-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | Currently, the mvebu-devbus Device Tree binding makes defining the timing parameters mandatory. However, in practice, when converting Orion5x platforms to the Device Tree, we may not necessarily have easy access to the hardware platforms to fetch those values which were not defined in old-style board files: all these platforms rely on the bootloader setting the timing parameters correctly. In order to facilitate the migration to the Device Tree of this platform, this commit relaxes the mvebu-devbus Device Tree binding by introducing a 'devbus,keep-config' boolean property, which, if defined, will ignore all timing parameters passed in the Device Tree, and simply rely on the timing values already defined by the bootloader. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-10-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: add Orion5x supportThomas Petazzoni2014-04-291-21/+86
| | | | | | | | | | | | | | | | | | | | This commit adds support for the Orion5x family of Marvell processors into the mvebu-devbus driver. It differs from the already supported Armada 370/XP by: * Having a single register (instead of two) for doing all the timing configuration. * Having a few less timing configuration parameters. For this reason, a separate compatible string "marvell,orion-devbus" is introduced. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-9-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: split functionsThomas Petazzoni2014-04-291-39/+51
| | | | | | | | | | | | | | | | | The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the registers. Therefore, in preparation to the introduction of Orion5x support, we separate into two functions the code that 1/ retrieves the timing parameters from the Device Tree and 2/ applies those timings parameters into the hardware registers. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-8-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: use _SHIFT suffixes instead of _BITThomas Petazzoni2014-04-291-18/+18
| | | | | | | | | | | | | As noted by Sebastian Hesselbarth, the definitions in mvebu-devbus.c are not bit definition, but rather shift values, so a _SHIFT prefix would make more sense. This commit therefore replaces the *_BIT definitions by *_SHIFT definitions. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-7-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: use ARMADA_ prefix in definesThomas Petazzoni2014-04-291-24/+24
| | | | | | | | | | | | | | The mvebu-devbus driver currently only supports the Armada 370/XP family, but it can also cover the Orion5x family. However, the Orion5x family has a different organization of the register. Therefore, in preparation to the introduction of Orion5x support, we rename the Armada 370/XP specific definitions to have an ARMADA_ prefix. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Tested-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Link: https://lkml.kernel.org/r/1398202002-28530-6-git-send-email-thomas.petazzoni@free-electrons.com Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: mvebu-devbus: fix the conversion of the bus widthThomas Petazzoni2014-04-171-2/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the Armada 370 and Armada XP datasheets, the part of the Device Bus register that configure the bus width should contain 0 for a 8 bits bus width, and 1 for a 16 bits bus width (other values are unsupported/reserved). However, the current conversion done in the driver to convert from a bus width in bits to the value expected by the register leads to setting the register to 1 for a 8 bits bus, and 2 for a 16 bits bus. This mistake was compensated by a mistake in the existing Device Tree files for Armada 370/XP platforms: they were declaring a 8 bits bus width, while the hardware in fact uses a 16 bits bus width. This commit fixes that by adjusting the conversion logic. This patch fixes a bug that was introduced in 3edad321b1bd2e6c8b5f38146c115c8982438f06 ('drivers: memory: Introduce Marvell EBU Device Bus driver'), which was merged in v3.11. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Link: https://lkml.kernel.org/r/1397489361-5833-2-git-send-email-thomas.petazzoni@free-electrons.com Fixes: 3edad321b1bd ('drivers: memory: Introduce Marvell EBU Device Bus driver') Cc: stable@vger.kernel.org # v3.11+ Acked-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* memory: ti-aemif: introduce AEMIF driverIvan Khoronzhuk2014-03-013-0/+439
| | | | | | | | | | | | | | | | | | | Add new AEMIF driver for EMIF16 Texas Instruments controller. The EMIF16 module is intended to provide a glue-less interface to a variety of asynchronous memory devices like ASRA M, NOR and NAND memory. A total of 256M bytes of any of these memories can be accessed at any given time via 4 chip selects with 64M byte access per chip select. Synchronous memories such as DDR1 SD RAM, SDR SDRAM and Mobile SDR are not supported. This controller is used on SoCs like Davinci, Keysone2 Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* powerpc: select MEMORY for FSL_IFC to not break existing .config filesPaul Gortmaker2014-03-011-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit d2ae2e20fbdde5a65f3a5a153044ab1e5c53f7cc ("driver/memory:Move Freescale IFC driver to a common driver") introduces this build regression into the mpc85xx_defconfig: drivers/built-in.o: In function `fsl_ifc_nand_remove': drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1147: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1031: undefined reference to `fsl_ifc_ctrl_dev' drivers/built-in.o: In function `match_bank': drivers/mtd/nand/fsl_ifc_nand.c:1013: undefined reference to `convert_ifc_address' drivers/built-in.o: In function `fsl_ifc_nand_probe': drivers/mtd/nand/fsl_ifc_nand.c:1059: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1080: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' drivers/mtd/nand/fsl_ifc_nand.c:1069: undefined reference to `fsl_ifc_ctrl_dev' make: *** [vmlinux] Error 1 This happens because there is nothing to descend us into the drivers/memory directory in the mpc85xx_defconfig. It wasn't selecting CONFIG_MEMORY. So we never built drivers/memory/fsl_ifc.o and so we have nothing to link the above symbols against. Since the goal of the original commit was to relocate the driver to an arch independent location, it only makes sense to relocate the Kconfig setting there as well. But that alone won't fix the build failure; for that we ensure whoever selects FSL_IFC also selects MEMORY. Cc: Prabhakar Kushwaha <prabhakar@freescale.com> Cc: Scott Wood <scottwood@freescale.com> Cc: Arnd Bergmann <arnd@arndb.de> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* driver/memory:Move Freescale IFC driver to a common driverPrabhakar Kushwaha2014-02-182-0/+310
| | | | | | | | | | | | | | Freescale IFC controller has been used for mpc8xxx. It will be used for ARM-based SoC as well. This patch moves the driver to driver/memory and fix the header file includes. Also remove module_platform_driver() and instead call platform_driver_register() from subsys_initcall() to make sure this module has been loaded before MTD partition parsing starts. Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge tag 'soc-for-linus' of ↵Linus Torvalds2013-09-061-70/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc Pull ARM SoC platform changes from Olof Johansson: "This branch contains mostly additions and changes to platform enablement and SoC-level drivers. Since there's sometimes a dependency on device-tree changes, there's also a fair amount of those in this branch. Pieces worth mentioning are: - Mbus driver for Marvell platforms, allowing kernel configuration and resource allocation of on-chip peripherals. - Enablement of the mbus infrastructure from Marvell PCI-e drivers. - Preparation of MSI support for Marvell platforms. - Addition of new PCI-e host controller driver for Tegra platforms - Some churn caused by sharing of macro names between i.MX 6Q and 6DL platforms in the device tree sources and header files. - Various suspend/PM updates for Tegra, including LP1 support. - Versatile Express support for MCPM, part of big little support. - Allwinner platform support for A20 and A31 SoCs (dual and quad Cortex-A7) - OMAP2+ support for DRA7, a new Cortex-A15-based SoC. The code that touches other architectures are patches moving MSI arch-specific functions over to weak symbols and removal of ARCH_SUPPORTS_MSI, acked by PCI maintainers" * tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (266 commits) tegra-cpuidle: provide stub when !CONFIG_CPU_IDLE PCI: tegra: replace devm_request_and_ioremap by devm_ioremap_resource ARM: tegra: Drop ARCH_SUPPORTS_MSI and sort list ARM: dts: vf610-twr: enable i2c0 device ARM: dts: i.MX51: Add one more I2C2 pinmux entry ARM: dts: i.MX51: Move pins configuration under "iomuxc" label ARM: dtsi: imx6qdl-sabresd: Add USB OTG vbus pin to pinctrl_hog ARM: dtsi: imx6qdl-sabresd: Add USB host 1 VBUS regulator ARM: dts: imx27-phytec-phycore-som: Enable AUDMUX ARM: dts: i.MX27: Disable AUDMUX in the template ARM: dts: wandboard: Add support for SDIO bcm4329 ARM: i.MX5 clocks: Remove optional clock setup (CKIH1) from i.MX51 template ARM: dts: imx53-qsb: Make USBH1 functional ARM i.MX6Q: dts: Enable I2C1 with EEPROM and PMIC on Phytec phyFLEX-i.MX6 Ouad module ARM i.MX6Q: dts: Enable SPI NOR flash on Phytec phyFLEX-i.MX6 Ouad module ARM: dts: imx6qdl-sabresd: Add touchscreen support ARM: imx: add ocram clock for imx53 ARM: dts: imx: ocram size is different between imx6q and imx6dl ARM: dts: imx27-phytec-phycore-som: Fix regulator settings ARM: dts: i.MX27: Remove clock name from CPU node ...
| * memory: mvebu-devbus: Remove unused variableEzequiel Garcia2013-08-121-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This variable is not being used anywhere and it's only forgotten garbage that should have been removed in the previous commit: commit 9b6e4c0a58e24c28bd757c9365824a37e80b751c Author: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Date: Fri Jul 26 10:17:38 2013 -0300 memory: mvebu-devbus: Remove address decoding window workaround Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
| * memory: mvebu-devbus: Remove address decoding window workaroundEzequiel Garcia2013-08-061-62/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Now that mbus device tree binding has been introduced, remove the address decoding window management from this driver. A suitable 'ranges' entry should be added to the devbus-compatible node in the device tree, as described by the mbus binding documentation. Acked-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org> Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Tested-by: Andrew Lunn <andrew@lunn.ch> Tested-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com> Signed-off-by: Jason Cooper <jason@lakedaemon.net>
* | tegra: simplify use of devm_ioremap_resourceJulia Lawall2013-08-162-4/+0
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Remove unneeded error handling on the result of a call to platform_get_resource when the value is passed to devm_ioremap_resource. A simplified version of the semantic patch that makes this change is as follows: (http://coccinelle.lip6.fr/) // <smpl> @@ expression pdev,res,n,e,e1; expression ret != 0; identifier l; @@ - res = platform_get_resource(pdev, IORESOURCE_MEM, n); ... when != res - if (res == NULL) { ... \(goto l;\|return ret;\) } ... when != res + res = platform_get_resource(pdev, IORESOURCE_MEM, n); e = devm_ioremap_resource(e1, res); // </smpl> Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Stephen Warren <swarren@nvidia.com>
* memory: tegra30-mc: Fix IRQ handler.Tuomas Tynkkynen2013-06-181-3/+6
| | | | | | | | | | | | In Tegra30 any memory controller interrupt would cause an infinite loop in the IRQ handler. Additionally, a garbage pointer was used to read the MC status registers, which causes wrong values to be printed if a MC error occurred. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: tegra20-mc: Fix hang in IRQ handler.Tuomas Tynkkynen2013-06-181-1/+4
| | | | | | | | | | In Tegra20 any memory controller interrupt would cause an infinite loop in the IRQ handler. Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Thierry Reding <thierry.reding@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* Merge 3.10-rc3 into char-misc-nextGreg Kroah-Hartman2013-05-271-6/+0
|\ | | | | | | | | | | We want the changes in here. Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
| * drivers/memory: don't check resource with devm_ioremap_resourceWolfram Sang2013-05-181-6/+0
| | | | | | | | | | | | | | devm_ioremap_resource does sanity checks on the given resource. No need to duplicate this in the driver. Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
* | drivers: memory: Introduce Marvell EBU Device Bus driverEzequiel Garcia2013-05-213-0/+351
|/ | | | | | | | | | | | | | | | | | | | | | | | | | Marvell EBU SoCs such as Armada 370/XP, Orion5x (88f5xxx) and Discovery (mv78xx0) supports a Device Bus controller to access several kinds of memories and I/O devices (NOR, NAND, SRAM, FPGA). This commit adds a driver to handle this controller. So far only Armada 370, Armada XP and Discovery SoCs are supported. The driver must be registered through a device tree node; as explained in the binding document. For each child node in the device tree, this driver will: * set timing parameters * register a child device * setup an address decoding window, using the mbus driver Keep in mind the address decoding window setup is only a temporary hack. This code will be removed from this devbus driver as soon as a proper device tree binding for the mbus driver is added. Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Jason Cooper <jason@lakedaemon.net> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: Load the correct custom config values from dtLokesh Vutla2013-03-251-3/+4
| | | | | | | | | | | | | of_get_property returns value in Big Endian format. Before using this value it should be converted to little endian using be32_to_cpup(). Custom configs of emif are read from dt using of_get_property, but these are not converted to litte endian format. Correcting the same here. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: errata i743: Prohibit usage of Power-Down modeGrygorii Strashko2013-03-251-0/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ERRATA DESCRIPTION : The EMIF supports power-down state for low power. The EMIF automatically puts the SDRAM into power-down after the memory is not accessed for a defined number of cycles and the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field is set to 0x4. As the EMIF supports automatic output impedance calibration, a ZQ calibration long command is issued every time it exits active power-down and precharge power-down modes. The EMIF waits and blocks any other command during this calibration. The EMIF does not allow selective disabling of ZQ calibration upon exit of power-down mode. Due to very short periods of power-down cycles, ZQ calibration overhead creates bandwidth issues and increases overall system power consumption. On the other hand, issuing ZQ calibration long commands when exiting self-refresh is still required. WORKAROUND : Because there is no power consumption benefit of the power-down due to the calibration and there is a performance risk, the guideline is to not allow power-down state and, therefore, to not have set the EMIF_PWR_MGMT_CTRL[10:8] REG_LP_MODE bit field to 0x4. This is applicable only for EMIF4D IP used in OMAP4 Soc's. Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vitaly Chernooky <vitaly.chernooky@ti.com> Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: Fix the incorrect 'size' parameter in memcpyOleksandr Dmytryshyn2013-03-251-1/+1
| | | | | | | | | | | | The issue was that only the first timings table was added to the emif platform data at the emif driver registration. All other timings tables was filled with zeros. Now all emif timings table are added to the platform data. Signed-off-by: Oleksandr Dmytryshyn <oleksandr.dmytryshyn@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: use restart if power_off not present when out of specNishanth Menon2013-03-251-1/+9
| | | | | | | | | | | | | | | | Some machine or kernel variants might have missed implementation of power off handlers. We DONOT want to let the system be in "out of spec" state in this condition. So, WARN and attempt a machine restart in the hopes of clearing the out-of-spec temperature condition. NOTE: This is not the safest option, but safer than leaving the system in unstable conditions. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: Handle devices which are not rated for >85CNishanth Menon2013-03-251-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | As per JESD209-2E specification for LPDDR2, http://www.jedec.org/standards-documents/results/jesd209-2E Table 73, LPDDR2 memories come in two flavors - Standard and Extended. The Standard types can operate from -25C to +85C However, beyond that and upto +105C can only be supported by Extended types. Unfortunately, it seems there is no info in MR0(device info) or MR[1,2](device feature) for run time detection of this capability as far as seen on the spec. Hence, we provide a custom_config flag to be populated by platforms which have these "extended" type memories. For the "Standard" memories, we need to consider MR4 notifications of temperature triggers >85C as equivalent to thermal shutdown events (equivalent to Spec specified thermal shutdown events for "extended" parts). Reported-by: Richard Woodruff <r-woodruff2@ti.com> Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: handle overflow for timing for LP modeNishanth Menon2013-03-251-8/+28
| | | | | | | | | | | In case the custom timings provide values which overflow the maximum possible field value, warn and use maximum permissible value. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: setup LP settings on freq updateAmbresh K2013-03-251-0/+2
| | | | | | | | | | | | | Program the power management shadow register on freq update Else the concept of threshold frequencies dont really matter as the system always uses the performance mode timing for LP which is programmed in at init time. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Ambresh K <ambresh@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* memory: emif: Fix the lpmode timeout calculationLokesh Vutla2013-03-251-3/+7
| | | | | | | | | | | | The driver tries to round up the specified timeout cycles to the next power of 2 value. This should be done defore updating timeout variable. Correcting this here. Reported-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* drivers: memory: use module_platform_driver_probe()Fabio Porcedda2013-03-151-11/+1
| | | | | | | | | | | This patch converts the drivers to use the module_platform_driver_probe() macro which makes the code smaller and a bit simpler. Signed-off-by: Fabio Porcedda <fabio.porcedda@gmail.com> Cc: Benoit Cousson <b-cousson@ti.com> Cc: Aneesh V <aneesh@ti.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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