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* Merge tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu into ↵Olof Johansson2020-01-161-3/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | arm/drivers mvebu drivers for 5.6 (part 1) - Various cleanup on the following drivers: - Turris Mox rWTM firmware - Moxtet bus - Armada 37xx rWTM mailbox - Marvell EBU Device Bus * tag 'mvebu-drivers-5.6-1' of git://git.infradead.org/linux-mvebu: mailbox: armada-37xx-rwtm: convert to devm_platform_ioremap_resource memory: mvebu-devbus: convert to devm_platform_ioremap_resource bus: moxtet: declare moxtet_bus_type as static firmware: turris-mox-rwtm: small white space cleanup Link: https://lore.kernel.org/r/877e1x3nxc.fsf@FE-laptop Signed-off-by: Olof Johansson <olof@lixom.net>
| * memory: mvebu-devbus: convert to devm_platform_ioremap_resourceYangtao Li2020-01-081-3/+1
| | | | | | | | | | | | | | Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* | Merge tag 'tegra-for-5.6-memory' of ↵Olof Johansson2020-01-167-149/+1928
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.6-rc1 This adds a couple of fixes for the Tegra30 EMC frequency scaling code and adds support for EMC frequency scaling on Tegra186 and later. * tag 'tegra-for-5.6-memory' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Correct error message for timed out auto calibration memory: tegra30-emc: Firm up hardware programming sequence memory: tegra30-emc: Firm up suspend/resume sequence memory: tegra: Correct reset value of xusb_hostr memory: tegra: Add support for the Tegra194 memory controller memory: tegra: Only include support for enabled SoCs memory: tegra: Support DVFS on Tegra186 and later memory: tegra: Add system sleep support memory: tegra: Extract memory client SID programming memory: tegra: Add per-SoC data for Tegra186 memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186 memory: tegra: Implement EMC debugfs interface on Tegra30 memory: tegra: Implement EMC debugfs interface on Tegra20 memory: tegra: Refashion EMC debugfs interface on Tegra124 Link: https://lore.kernel.org/r/20200111003553.2411874-3-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
| * | memory: tegra30-emc: Correct error message for timed out auto calibrationDmitry Osipenko2020-01-101-2/+1
| | | | | | | | | | | | | | | | | | | | | The code waits for auto calibration to be finished and not to be disabled. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra30-emc: Firm up hardware programming sequenceDmitry Osipenko2020-01-101-61/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously there was a problem where a late handshake handling caused a memory corruption, this problem was resolved by issuing calibration command right after changing the timing, but looks like the solution wasn't entirely correct since calibration interval could be disabled as well. Now programming sequence is completed immediately after receiving handshake from CaR, without potentially long delays and in accordance to the TRM's programming guide. Secondly, the TRM's programming guide suggests to flush EMC writes by reading any *MC* register before doing CaR changes. This is also addressed now. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra30-emc: Firm up suspend/resume sequenceDmitry Osipenko2020-01-101-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | The current code doesn't prevent race conditions of suspend/resume vs CCF. Let's take exclusive control over the EMC clock during suspend in a way that is free from race conditions. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Correct reset value of xusb_hostrNicolin Chen2020-01-101-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | According to Tegra X1 (Tegra210) TRM, the reset value of xusb_hostr field (bit [7:0]) should be 0x7a. So this patch simply corrects it. Signed-off-by: Nicolin Chen <nicoleotsuka@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Add support for the Tegra194 memory controllerThierry Reding2020-01-093-0/+953
| | | | | | | | | | | | | | | | | | | | | | | | The memory and external memory controllers on Tegra194 are very similar to their predecessors from Tegra186. Add the necessary SoC-specific data to support the newer versions. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Only include support for enabled SoCsThierry Reding2020-01-092-0/+8
| | | | | | | | | | | | | | | | | | | | | The memory client tables can be fairly large and they can easily be omitted if support for the corresponding SoC is not enabled. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Support DVFS on Tegra186 and laterThierry Reding2020-01-093-3/+304
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add a Tegra186 (and later) EMC driver that reads the EMC DVFS tables from BPMP and uses the EMC clock to change the external memory clock. This currently only provides a debugfs interface to show the available frequencies and set lower and upper limits of the allowed range. This can be used for testing the various frequencies. The goal is to eventually integrate this with the interconnect framework so that the EMC frequency can be scaled based on demand from memory clients. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Add system sleep supportThierry Reding2020-01-091-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | Add system suspend/resume support for the memory controller found on Tegra186 and later. This is required so that the SID registers can be reprogrammed after their content was lost during system sleep. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Extract memory client SID programmingThierry Reding2020-01-091-22/+27
| | | | | | | | | | | | | | | | | | | | | Move programming of the memory client to SID mapping into a separate function so that it can be reused from multiple call sites. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Add per-SoC data for Tegra186Thierry Reding2020-01-091-10/+19
| | | | | | | | | | | | | | | | | | | | | Instead of hard-coding the memory client table, use per-SoC data in preparation for adding support for other SoCs. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Rename tegra_mc to tegra186_mc on Tegra186Thierry Reding2020-01-091-4/+10
| | | | | | | | | | | | | | | | | | This is just for consistency with the rest of the driver. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Implement EMC debugfs interface on Tegra30Thierry Reding2020-01-091-0/+173
| | | | | | | | | | | | | | | | | | | | | | | | A common debugfs interface is already available on Tegra20, Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra30 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Implement EMC debugfs interface on Tegra20Thierry Reding2020-01-091-0/+175
| | | | | | | | | | | | | | | | | | | | | | | | A common debugfs interface is already available on Tegra124, Tegra186 and Tegra194. Implement the same interface on Tegra20 to enable testing of the EMC frequency scaling code using a unified interface. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | memory: tegra: Refashion EMC debugfs interface on Tegra124Thierry Reding2020-01-091-42/+143
| |/ | | | | | | | | | | | | | | | | | | The current debugfs interface is only partially useful. While it allows listing supported frequencies and testing individual clock rates, it is limited in that it can't be used to restrict the range of frequencies that the driver is allowed to set. This is something we may want to use to test adaptive scaling once that's implemented. Signed-off-by: Thierry Reding <treding@nvidia.com>
* | memory: samsung: Rename Exynos to lowercaseKrzysztof Kozlowski2020-01-072-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix up inconsistent usage of upper and lowercase letters in "Exynos" name. "EXYNOS" is not an abbreviation but a regular trademarked name. Therefore it should be written with lowercase letters starting with capital letter. The lowercase "Exynos" name is promoted by its manufacturer Samsung Electronics Co., Ltd., in advertisement materials and on website. Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* | memory: samsung: exynos5422-dmc: Convert to devm_platform_ioremap_resourceYangtao Li2019-12-301-5/+2
|/ | | | | | | | Use devm_platform_ioremap_resource() to simplify code. Signed-off-by: Yangtao Li <tiny.windzz@gmail.com> Acked-by: Lukasz Luba <lukasz.luba@arm.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
* Merge tag 'tegra-for-5.5-memory-fixes' of ↵Olof Johansson2019-12-061-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/fixes memory: tegra: Fixes for v5.5-rc1 This contains a fix for a kernel panic that can occur on suspend if EMC timings are not available in device tree. * tag 'tegra-for-5.5-memory-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra30-emc: Fix panic on suspend Link: https://lore.kernel.org/r/20191204130753.3614278-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
| * memory: tegra30-emc: Fix panic on suspendDmitry Osipenko2019-11-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Trying to suspend driver results in a crash if timings aren't available in device-tree. Reported-by: Jon Hunter <jonathanh@nvidia.com> Fixes: e34212c75a68 ("memory: tegra: Introduce Tegra30 EMC driver") Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Acked-by: Jon Hunter <jonathanh@nvidia.com> Tested-by: Jon Hunter <jonathanh@nvidia.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
* | Merge tag 'armsoc-drivers' of ↵Linus Torvalds2019-12-0518-222/+3327
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc Pull ARM SoC driver updates from Olof Johansson: "Various driver updates for platforms: - A larger set of work on Tegra 2/3 around memory controller and regulator features, some fuse cleanups, etc.. - MMP platform drivers, in particular for USB PHY, and other smaller additions. - Samsung Exynos 5422 driver for DMC (dynamic memory configuration), and ASV (adaptive voltage), allowing the platform to run at more optimal operating points. - Misc refactorings and support for RZ/G2N and R8A774B1 from Renesas - Clock/reset control driver for TI/OMAP - Meson-A1 reset controller support - Qualcomm sdm845 and sda845 SoC IDs for socinfo" * tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (150 commits) firmware: arm_scmi: Fix doorbell ring logic for !CONFIG_64BIT soc: fsl: add RCPM driver dt-bindings: fsl: rcpm: Add 'little-endian' and update Chassis definition memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver soc: mediatek: Refactor bus protection control soc: mediatek: Refactor sram control ...
| * | Merge tag 'tegra-for-5.5-memory-v2' of ↵Olof Johansson2019-11-119-149/+1428
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into arm/drivers memory: tegra: Changes for v5.5-rc1 This contains a couple of fixes and adds support for EMC frequency scaling on Tegra30. * tag 'tegra-for-5.5-memory-v2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: memory: tegra: Consolidate registers definition into common header memory: tegra: Ensure timing control debug features are disabled memory: tegra: Introduce Tegra30 EMC driver memory: tegra: Do not handle error from wait_for_completion_timeout() memory: tegra: Increase handshake timeout on Tegra20 memory: tegra: Print a brief info message about EMC timings memory: tegra: Pre-configure debug register on Tegra20 memory: tegra: Include io.h instead of iopoll.h memory: tegra: Adapt for Tegra20 clock driver changes memory: tegra: Don't set EMC rate to maximum on probe for Tegra20 memory: tegra: Add gr2d and gr3d to DRM IOMMU group memory: tegra: Set DMA mask based on supported address bits clk: tegra: Add Tegra20/30 EMC clock implementation Link: https://lore.kernel.org/r/20191111143836.4027200-1-thierry.reding@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * memory: tegra: Consolidate registers definition into common headerDmitry Osipenko2019-11-114-74/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | The Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Ensure timing control debug features are disabledDmitry Osipenko2019-11-112-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Timing control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Introduce Tegra30 EMC driverDmitry Osipenko2019-11-116-14/+1310
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Tested-by: Peter Geis <pgwipeout@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Do not handle error from wait_for_completion_timeout()Dmitry Osipenko2019-11-111-5/+1
| | | | | | | | | | | | | | | | | | | | | | | | Contrary to its wait_for_completion_timeout_interruptible() sibling, the wait_for_completion_timeout() function does not return an error. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Increase handshake timeout on Tegra20Dmitry Osipenko2019-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Turned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay. Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Print a brief info message about EMC timingsDmitry Osipenko2019-11-111-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing. Suggested-by: Marc Dietrich <marvin24@gmx.de> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Pre-configure debug register on Tegra20Dmitry Osipenko2019-11-111-1/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Include io.h instead of iopoll.hDmitry Osipenko2019-11-111-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The register polling code was gone, but the included header change was missed. Fix it up for consistency. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Adapt for Tegra20 clock driver changesDmitry Osipenko2019-11-111-2/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | Now Tegra20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra clock driver API. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Don't set EMC rate to maximum on probe for Tegra20Dmitry Osipenko2019-11-111-77/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver. Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com> Signed-off-by: Dmitry Osipenko <digetx@gmail.com> Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Add gr2d and gr3d to DRM IOMMU groupThierry Reding2019-11-113-12/+19
| | | | | | | | | | | | | | | | | | | | | All of the devices making up the Tegra DRM device want to share a single IOMMU domain. Put them into a single group to allow them to do that. Signed-off-by: Thierry Reding <treding@nvidia.com>
| | * memory: tegra: Set DMA mask based on supported address bitsThierry Reding2019-11-111-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | The memory controller on Tegra124 and later supports 34 or more address bits. Advertise that by setting the DMA mask based on the number of the address bits. Signed-off-by: Thierry Reding <treding@nvidia.com>
| * | Merge tag 'at91-5.5-drivers' of ↵Olof Johansson2019-11-081-6/+5
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux into arm/drivers AT91 drivers for 5.5 - a new driver exposing the serial number registers through nvmem - a few documentation and definition changes * tag 'at91-5.5-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/at91/linux: soc: at91: Add Atmel SFR SN (Serial Number) support memory: atmel-ebi: switch to SPDX license identifiers memory: atmel-ebi: move NUM_CS definition inside EBI driver ARM: at91: Documentation: update the sama5d3 and armv7m datasheets Link: https://lore.kernel.org/r/20191107221644.GA201884@piout.net Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | memory: atmel-ebi: switch to SPDX license identifiersTudor Ambarus2019-11-071-4/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adopt the SPDX license identifiers to ease license compliance management. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20190906151519.19442-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
| | * | memory: atmel-ebi: move NUM_CS definition inside EBI driverTudor Ambarus2019-11-071-2/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | The total number of EBI CS lines is described by the EBI controller and not by the Matrix. Move the definition for the number of CS inside EBI driver. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Link: https://lore.kernel.org/r/20190906150632.19039-1-tudor.ambarus@microchip.com Signed-off-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
| * | Merge branch 'for_5.5/driver-soc' of ↵Olof Johansson2019-11-041-4/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone into arm/drivers * 'for_5.5/driver-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/ssantosh/linux-keystone: memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs' soc: ti: omap-prm: fix return value check in omap_prm_probe() soc: ti: omap-prm: add omap5 PRM data soc: ti: omap-prm: add am4 PRM data soc: ti: omap-prm: add dra7 PRM data soc: ti: omap-prm: add data for am33xx soc: ti: omap-prm: add omap4 PRM data soc: ti: omap-prm: add support for denying idle for reset clockdomain soc: ti: omap-prm: poll for reset complete during de-assert soc: ti: add initial PRM driver with reset control support dt-bindings: omap: add new binding for PRM instances Link: https://lore.kernel.org/r/1572372856-20598-1-git-send-email-santosh.shilimkar@oracle.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | memory: emif: remove set but not used variables 'cs1_used' and 'custom_configs'YueHaibing2019-10-291-4/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/memory/emif.c:1616:9: warning: variable cs1_used set but not used [-Wunused-but-set-variable] drivers/memory/emif.c:1624:36: warning: variable custom_configs set but not used [-Wunused-but-set-variable] They are never used since introduction. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Santosh Shilimkar <santosh.shilimkar@oracle.com>
| * | Merge tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux ↵Olof Johansson2019-10-241-63/+101
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | into arm/drivers This pull request contains Broadcom ARM/ARM64/MIPS based SoCs drivers updates for 5.5, please pull the following: - Markus updates the DPFE driver so as to support deferring the firmware loading process until the first sysfs attribute is accessed, in the process he does a bunch of cleanups and minor fixes - Florian adds support for the DPFE on 7211 which uses a "new style" API v2 and makes necessary changes along the way * tag 'arm-soc/for-5.5/drivers' of https://github.com/Broadcom/stblinux: memory: brcmstb: dpfe: Fixup API version/commands for 7211 memory: brcmstb: dpfe: Compute checksum at __send_command() time memory: brcmstb: dpfe: support for deferred firmware download memory: brcmstb: dpfe: pass *priv as argument to brcmstb_dpfe_download_firmware() memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware() memory: brcmstb: dpfe: add locking around DCPU enable/disable memory: brcmstb: dpfe: initialize priv->dev memory: brcmstb: dpfe: rename struct private_data Link: https://lore.kernel.org/r/20191023212814.30622-2-f.fainelli@gmail.com Signed-off-by: Olof Johansson <olof@lixom.net>
| | * | memory: brcmstb: dpfe: Fixup API version/commands for 7211Florian Fainelli2019-10-181-8/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 7211 uses a newer version of API v2 which is half way between what was defined as API v3 and what used to be called API v2 but was used with DPFE firmwares with major versions 1.x.x.x. Starting with **the new** API v2, we are no longer getting loadable firmware images, so the capability to load it is removed (like v3). To avoid spreading more confusion, map 7268/7271/7278 to the old DPFE API version 2, 7211 to the new API v2 and introduce the specific commands for that, and leave newer versions to map to API v3. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com>
| | * | memory: brcmstb: dpfe: Compute checksum at __send_command() timeFlorian Fainelli2019-10-181-13/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of pre-computing the checksum, do it at the time we send the command, this reduces the possibility of introducing errors as well as limits the amount of code necessary while adding new commands and/or new API versions. The MSG_CHKSUM enumeration value is no longer necessary and is removed. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Markus Mayer <mmayer@broadcom.com>
| | * | memory: brcmstb: dpfe: support for deferred firmware downloadMarkus Mayer2019-10-181-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We add support for deferred downloading of the DPFE firmware. It may be necessary to do this if the root file system containing the firmware image is not yet available at the time the driver's probe function is being called. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | memory: brcmstb: dpfe: pass *priv as argument to ↵Markus Mayer2019-10-181-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | brcmstb_dpfe_download_firmware() Rather than passing a (struct platform_device *) to brcmstb_dpfe_download_firmware(), we pass a (struct private_data *). This is the more sensible thing to do. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | memory: brcmstb: dpfe: move init_data into brcmstb_dpfe_download_firmware()Markus Mayer2019-10-181-12/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than declaring our init_data in several places and passing it as parameter into brcmstb_dpfe_download_firmware(), we declare it inside brcmstb_dpfe_download_firmware() instead. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | memory: brcmstb: dpfe: add locking around DCPU enable/disableMarkus Mayer2019-10-181-10/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To ensure consistency, we add locking primitives inside the DCPU enable and disable routines. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | memory: brcmstb: dpfe: initialize priv->devMarkus Mayer2019-10-181-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add missing initialization of priv->dev. It is only used in an emergency error message that is very unlikely to ever occur, which is how this has remained unnoticed. Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| | * | memory: brcmstb: dpfe: rename struct private_dataMarkus Mayer2019-10-181-14/+14
| | |/ | | | | | | | | | | | | | | | | | | | | | To avoid potential (future) conflicts with other data structures we rename "struct private_data" to "struct brcmstb_dpfe_priv". Signed-off-by: Markus Mayer <mmayer@broadcom.com> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
| * | memory: samsung: exynos5422-dmc: Add support for interrupt from performance ↵Lukasz Luba2019-10-021-25/+320
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | counters Introduce a new interrupt driven mechanism for managing speed of the memory controller. The interrupts are generated due to performance counters overflow. The performance counters might track memory reads, writes, transfers, page misses, etc. In the basic algorithm tracking read transfers and calculating memory pressure should be enough to skip polling mode in devfreq. Signed-off-by: Lukasz Luba <l.luba@partner.samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 02:56:11 +0100