| Commit message (Collapse) | Author | Age | Files | Lines |
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For example, with SDIO WLAN cards, some transfers happen with buffers at
odd addresses, whereas the SH-Mobile DMA engine requires even addresses
for SDHI. This patch extends the tmio driver with a bounce buffer, that
is used for single entry scatter-gather lists both for sending and
receiving. If we ever encounter unaligned transfers with multi-element
sg lists, this patch will have to be extended. For now it just falls
back to PIO in this and other unsupported cases.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Samuel Ortiz <sameo@linux.intel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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drivers/mmc/host/tmio_mmc.h is only used by drivers/mmc/host/tmio_mmc.c,
this needlessly complicates source-code handling.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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The easiest way to fall back to PIO, when a DMA descriptor allocation
fails is to disable DMA on the controller but continue with the current
request in PIO mode. This way tmio_mmc_start_dma() can become void, since
it cannot be failing any more. The current version is also broken: it is
testing a wrong pointer and thus failing to recognise, that a descriptor
allocation wasn't successful.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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The driver is capable of handling multi-element sg lists in both PIO and
DMA modes. In DMA mode this also allows to use the DMA sg capability more
efficiently and almost doubles the throughput.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This adds the mmc host driver for the Synopsys DesignWare mmc
host controller, found in a number of embedded SoC designs.
Signed-off-by: Will Newton <will.newton@imgtec.com>
Reviewed-by: Matt Fleming <matt@console-pimps.org>
Reviewed-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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SDHCI driver for Tegra. This driver plugs in as a new variant of
sdhci-pltfm, using the platform data structure passed in to specify the
GPIOs to use for card detect, write protect and card power enablement.
Original driver (of which only the header file is left):
Signed-off-by: Yvonne Yip <y@palm.com>
The rest, which has been rewritten by now:
Signed-off-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Mike Rapoport <mike@compulab.co.il>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Some controllers misparse segment length 0 as being 0, not 65536. Add
a quirk to deal with it.
Signed-off-by: Olof Johansson <olof@lixom.net>
Reviewed-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This patch supports controllers with no internal clock divider in SDHCI,
such as the s5pc210 board. The external clock divider can be used to
make a proper clock because SDHCI doesn't support internal clock divider
by itself.
If external clock divider type is selected, some functions related
to clock control will be overrided by other functions.
The current clock control index is added to let you know which
clock bus is used for SDHCI when overriding functions.
Checking functions are added into sdhci_s3c_consider_clock, because
the clock divider step is different from that of host controller.
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
Cc: Jaehoon Chung <jh80.chung@samsung.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This patch adds support for additional host capabilities like SD/MMC
high speed, SDHCI bus width, etc.
Signed-off-by: Jeongbae Seo <jeongbae.seo@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Some old MMC devices fail with the 4/8 bits the driver tries to use
exclusively. This patch adds a test for the given bus setup and falls
back to the lower bit mode (until 1-bit mode) when the test fails.
[Major rework and refactoring by tiwai]
[Quirk addition and many fixes by prakity]
Signed-off-by: Aries Lee <arieslee@jmicron.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Philip Rakity <prakity@marvell.com>
Tested-by: Philip Rakity <prakity@marvell.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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JMicron 388 SD/MMC combo controller supports the 1.8V low-voltage for
SD, but MMC doesn't work with the low-voltage, resulting in an error
at probing.
This patch adds the support for multiple voltage mask per device type,
so that SD works with 1.8V while MMC forces 3.3V. Here new ocr_avail_*
fields for each device are introduced, so that the actual OCR mask is
switched dynamically.
Also, the restriction of low-voltage in core/sd.c is removed when the
bit is allowed explicitly via ocr_avail_sd mask.
This patch was rewritten from scratch based on Aries' original code.
Signed-off-by: Aries Lee <arieslee@jmicron.com>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Reviewed-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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More information should be shown when sdhci_dumpregs is called.
Knowing the command is useful for debugging, and Capability 1
is useful for SD v3.
Signed-off-by: Philip Rakity <prakity@marvell.com>
Reviewed-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This patch disables the broken ADMA on selected O2Micro devices.
Signed-off-by: Jennifer Li <Jennifer.li@o2micro.com>
Reviewed-by: Chris Ball <cjb@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Remove release_resource() after release_mem_region().
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This also fixes the build problem introduced by my previous patch
due to unhandled API changes introduced by commit:
99fc513101 (mmc: Move regulator handling closer to core)
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This implementation is based on the pxamci.c driver and it will
be used to support the mx31_3ds machine.
Signed-off-by: Alberto Panizzo <maramaopercheseimorto@gmail.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Implement an sdhci-pltfm driver for the controller found in the
Marvell Dove SoC.
Signed-off-by: Mike Rapoport <mike@compulab.co.il>
CC: Saeed Bishara <saeed@marvell.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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* 'for-2.6.38' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/wq: (33 commits)
usb: don't use flush_scheduled_work()
speedtch: don't abuse struct delayed_work
media/video: don't use flush_scheduled_work()
media/video: explicitly flush request_module work
ioc4: use static work_struct for ioc4_load_modules()
init: don't call flush_scheduled_work() from do_initcalls()
s390: don't use flush_scheduled_work()
rtc: don't use flush_scheduled_work()
mmc: update workqueue usages
mfd: update workqueue usages
dvb: don't use flush_scheduled_work()
leds-wm8350: don't use flush_scheduled_work()
mISDN: don't use flush_scheduled_work()
macintosh/ams: don't use flush_scheduled_work()
vmwgfx: don't use flush_scheduled_work()
tpm: don't use flush_scheduled_work()
sonypi: don't use flush_scheduled_work()
hvsi: don't use flush_scheduled_work()
xen: don't use flush_scheduled_work()
gdrom: don't use flush_scheduled_work()
...
Fixed up trivial conflict in drivers/media/video/bt8xx/bttv-input.c
as per Tejun.
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Workqueue creation API has been updated and flush_scheduled_work() is
deprecated and scheduled to be removed.
* core/core.c: Use alloc_ordered_workqueue() instead of
create_singlethread_workqueue(). This removes an unnecessary
rescuer.
* host/omap.c: Create, use and flush mmc_omap_wq instead of the
system_wq.
* Flush host->mmc_carddetect_work directly on removal instead of using
flush_scheduled_work().
Signed-off-by: Tejun Heo <tj@kernel.org>
Cc: Chris Ball <cjb@laptop.org>
Cc: linux-mmc@vger.kernel.org
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master.kernel.org:/pub/scm/linux/kernel/git/torvalds/linux-2.6 into rmobile-latest
Conflicts:
arch/arm/mach-shmobile/Kconfig
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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* 'devel' of master.kernel.org:/home/rmk/linux-2.6-arm: (416 commits)
ARM: DMA: add support for DMA debugging
ARM: PL011: add DMA burst threshold support for ST variants
ARM: PL011: Add support for transmit DMA
ARM: PL011: Ensure IRQs are disabled in UART interrupt handler
ARM: PL011: Separate hardware FIFO size from TTY FIFO size
ARM: PL011: Allow better handling of vendor data
ARM: PL011: Ensure error flags are clear at startup
ARM: PL011: include revision number in boot-time port printk
ARM: vexpress: add sched_clock() for Versatile Express
ARM i.MX53: Make MX53 EVK bootable
ARM i.MX53: Some bug fix about MX53 MSL code
ARM: 6607/1: sa1100: Update platform device registration
ARM: 6606/1: sa1100: Fix platform device registration
ARM i.MX51: rename IPU irqs
ARM i.MX51: Add ipu clock support
ARM: imx/mx27_3ds: Add PMIC support
ARM: DMA: Replace page_to_dma()/dma_to_page() with pfn_to_dma()/dma_to_pfn()
mx51: fix usb clock support
MX51: Add support for usb host 2
arch/arm/plat-mxc/ehci.c: fix errors/typos
...
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Make the MMCI announcement printk say which primecell part number
has been found. Display the revision as an unsigned decimal, and
display only the first 8 hex digits of the base address unless it's
larger.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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I misread the datasheet as if bypass mode was not available at all
on the ux500's, I was wrong. It is there, the datasheet just
states that you should not have to use it.
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The Ux500 variant of this block has a different divider.
The value used right now is too big and which means a loss
in performance. This fix corrects it. Also expand the math
comments a bit so it's clear what's happening. Further
the Ux500 variant does not like if we use the BYPASS bit,
instead we are supposed to set the clock divider to zero.
Signed-off-by: Ulf Hansson <ulf.hansson@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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This adds some minor variant data and trickery to enable SDIO
on the ST Micro variants of MMCI/PL180.
Signed-off-by: Marcin Mielczarczyk <marcin.mielczarczyk@tieto.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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On the U300 the MCI_DATAEND and MCI_DATABLOCKEND IRQs can arrive
out-of-order. Replace an ugly #ifdef hack with a proper runtime
solution which models what is really happening.
In the U300 DMA mode and on all Ux500 models, the MCI_DATABLOCKEND
flag isn't properly cleared in hardware following and ACK leading
to all kind of weird behaviour when the flag is still up in
subsequent interrupts, so we add two flags indicating the
error and handle this runtime.
Cc: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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The DBx500 variants have only one IRQ line hooked up. Allow these (and
any other implementations which choose to use only one irq) to work by
directing the PIO interrupts also to the first IRQ line.
Signed-off-by: Rabin Vincent <rabin.vincent@stericsson.com>
Signed-off-by: Linus Walleij <linus.walleij@stericsson.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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* 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm: (35 commits)
mmc: msm_sdcc: Check for only DATA_END interrupt to end a request
mmc: msm_sdcc: Fix bug in PIO mode when data size is not word aligned
mmc: msm_sdcc: Reset SDCC in case of data transfer errors
mmc: msm_sdcc: Add prog done interrupt support
mmc: msm_sdcc: Fix possible circular locking dependency warning
MSM: Add USB support for MSM7x30
MSM: Add USB suport for QSD8x50
msm: initial framebuffer support
msm: add handling for clocks tagged as CLK_MINMAX
msm: trout: change name of pmdh_clk to mddi_clk
msm: add CLK_MINMAX to pmdh_clk
msm: trout: add gpio_to_irq
msm: iommu: Use the correct memory allocation flag
msm_serial: Remove redundant unlikely()
msm: iommu: Miscellaneous code cleanup
msm: iommu: Support cache-coherent memory access
msm: iommu: Definitions for extended memory attributes
msm: iommu: Kconfig dependency for the IOMMU API
msm: iommu: Check if device is already attached
msm: iommu: Kconfig item for cacheable page tables
...
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* msm-core: (28 commits)
msm: initial framebuffer support
msm: add handling for clocks tagged as CLK_MINMAX
msm: trout: change name of pmdh_clk to mddi_clk
msm: add CLK_MINMAX to pmdh_clk
msm: trout: add gpio_to_irq
msm: iommu: Use the correct memory allocation flag
msm_serial: Remove redundant unlikely()
msm: iommu: Miscellaneous code cleanup
msm: iommu: Support cache-coherent memory access
msm: iommu: Definitions for extended memory attributes
msm: iommu: Kconfig dependency for the IOMMU API
msm: iommu: Check if device is already attached
msm: iommu: Kconfig item for cacheable page tables
msm: iommu: Don't flush page tables if no devices attached
msm: iommu: Mark functions with the right section names
msm: iommu: Support for the 2nd GFX core's IOMMU
msm: iommu: Revise GFX2D0 IOMMU contexts and M2V mappings
msm: iommu: Revise GFX3D IOMMU contexts and M2V mappings
msm: iommu: Use more consistent naming in platform data
msm: iomap: Addresses and IRQs for 2nd GFX core IOMMU
...
* msm-mmc: (33 commits)
mmc: msm_sdcc: Check for only DATA_END interrupt to end a request
mmc: msm_sdcc: Fix bug in PIO mode when data size is not word aligned
mmc: msm_sdcc: Reset SDCC in case of data transfer errors
mmc: msm_sdcc: Add prog done interrupt support
mmc: msm_sdcc: Fix possible circular locking dependency warning
msm: initial framebuffer support
msm: add handling for clocks tagged as CLK_MINMAX
msm: trout: change name of pmdh_clk to mddi_clk
msm: add CLK_MINMAX to pmdh_clk
msm: trout: add gpio_to_irq
msm: iommu: Use the correct memory allocation flag
msm_serial: Remove redundant unlikely()
msm: iommu: Miscellaneous code cleanup
msm: iommu: Support cache-coherent memory access
msm: iommu: Definitions for extended memory attributes
msm: iommu: Kconfig dependency for the IOMMU API
msm: iommu: Check if device is already attached
msm: iommu: Kconfig item for cacheable page tables
msm: iommu: Don't flush page tables if no devices attached
msm: iommu: Mark functions with the right section names
...
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The current code checks for both DATA_END and DATA_BLK_END bits in
MCI_STATUS register and ends a request only if both are set at a time.
The hardware doesn't always set DATA_BLK_END when DATA_END is set.
But DATA_END status itself is sufficient condition from hardware that
data transfer is done and hence, check for only DATA_END interrupt in
software to end a request.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
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The current code for PIO doesn't transfer whole data when data size
is not in multiple of 4 bytes. The last few bytes are not written to
the card resulting in no DATAEND interrupt from SDCC. This patch
allows data transfer for non-aligned data size in PIO mode.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
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SDCC uses an asynchronous FIFOs for data synchronization (one for TX
and one for RX). For any error when DPSM (Data path state machine) is
involved the transfer is terminated with the remaining data stuck inside
FIFOs. Reset the controller in case of data errors to ensure that
any left over data in FIFOs is flushed out and DPSM is in good state.
The following problems are observed without this reset functionality -
1. After the card is removed in an unsafe way (removed when there
is an on going data transfer), the card will not be detected upon
its next insertion. This is because the controller wouldn't respond
to few initialization commands.
2. When an error occurs for a data transfer in non-DMA mode, sometimes
we get spurious PIO interrupt after the request is processed.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
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Enable prog done interrupt for stop command(CMD12) that is sent
after a multi-block write(CMD25). The PROG_DONE bit is set when
the card has finished its programming and is ready for next data.
After every write request the card will be polled for ready status
using CMD13. For a multi-block write(CMD25) before sending CMD13,
stop command (CMD12) will be sent. If we enable prog done interrupt
for CMD12, then CMD13 polling can be avoided. The prog done interrupt
means that the card is done with its programming and is ready for
next request.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
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In the context of request processing thread, data mover lock is
acquired after the host lock. In another context, in the completion
handler of data mover the locks are acquired in the reverse order,
resulting in possible circular lock dependency warning. Hence,
schedule a tasklet to process the dma completion so as to avoid
nested locks.
Signed-off-by: Sahitya Tummala <stummala@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
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Based on report made by Yauhen in:
"MMC: Fix multiblock SDIO transfers in AT91 MCI" patch,
I report those changes to the brother driver: atmel-mci.
So, this patch sets SDIO transfer types: SDIO block and SDIO byte
transfers instead of using ordinary MMC block transfers.
It is checking opcode for SDIO CMD53 and setting transfer
type in MCI_CMDR register properly.
Reported-by: Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
Cc: <stable@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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The AT91 MCI has special SDIO transfer types: SDIO block and SDIO byte
transfers, but at91_mci driver doesn't use them and handles all SDIO
transfers as ordinary MMC block transfers. This causes problems for
multiple-block SDIO transfers (in particular for 256-bytes blocks).
Fix this situation by checking the opcode for SDIO CMD53 and setting
the transfer type in the AT91_MCI_CMDR register properly.
This patch was tested with libertas SDIO driver: problem with TX
timeouts on big packets was eliminated.
Signed-off-by: Yauhen Kharuzhy <yauhen.kharuzhy@promwad.com>
Cc: <stable@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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rmobile-latest
Conflicts:
arch/arm/mach-shmobile/Kconfig
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Simplify the driver by removing the possibility to build it without the DMA
support and remove the respective Kconfig parameter.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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Conflicts:
arch/arm/mach-shmobile/include/mach/entry-macro.S
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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We now:
* check for a v3 controller before setting 8-bit bus width
* offer a callback for platform code to switch to 8-bit mode, which
allows non-v3 controllers to support it
* rely on mmc->caps |= MMC_CAP_8_BIT_DATA; in platform code to specify
that the board designers have indeed brought out all the pins for
8-bit to the slot.
We were previously relying only on whether the *controller* supported
8-bit, which doesn't tell us anything about the pin configuration in
the board design.
This fixes the MMC card regression reported by Maxim Levitsky here:
http://thread.gmane.org/gmane.linux.kernel.mmc/4336
by no longer assuming that 8-bit works by default.
Signed-off-by: Philip Rakity <prakity@marvell.com>
Tested-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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While booting OMAP4 ES2.0 boards, cards on MMC1 and MMC2 controllers
are not getting detected sometimes.
During reset of command/data line, wrong pointer to base address
was passed while read operation to SYSCTL register, thus impacting
the updated reset logic.
Passing the correct base address fixes the issue.
Signed-off-by: Kishore Kadiyala <kishore.kadiyala@ti.com>
Acked-by: Felipe Balbi <balbi@ti.com>
Acked-by: Madhusudhan Chikkature <madhu.cr@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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SDHC2 is newly added in C0 stepping of Langwell. Without the Moorestown
specific quirk, the default pci_probe will be called and crash the kernel.
This patch unblocks the crash problem on C0 by using the same probing
function as HC1, which limits the number of slots to one.
Signed-off-by: Jacob Pan <jacob.jun.pan@linux.intel.com>
Signed-off-by: Alan Cox <alan@linux.intel.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Only these CPUs list the bug in their errata.
Signed-off-by: Eric Bénard <eric@eukrea.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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This patch fixes timeout problems on i.MX's sdhci as suggested by
Richard Zhu.
Tested on:
- i.MX257: not needed
- i.MX357: needed
- i.MX515: needed
More details can be found here:
http://lists.infradead.org/pipermail/linux-arm-kernel/2010-October/029748.html
Signed-off-by: Eric Bénard <eric@eukrea.com>
Tested-by: Shawn Guo <shawn.gsc@gmail.com>
Acked-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Chris Ball <cjb@laptop.org>
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A little more work was needed for SDIO IRQ wakeups to be functional.
Wake-on-WLAN on the SD WiFi adapter in the XO-1.5 laptop is now working.
Signed-off-by: Daniel Drake <dsd@laptop.org>
Signed-off-by: Chris Ball <cjb@laptop.org>
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Improves error handling in the ushc driver.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Acked-by: David Vrabel <david.vrabel@csr.com>
Signed-off-by: Chris Ball <cjb@laptop.org>
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The MMCIF controller on sh-mobile platforms can use the DMA controller for data
transfers. Interface to the SH dmaengine driver to enable DMA. We also have to
lower the maximum number of segments to match with the number od DMA
descriptors on SuperH, this doesn't significantly affect driver's PIO
performance.
Signed-off-by: Guennadi Liakhovetski <g.liakhovetski@gmx.de>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
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