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* Merge tag 'clk-for-linus-3.20' of ↵Linus Torvalds2015-02-211-15/+48
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.linaro.org/people/mike.turquette/linux Pull clock framework updates from Mike Turquette: "The clock framework changes contain the usual driver additions, enhancements and fixes mostly for ARM32, ARM64, MIPS and Power-based devices. Additionally the framework core underwent a bit of surgery with two major changes: - The boundary between the clock core and clock providers (e.g clock drivers) is now more well defined with dedicated provider helper functions. struct clk no longer maps 1:1 with the hardware clock but is a true per-user cookie which helps us tracker users of hardware clocks and debug bad behavior. - The addition of rate constraints for clocks. Rate ranges are now supported which are analogous to the voltage ranges in the regulator framework. Unfortunately these changes to the core created some breakeage. We think we fixed it all up but for this reason there are lots of last minute commits trying to undo the damage" * tag 'clk-for-linus-3.20' of git://git.linaro.org/people/mike.turquette/linux: (113 commits) clk: Only recalculate the rate if needed Revert "clk: mxs: Fix invalid 32-bit access to frac registers" clk: qoriq: Add support for the platform PLL powerpc/corenet: Enable CLK_QORIQ clk: Replace explicit clk assignment with __clk_hw_set_clk clk: Add __clk_hw_set_clk helper function clk: Don't dereference parent clock if is NULL MIPS: Alchemy: Remove bogus args from alchemy_clk_fgcs_detr clkdev: Always allocate a struct clk and call __clk_get() w/ CCF clk: shmobile: div6: Avoid division by zero in .round_rate() clk: mxs: Fix invalid 32-bit access to frac registers clk: omap: compile legacy omap3 clocks conditionally clkdev: Export clk_register_clkdev clk: Add rate constraints to clocks clk: remove clk-private.h pci: xgene: do not use clk-private.h arm: omap2+ remove dead clock code clk: Make clk API return per-user struct clk instances clk: tegra: Define PLLD_DSI and remove dsia(b)_mux clk: tegra: Add support for the Tegra132 CAR IP block ...
| * Merge branch 'clk-next' into v3.19-rc7Michael Turquette2015-02-021-24/+49
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| | * mmc: sunxi: Convert MMC driver to the standard clock phase APIMaxime Ripard2015-01-141-24/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we have proper support to use the generic phase API in our clock driver, switch the MMC driver to use it. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Acked-by: Ulf Hansson <ulf.hansson@linaro.org> Acked-by: David Lanzendörfer <david.lanzendoerfer@o2s.ch> Reviewed-by: Chen-Yu Tsai <wens@csie.org> Tested-by: Chen-Yu Tsai <wens@csie.org>
* | | mmc: sdhci-s3c: solve problem with sleeping in atomic contextPaul Osmialowski2015-02-041-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change addresses following problem: [ 2.560726] ------------[ cut here ]------------ [ 2.565341] WARNING: CPU: 0 PID: 1 at kernel/locking/lockdep.c:2744 lockdep_trace_alloc+0xec/0x118() [ 2.574439] DEBUG_LOCKS_WARN_ON(irqs_disabled_flags(flags)) [ 2.579821] Modules linked in: [ 2.583038] CPU: 0 PID: 1 Comm: swapper/0 Tainted: G W 3.18.0-next-20141216-00002-g4ff197fc1902-dirty #1318 [ 2.593796] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree) [ 2.599892] [<c0014c44>] (unwind_backtrace) from [<c0011bbc>] (show_stack+0x10/0x14) [ 2.607612] [<c0011bbc>] (show_stack) from [<c04953b8>] (dump_stack+0x70/0xbc) [ 2.614822] [<c04953b8>] (dump_stack) from [<c0023444>] (warn_slowpath_common+0x74/0xb0) [ 2.622885] [<c0023444>] (warn_slowpath_common) from [<c0023514>] (warn_slowpath_fmt+0x30/0x40) [ 2.631569] [<c0023514>] (warn_slowpath_fmt) from [<c0063644>] (lockdep_trace_alloc+0xec/0x118) [ 2.640246] [<c0063644>] (lockdep_trace_alloc) from [<c00df52c>] (__kmalloc+0x3c/0x1cc) [ 2.648240] [<c00df52c>] (__kmalloc) from [<c0394970>] (clk_fetch_parent_index+0xb8/0xd4) [ 2.656390] [<c0394970>] (clk_fetch_parent_index) from [<c0394a6c>] (clk_calc_new_rates+0xe0/0x1fc) [ 2.665415] [<c0394a6c>] (clk_calc_new_rates) from [<c0394b40>] (clk_calc_new_rates+0x1b4/0x1fc) [ 2.674181] [<c0394b40>] (clk_calc_new_rates) from [<c0395408>] (clk_set_rate+0x50/0xc8) [ 2.682265] [<c0395408>] (clk_set_rate) from [<c0377708>] (sdhci_cmu_set_clock+0x68/0x16c) [ 2.690503] [<c0377708>] (sdhci_cmu_set_clock) from [<c03735cc>] (sdhci_do_set_ios+0xf0/0x64c) [ 2.699095] [<c03735cc>] (sdhci_do_set_ios) from [<c0373b48>] (sdhci_set_ios+0x20/0x2c) [ 2.707080] [<c0373b48>] (sdhci_set_ios) from [<c035ddf0>] (mmc_power_up+0x118/0x1fc) [ 2.714889] [<c035ddf0>] (mmc_power_up) from [<c035ecd0>] (mmc_start_host+0x44/0x6c) [ 2.722615] [<c035ecd0>] (mmc_start_host) from [<c035fd60>] (mmc_add_host+0x58/0x7c) [ 2.730341] [<c035fd60>] (mmc_add_host) from [<c037454c>] (sdhci_add_host+0x968/0xd94) [ 2.738240] [<c037454c>] (sdhci_add_host) from [<c0377b60>] (sdhci_s3c_probe+0x354/0x52c) [ 2.746406] [<c0377b60>] (sdhci_s3c_probe) from [<c0283b58>] (platform_drv_probe+0x48/0xa4) [ 2.754733] [<c0283b58>] (platform_drv_probe) from [<c02824e8>] (driver_probe_device+0x13c/0x37c) [ 2.763585] [<c02824e8>] (driver_probe_device) from [<c02827bc>] (__driver_attach+0x94/0x98) [ 2.772003] [<c02827bc>] (__driver_attach) from [<c0280a60>] (bus_for_each_dev+0x54/0x88) [ 2.780163] [<c0280a60>] (bus_for_each_dev) from [<c0281b48>] (bus_add_driver+0xe4/0x200) [ 2.788322] [<c0281b48>] (bus_add_driver) from [<c0282dfc>] (driver_register+0x78/0xf4) [ 2.796308] [<c0282dfc>] (driver_register) from [<c00089b0>] (do_one_initcall+0xac/0x1f0) [ 2.804473] [<c00089b0>] (do_one_initcall) from [<c0673d94>] (kernel_init_freeable+0x10c/0x1d8) [ 2.813153] [<c0673d94>] (kernel_init_freeable) from [<c0490058>] (kernel_init+0x28/0x108) [ 2.821398] [<c0490058>] (kernel_init) from [<c000f268>] (ret_from_fork+0x14/0x2c) [ 2.828939] ---[ end trace 03cc00e539849d1f ]--- clk_set_rate() tries to take clk's prepare_lock mutex while being in atomic context entered in sdhci_do_set_ios(). The solution is inspired by similar situation in sdhci_set_power() also called from sdhci_do_set_ios(): spin_unlock_irq(&host->lock); mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); spin_lock_irq(&host->lock); Note that since sdhci_s3c_set_clock() sets SDHCI_CLOCK_CARD_EN, proposed change first resets this bit. It is reset anyway (by setting SDHCI_CLOCK_INT_EN bit only) after call to clk_set_rate() in order to wait for the clock to stabilize and is set again as soon as the clock becomes stable. Signed-off-by: Paul Osmialowski <p.osmialowsk@samsung.com> Tested-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: pwrseq: add driver for emmc hardware resetMarek Szyprowski2015-02-044-1/+106
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provides a simple mmc-pwrseq-emmc driver, which controls single gpio line. It perform standard eMMC hw reset procedure, as descibed by Jedec 4.4 specification. This procedure is performed just after MMC core enabled power to the given mmc host (to fix possible issues if bootloader has left eMMC card in initialized or unknown state), and before performing complete system reboot (also in case of emergency reboot call). The latter is needed on boards, which doesn't have hardware reset logic connected to emmc card and (limited or broken) ROM bootloaders are unable to read second stage from the emmc card if the card is left in unknown or already initialized state. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: moxart: fix probe logicArnd Bergmann2015-02-041-11/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Jonas Jensen wanted to submit a patch for these, but apparently forgot about it. I stumbled over this symptom first: drivers/built-in.o: In function `moxart_probe': :(.text+0x2af128): undefined reference to `of_dma_request_slave_channel' This is because of_dma_request_slave_channel is an internal helper and not exported to loadable module. I'm changing the driver to use dma_request_slave_channel_reason() instead. Further problems from inspection: * The remove function must not call kfree on the host pointer, because it is allocated together with the mmc_host. * The clock is never released * The dma_cap_mask_t is completely unused and can be removed * deferred probing does not work if the dma driver is loaded after the mmc driver. This patch should fix all of the above. Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: core: Invoke mmc_pwrseq_post_power_on() prior MMC_POWER_ON stateUlf Hansson2015-02-031-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Host drivers have different ways to sends their "init stream" to the card. Some need to do it as part of a request, some do it from the ->set_ios() callback in the MMC_POWER_ON state and some don't send an "init stream" at all. To be able to use the reset GPIOs from the simple MMC power sequence provider, the card need to be powered and the "init stream" must not have been sent. To cope with these requirements, invoke mmc_pwrseq_post_power_on() prior we change the state to MMC_POWER_ON in mmc_power_up(). Host drivers shall perform power up operations in the MMC_POWER_UP state. Unfortunate three hosts (au1xmmc, cb710-mmc and toshsd) don't conform to this expectation. Instead those ignore the MMC_POWER_UP state and delays their power up operations to the MMC_POWER_ON state. Those hosts needs to change their behavior to enable proper support for the simple MMC power sequence provider. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
* | | mmc: pwrseq_simple: Add optional reference clock supportJavier Martinez Canillas2015-01-301-2/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some WLAN chips attached to a SDIO interface, need a reference clock. Since this is very common, extend the prseq_simple driver to support an optional clock that is enabled prior the card power up procedure. Note: the external clock is optional. Thus an error is not returned if the clock is not found. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: pwrseq_simple: Extend to support more pinsJavier Martinez Canillas2015-01-301-15/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Many WLAN attached to a SDIO/MMC interface, needs more than one pin for their reset sequence. For example, is very common for chips to have two pins: one for reset and one for power enable. This patch adds support for more reset pins to the pwrseq_simple driver and instead hardcoding a fixed number, it uses the of_gpio_named_count() since the MMC power sequence is only built when CONFIG_OF is enabled. Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: Add hardware dependencies for sdhci-pxav3 and sdhci-pxav2Jean Delvare2015-01-301-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I seem to understand that the sdhci-pxav3 and sdhci-pxav2 drivers are only needed on the MMP architecture. So add a hardware dependency on ARCH_MMP, so that other users don't get to build useless drivers. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Chris Ball <chris@printf.net> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Eric Miao <eric.y.miao@gmail.com> Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pxav3: Modify clock settings for the SDR50 and DDR50 modesMarcin Wojtas2015-01-291-8/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to erratum 'FE-2946959' both SDR50 and DDR50 modes require specific clock adjustments in SDIO3 Configuration register. This commit add the support of this register and for SDR50 or DDR50 mode use it as suggested by the erratum: - Set the SDIO3 Clock Inv field in SDIO3 Configuration register to not inverted. - Set the Sample FeedBack Clock field to 0x1 [gregory.clement@free-electrons.com: port from 3.10] Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pxav3: Fix Armada 38x controller's caps according to erratum ↵Marcin Wojtas2015-01-291-5/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ERR-7878951 According to erratum 'ERR-7878951' Armada 38x SDHCI controller has different capabilities than the ones shown in its registers: - it doesn't support the voltage switching: it can work either with 3.3V or 1.8V supply - it doesn't support the SDR104 mode - SDR50 mode doesn't need tuning The SDHCI_QUIRK_MISSING_CAPS quirk is used for updating the capabilities accordingly. [gregory.clement@free-electrons.com: port from 3.10] Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller") Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pxav3: Fix SDR50 and DDR50 capabilities for the Armada 38x flavorGregory CLEMENT2015-01-291-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to erratum 'FE-2946959' both SDR50 and DDR50 modes require specific clock adjustments in SDIO3 Configuration register. However, this register was not part of the device tree binding. Even if the binding can (and will) be extended we still need handling the case where this register was not available. In this case we use the SDHCI_QUIRK_MISSING_CAPS quirk remove them from the capabilities. This commit is based on the work done by Marcin Wojtas<mw@semihalf.com> Fixes: 5491ce3f79ee ("mmc: sdhci-pxav3: add support for the Armada 38x SDHCI controller") Cc: <stable@vger.kernel.org> # v3.15+ Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com> Signed-off-by: Marcin Wojtas <mw@semihalf.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: switch voltage before sdhci_set_ios in runtime resumeJisheng Zhang2015-01-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I observed the Host Control2 register isn't correctly restored after runtime resuming on BG2Q. For example, the register reads as 0x800c before runtime suspend, but it's set as 0x8004 after runtime resuming. This could results in a non working host. The reason is the Host Control2 is incorrectly reset when switching voltage. We fix this by following the same sequence during initialization. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: tegra: Write xfer_mode, CMD regs in togetherPavan Kunapuli2015-01-291-1/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If there is a gap between xfer mode and command register writes, tegra SDMMC controller can sometimes issue a spurious command before the CMD register is written. To avoid this, these two registers need to be written together in a single write operation. This is implemented as an NVQUIRK as it applies to T114, T124 and T132. Signed-off-by: Pavan Kunapuli <pkunapuli@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: Resolve BKOPS compatability issueAlexey Skidanov2015-01-292-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is coming to fix compatibility issue of BKOPS_EN field of EXT_CSD. In eMMC-5.1, BKOPS_EN was changed, and now it has two operational bits: Bit 0 - MANUAL_EN Bit 1 - AUTO_EN In previous eMMC revisions, only Bit 0 was supported. Signed-off-by: Alexey Skidanov <alexey.skidanov@sandisk.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pxav3: fix setting of pdata->clk_delay_cyclesJisheng Zhang2015-01-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code checks "clk_delay_cycles > 0" to know whether the optional "mrvl,clk_delay_cycles" is set or not. But of_property_read_u32() doesn't touch clk_delay_cycles if the property is not set. And type of clk_delay_cycles is u32, so we may always set pdata->clk_delay_cycles as a random value. This patch fix this problem by check the return value of of_property_read_u32() to know whether the optional clk-delay-cycles is set or not. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: <stable@vger.kernel.org> # v3.6+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: rockchip: remove incorrect __exit_p()Dmitry Torokhov2015-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dw_mci_pltfm_remove() is not (nor should it be) marked as __exit, so we should not be using __exit_p() wrapper with it. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: dw_mmc: exynos: remove incorrect __exit_p()Dmitry Torokhov2015-01-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | dw_mci_pltfm_remove() is not (nor should it be) marked as __exit, so we should not be using __exit_p() wrapper with it. Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com> Reviewed-by: Doug Anderson <dianders@chromium.org> Tested-by: Doug Anderson <dianders@chromium.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: Fix menuconfig alignment of MMC_SDHCI_* optionsJean Delvare2015-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let MMC_SDHCI_BIG_ENDIAN_32BIT_BYTE_SWAPPER depend on MMC_SDHCI. Not only this is more correct, but this also avoids breaking the alignment of all other MMC_SDHCI_* options in menuconfig. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Chris Ball <chris@printf.net> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Albert Herranz <albert_herranz@yahoo.es> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: Enable Ricoh MMC quirk by defaultJean Delvare2015-01-281-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config option MMC_RICOH_MMC's help text reads: If unsure, say Y. However the option defaults to N. Set the default to Y to match the recommendation in the help text. Signed-off-by: Jean Delvare <jdelvare@suse.de> Cc: Chris Ball <chris@printf.net> Cc: Ulf Hansson <ulf.hansson@linaro.org> Cc: Philipl Langdale <philipl@overt.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: mmci: Get rid of dead code in mmci_dma_setupPramod Gurav2015-01-281-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | DMA configuration has been removed from function mmci_dma_setup but the local mask variable was not removed. This remains unused hence remove it from the function and operations on it Signed-off-by: Pramod Gurav <pramod.gurav@smartplayin.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci-pxav3: fix race between runtime pm and irqJisheng Zhang2015-01-281-10/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is to fix a race condition that may cause an unhandled irq, which results in big sdhci interrupt numbers and endless "mmc1: got irq while runtime suspended" msgs before v3.15. Consider following scenario: CPU0 CPU1 sdhci_pxav3_runtime_suspend() spin_lock_irqsave(&host->lock, flags); sdhci_irq() spining on the &host->lock host->runtime_suspended = true; spin_unlock_irqrestore(&host->lock, flags); get the &host->lock runtime_suspended is true now return IRQ_NONE; Fix this race by using the core sdhci.c supplied sdhci_runtime_suspend_host() in runtime suspend hook which will disable card interrupts. We also use the sdhci_runtime_resume_host() in the runtime resume hook accordingly. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Cc: <stable@vger.kernel.org> # v3.9+ Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: block: Remove unnecessary temporary variableTobias Klauser2015-01-281-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | Directly return the result of mmc_blk_alloc_req() instead of assigning and returning the variable md. Signed-off-by: Tobias Klauser <tklauser@distanz.ch> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: pwrseq_simple: Add support for a reset GPIO pinUlf Hansson2015-01-281-0/+38
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The need for reset GPIOs has several times been pointed out from erlier posted patchsets. Especially some WLAN chips which are attached to an SDIO interface may use a GPIO reset. The reset GPIO is asserted at initialization and prior we start the power up procedure. The GPIO will be de-asserted right after the power has been provided to the card, from the ->post_power_on() callback. Note, the reset GPIO is optional. Thus we don't return an error even if we can't find a GPIO for the consumer. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
* | | mmc: pwrseq: Initial support for the simple MMC power sequence providerUlf Hansson2015-01-284-2/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To add the core part for the MMC power sequence, let's start by adding initial support for the simple MMC power sequence provider. In this initial step, the MMC power sequence node are fetched and the compatible string for the simple MMC power sequence provider are verified. At this point we don't parse the node for any properties, but instead that will be handled from following patches. Since there are no properties supported yet, let's just implement the ->alloc() and the ->free() callbacks. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
* | | mmc: core: Initial support for MMC power sequencesUlf Hansson2015-01-285-2/+101
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | System on chip designs may specify a specific MMC power sequence. To successfully detect an (e)MMC/SD/SDIO card, that power sequence must be followed while initializing the card. To be able to handle these SOC specific power sequences, let's add a MMC power sequence interface. It provides the following functions to help the mmc core to deal with these power sequences. mmc_pwrseq_alloc() - Invoked from mmc_of_parse(), to initialize data. mmc_pwrseq_pre_power_on()- Invoked in the beginning of mmc_power_up(). mmc_pwrseq_post_power_on()- Invoked at the end in mmc_power_up(). mmc_pwrseq_power_off()- Invoked from mmc_power_off(). mmc_pwrseq_free() - Invoked from mmc_free_host(), to free data. Each MMC power sequence provider will be responsible to implement a set of callbacks. These callbacks mirrors the functions above. This patch adds the skeleton, following patches will extend the core of the MMC power sequence and add support for a specific simple MMC power sequence. Do note, since the mmc_pwrseq_alloc() is invoked from mmc_of_parse(), host drivers needs to make use of this API to enable the support for MMC power sequences. Moreover the MMC power sequence support depends on CONFIG_OF. Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org> Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk> Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
* | | mmc: sdhci-pxav3: Remove checks for optional core clock in error/remove pathJisheng Zhang2015-01-211-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 63589e92c2d9 ("clk: Ignore error and NULL pointers passed to clk_{unprepare, disable}()") allows NULL or error pointer to be passed unconditionally. This patch is to simplify probe error and remove code paths. However, we reserve the core clock checks in runtime suspend/resume code because we want a little smaller latency. Signed-off-by: Jisheng Zhang <jszhang@marvell.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: rtsx: check sg_count before long data xferMicky Ching2015-01-211-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check sg_count before sending long data xfer. Because dma_map_sg() return int, and sg_count may be negative, so using int instead of unsigned. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: rtsx: finish request if no card existMicky Ching2015-01-211-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | Return error-code directly if no card exist, this can make card remove faster. Signed-off-by: Micky Ching <micky_ching@realsil.com.cn> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: sdhci: host: fix odd_ptr_err.cocci warningsWu Fengguang2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/mmc/host/sdhci_f_sdh30.c:143:5-11: inconsistent IS_ERR and PTR_ERR, PTR_ERR on line 144 PTR_ERR should access the value just tested by IS_ERR Semantic patch information: There can be false positives in the patch case, where it is the call IS_ERR that is wrong. Generated by: scripts/coccinelle/tests/odd_ptr_err.cocci CC: Vincent Yang <vincent.yang.fujitsu@gmail.com> Signed-off-by: Fengguang Wu <fengguang.wu@intel.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: vub300: remove unreachable return value handlingNicholas Mc Guire2015-01-211-3/+1
| | | | | | | | | | | | | | | Signed-off-by: Nicholas Mc Guire <der.herr@hofr.at> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | mmc: block: fix format string warningAsaf Vertz2015-01-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Fixed the following warning (reported by cppcheck): [drivers/mmc/card/block.c:2149]: (warning) %d in format string (no. 1) requires 'int' but the argument type is 'unsigned int'. Signed-off-by: Asaf Vertz <asaf.vertz@tandemg.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
* | | Merge branch 'tmio' into nextUlf Hansson2015-01-205-110/+164
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| * | | mmc: tmio: remove TMIO_MMC_HAVE_CTL_DMA_REG flagKuninori Morimoto2015-01-202-8/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tmio_mmc_host has .enable_dma callback now. We don't need TMIO_MMC_HAVE_CTL_DMA_REG anymore. Let's remove it Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: sh_mobile_sdhi: enable 32bit DMA accessKuninori Morimoto2015-01-201-9/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now, sh_mobile_sdhi can use 32bit DMA access in R-Cer Gen2. Let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: sh_mobile_sdhi: use .enable_dmaKuninori Morimoto2015-01-201-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | tmio_mmc_dma has .enable_dma callback now. let's use it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: sh_mobile_sdhi: add new macro for mmc_host to sh_mobile_sdhiKuninori Morimoto2015-01-201-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | getting struct sh_mobile_sdhi from struct mmc_host needs to use complex container_of(). This patch adds new host_to_priv macro to get it easily. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: sh_mobile_sdhi: tidyup mmc_data->bus_shift for latest SoCKuninori Morimoto2015-01-201-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Latest SDHI on Renesas has expand register mapping. update mmc_data->bus_shift for it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: sh_mobile_sdhi: remove .init/.cleanupKuninori Morimoto2015-01-201-25/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No one is using .init/.cleanup callback function. Let's remove these. sdhi_ops and .cd_wakeup are also removed Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: enable SoC specific DMA buswidth settingsKuninori Morimoto2015-01-202-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Renesas SDHI which is based on TMIO driver has 2 type SoC. 1st one is used as SH-Mobile series, and 2nd is R-Car series. R-Car series SoC has DMA buswidth setting register which enables 32bit access. This patch adds .dma_buswidth and enables it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: add .enable_dma on tmio_mmc_dmaKuninori Morimoto2015-01-202-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some controllers need DMA special register/setting. This patch adds new .enable_dma callback for it. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_data has .dma_rx_offsetKuninori Morimoto2015-01-203-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .dma_rx_offset is implemented under tmio_mmc_dma. It goes to tmio_mmc_data by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_data has .alignment_shiftKuninori Morimoto2015-01-203-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .alignment_shift is implemented under tmio_mmc_dma. It goes to tmio_mmc_data by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .bus_shiftKuninori Morimoto2015-01-204-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .bus_shift is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .multi_io_quirkKuninori Morimoto2015-01-203-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .multi_io_quirk is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .clk_disableKuninori Morimoto2015-01-203-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .clk_disable is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .clk_enableKuninori Morimoto2015-01-203-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .clk_enable is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .write16_hookKuninori Morimoto2015-01-203-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .write16_hook is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
| * | | mmc: tmio: tmio_mmc_host has .dmaKuninori Morimoto2015-01-203-15/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current .dma is implemented under tmio_mmc_data. It goes to tmio_mmc_host by this patch. Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Acked-by: Lee Jones <lee.jones@linaro.org> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-29 10:34:26 +0100