| Commit message (Collapse) | Author | Age | Files | Lines |
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Pull arm-soc board specific changes from Olof Johansson:
"While we generally attempt to get rid of board specific files and
replace them with device tree based descriptions, a lot of platforms
have not come that far:
In shmobile, we add two new board files because their recently started
effort to add DT support has not proceeded enough to use it for all of
the important hardware.
In Kirkwood, we are adding support for new boards with a combination
of DT and board file contents in multiple cases.
pxa/mmp and imx are extending support for existing board files but not
adding new ones."
Fix up trivial conflicts in arch/arm/mach-{mmp/ttc_dkb.c,shmobile/{Kconfig,Makefile}}
* tag 'boards' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (94 commits)
ARM: shmobile: fix smp build
ARM: kirkwood: Add support for RaidSonic IB-NAS6210/6220 using devicetree
kirkwood: Add iconnect support
orion/kirkwood: create a generic function for gpio led blinking
kirkwood/orion: fix orion_gpio_set_blink
ARM: kirkwood: Define DNS-320/DNS-325 NAND in fdt
kirkwood: Allow nand to be configured via. devicetree
mtd: Add orion_nand devicetree bindings
ARM: kirkwood: Basic support for DNS-320 and DNS-325
ARM: mach-shmobile: Use DT_MACHINE for armadillo 800 eva
ARM: mach-shmobile: Use DT_MACHINE for KZM9G
ARM: pxa: hx4700: Add Synaptics NavPoint touchpad
ARM: pxa: Use REGULATOR_SUPPLY macro
ARM: mach-shmobile: kzm9g: enable SMP boot
ARM: mach-shmobile: kzm9g: defconfig update
ARM: mach-shmobile: kzm9g: add PCF8757 gpio-key
ARM: mach-shmobile: kzm9g: add SDHI support
ARM: mach-shmobile: kzm9g: add MMCIF support
ARM: mach-shmobile: kzm9g: correct screen direction
ARM: mach-shmobile: sh73a0.h: add GPIO_NR
...
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Allow a NAND chip using the orion_nand driver to be described using devicetree.
Changes since last submission (V4) [Addressing comments by]:-
* WARN when bank-width is out of range [Andrew Lunn]
Changes since last submission (V3):-
* Document all parameters [Grant Likely]
* Convert bank-width to be in bytes
* Add explicit defaults for cle, ale and bank-width
Signed-off-by: Jamie Lentin <jm@lentin.co.uk>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
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Pull arm soc-specific pinctrl changes from Olof Johansson:
"With this, five platforms are moving to the relatively new pinctrl
subsystem for their pin management, replacing the older soc specific
in-kernel interfaces with common code.
There is quite a bit of net addition of code for each platform being
added to the pinctrl subsystem. But the payback comes later when
adding new boards can be done by only providing new device trees
instead."
Fix up trivial conflicts in arch/arm/mach-ux500/{Makefile,board-mop500.c}
* tag 'pinctrl' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (61 commits)
mtd: nand: gpmi: fix compile error caused by pinctrl call
ARM: PRIMA2: select PINCTRL and PINCTRL_SIRF in Kconfig
ARM: nomadik: enable PINCTRL_NOMADIK where needed
ARM: mxs: enable pinctrl support
video: mxsfb: adopt pinctrl support
ASoC: mxs-saif: adopt pinctrl support
i2c: mxs: adopt pinctrl support
mtd: nand: gpmi: adopt pinctrl support
mmc: mxs-mmc: adopt pinctrl support
serial: mxs-auart: adopt pinctrl support
serial: amba-pl011: adopt pinctrl support
spi/imx: adopt pinctrl support
i2c: imx: adopt pinctrl support
can: flexcan: adopt pinctrl support
net: fec: adopt pinctrl support
ARM: ux500: switch MSP to using pinctrl for pins
ARM: ux500: alter MSP registration to return a device pointer
ARM: ux500: switch to using pinctrl for uart0
ARM: ux500: delete custom pin control system
ARM: ux500: switch over to Nomadik pinctrl driver
...
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Fix following compile error caused by commit 39febc0 (mtd: nand: gpmi:
adopt pinctrl support).
CC drivers/mtd/nand/gpmi-nand/gpmi-nand.o
drivers/mtd/nand/gpmi-nand/gpmi-nand.c: In function ‘acquire_resources’:
drivers/mtd/nand/gpmi-nand/gpmi-nand.c:499:45: error: ‘pdev’ undeclared (first use in this function)
Reported-by: Subodh Nijsure <snijsure@grid-net.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
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Cc: linux-mtd@lists.infradead.org
Cc: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
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Pull first batch of arm-soc cleanups from Olof Johansson:
"These cleanups are basically all over the place. The idea is to
collect changes with minimal impact but large number of changes so we
can avoid them from distracting in the diffstat in the other series.
A significant number of lines get removed here, in particular because
the ixp2000 and ixp23xx platforms get removed. These have never been
extremely popular and have fallen into disuse over time with no active
maintainer taking care of them. The u5500 soc never made it into a
product, so we are removing it from the ux500 platform.
Many good cleanups also went into the at91 and omap platforms, as has
been the case for a number of releases."
Trivial modify-delete conflicts in arch/arm/mach-{ixp2000,ixp23xx}
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (152 commits)
ARM: clps711x: Cleanup IRQ handling
ARM clps711x: Removed unused header mach/time.h
ARM: clps711x: Added note about support EP731x CPU to Kconfig
ARM: clps711x: Added missing register definitions
ARM: clps711x: Used own subarch directory for store header file
Dove: Fix Section mismatch warnings
ARM: orion5x: ts78xx debugging changes
ARM: orion5x: remove PM dependency from ts78xx
ARM: orion5x: ts78xx fix NAND resource off by one
ARM: orion5x: ts78xx whitespace cleanups
Orion5x: Fix Section mismatch warnings
Orion5x: Fix warning: struct pci_dev declared inside paramter list
ARM: clps711x: Combine header files into one for clps711x-targets
ARM: S3C24XX: Use common macro to define resources on mach-qt2410.c
ARM: S3C24XX: Use common macro to define resources on mach-osiris.c
ARM: EXYNOS: Adapt to cpuidle core time keeping and irq enable
ARM: S5PV210: Use common macro to define resources on mach-smdkv210.c
ARM: S5PV210: Use common macro to define resources on dev-audio.c
ARM: S5PC100: Use common macro to define resources on dev-audio.c
ARM: S5P64X0: Use common macro to define resources on dev-audio.c
...
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Using a single definition for the physical and virtual address register for all
variants boards clps711x. This patch also includes the use of a single function
clps_read/write in some units.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Pull three MTD fixes from David Woodhouse:
- Fix a lock ordering deadlock in JFFS2
- Fix an oops in the dataflash driver, triggered by a dummy call to test
whether it has OTP functionality.
- Fix request_mem_region() failure on amsdelta NAND driver.
* tag 'for-linus-3.4-20120513' of git://git.infradead.org/linux-mtd:
mtd: ams-delta: fix request_mem_region() failure
jffs2: Fix lock acquisition order bug in gc path
mtd: fix oops in dataflash driver
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A call to request_mem_region() has been introduced in the omap-gpio
driver recently (commit 96751fcbe5438e95514b025e9cee7a6d38038f40,
"gpio/omap: Use devm_ API and add request_mem_region"). This change
prevented the Amstrad Delta NAND driver, which was doing the same in
order to take control over OMAP MPU I/O lines that the NAND device hangs
off, from loading successfully.
The I/O lines and corresponding registers used by the NAND driver are a
subset of those used for the GPIO function. Then, to avoid run time
collisions, all MPUIO GPIO lines should be marked as requested while
initializing the NAND driver, and vice versa, a single MPUIO GPIO line
already requested before the NAND driver initialization is attempted
should prevent the NAND device from being started successfully.
There is another driver, omap-keypad, which also manipulates MPUIO
registers, but has never been calling request_mem_region() on startup,
so it's not affected by the change in the gpio-omap and works correctly.
It uses the depreciated omap_read/write functions for accessing MPUIO
registers. Unlike the NAND driver, these I/O lines and registers are
separate from those used by the GPIO driver. However, both register sets
are non-contiguous and overlapping, so it would be impractical to
request the two sets separately, one from the gpio-omap, the other form
the omap-keypad driver.
In order to solve all these issues correctly, a solution first suggested
by Artem Bityutskiy, then closer specified by Tony Lindgren while they
commented the initial version of this fix, should be implemented. The
gpio-omap driver should export a few functions which would allow the
other two drivers to access MPUIO registers in a safe manner instead of
trying to manage them in parallel to the GPIO driver. However, such a
big change, affecting 3 drivers all together, is not suitable for the rc
cycle, and should be prepared for the merge window. Then, an
alternative solution is proposed as a regression fix.
For the ams-delta NAND driver to initialize correctly in coexistence
with the changed GPIO driver, drop the request_mem_region() call from
the former, especially as this call is going to be removed while the
long-term solution is implemented.
Tested on Amstrad Delta.
Signed-off-by: Janusz Krzysztofik <jkrzyszt@tis.icnet.pl>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Enable channel in device_issue_pending call, so that the order between
cookie assignment and channel enabling can be ensured naturally.
It fixes the mxs gpmi-nand breakage which is caused by the incorrect
order of cookie assigning and channel enabling.
Suggested-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Tested-by: Huang Shijie <b32955@freescale.com>
Tested-by <samgandhi9@gmail.com>
Signed-off-by: Vinod Koul <vinod.koul@linux.intel.com>
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Pull MTD changes from David Woodhouse:
- Artem's cleanup of the MTD API continues apace.
- Fixes and improvements for ST FSMC and SuperH FLCTL NAND, amongst
others.
- More work on DiskOnChip G3, new driver for DiskOnChip G4.
- Clean up debug/warning printks in JFFS2 to use pr_<level>.
Fix up various trivial conflicts, largely due to changes in calling
conventions for things like dmaengine_prep_slave_sg() (new inline
wrapper to hide new parameter, clashing with rewrite of previously last
parameter that used to be an 'append' flag, and is now a bitmap of
'unsigned long flags').
(Also some header file fallout - like so many merges this merge window -
and silly conflicts with sparse fixes)
* tag 'for-linus-3.4' of git://git.infradead.org/mtd-2.6: (120 commits)
mtd: docg3 add protection against concurrency
mtd: docg3 refactor cascade floors structure
mtd: docg3 increase write/erase timeout
mtd: docg3 fix inbound calculations
mtd: nand: gpmi: fix function annotations
mtd: phram: fix section mismatch for phram_setup
mtd: unify initialization of erase_info->fail_addr
mtd: support ONFI multi lun NAND
mtd: sm_ftl: fix typo in major number.
mtd: add device-tree support to spear_smi
mtd: spear_smi: Remove default partition information from driver
mtd: Add device-tree support to fsmc_nand
mtd: fix section mismatch for doc_probe_device
mtd: nand/fsmc: Remove sparse warnings and errors
mtd: nand/fsmc: Add DMA support
mtd: nand/fsmc: Access the NAND device word by word whenever possible
mtd: nand/fsmc: Use dev_err to report error scenario
mtd: nand/fsmc: Use devm routines
mtd: nand/fsmc: Modify fsmc driver to accept nand timing parameters via platform
mtd: fsmc_nand: add pm callbacks to support hibernation
...
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A lot of functions have been marked __devinit, but they shouldn't, because they
are needed for bbt_scan. While I believe the whole MX23 handling should be done
entirely different, I am missing the resources to fix it. So, let's have at least
the annotations correct.
Signed-off-by: Wolfram Sang <w.sang@pengutronix.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Initialization of 'erase_info->fail_addr' to MTD_FAIL_ADDR_UNKNOWN prior
erase operation is duplicated accross several MTD drivers, and also taken
care of by some MTD users as well.
Harmonize it: initialize 'fail_addr' within 'mtd_erase()' interface.
Signed-off-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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With onfi a flash is organized into one or more logical units (LUNs).
A logical unit (LUN) is the minimum unit that can independently execute
commands and report status.
Mtd does not exploit LUN, so make it see a big single flash where size is
lun_size * number_of_lun.
Without this patch MT29F8G08ADBDAH4 size is 512MiB instead of 1GiB.
Artem: split long line on 2 shorter ones.
Signed-off-by: Matthieu Castet <matthieu.castet@parrot.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This patch adds support to configure the FSMC NAND driver (used amongst
others on SPEAr platforms) via device-tree instead of platform_data.
Signed-off-by: Stefan Roese <sr@denx.de>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This patch removes the sparse below warnings and errors for nand/fsmc driver
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
warning: incorrect type in initializer (different address spaces)
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
expected struct fsmc_regs *regs
/root/vipin/spear/kernel/3.3/linux-3.3/drivers/mtd/nand/fsmc_nand.c:363:31:
got void [noderef] <asn:2>*regs_va
[...]
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The fsmc_nand driver uses cpu to read/write onto the device. This is inefficient
because of two reasons
- the cpu gets locked on AHB bus while reading from NAND
- the cpu is unnecessarily used when dma can do the job
This patch adds the support for accessing the device through DMA
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The default way of accessing nand device is using the nand width. This means
that 8bit devices are using u8 * and 16bit devices are accessed using u16 *.
This results in a non-optimal performance since the FSMC is designed to
translate the normal word accesses into device width based accesses. This patch
implements read_buf and write_buf callbacks using word by word accesses.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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fsmc controller takes time to calculate the bch8 codes and the error offsets.
The calculate logic checks for completion upto a timeout. This patch adds a
error print when this timer expires and the ecc or error offsets are not yet
calculated.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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fsmc_nand driver currently uses normal kzalloc, request_mem etc routines. This
patch replaces these routines with devm_kzalloc and devm_request_mem_region etc.
Consequently, the error and driver removal scenarios are curtailed.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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FSMC controllers provide registers to program the required timing values for
attached NAND device. The timing values used until now are relaxed and should
work for all devices.
Although, for read/write performance improvements, the fsmc nand driver should
accept nand timings as a platform data and program the timing parameters into
fsmc registers accordingly.
This patch implements this modification. Additionally, it programs the default
timing parameters if these are not passed via platform data.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Ideally, the block should have 0xff written on the bad block position. Any value
other than 0xff implies a bad block. In practical situations, there can be
bit flips in the oob area as well which means that a block with 0x7f being read
at bad block position may imply a bad block but it is infact only a bit flip in
the bad block byte.
To resolve this problem, the block is marked as good if number of high bits is
greater than or equal to badblockbits (initialized to 7)
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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ECC can correct up to 8 bits in 512 bytes data + 13 bytes ecc. This means that
the algorithm can correct a max of 8 bits in 4200 bits ie the error indices can
be from 0 to 4199. Of these 0 to 4095 are for data and 4096 to 4199 for ecc.
The driver flips the bit only if the index is <= 4096. This is a bug since the
data bits are only from 0 to 4095.
This patch modifies the check as < 4096
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The ECC logic of FSMC works on 512 bytes data + 13 bytes ECC to generate error
indices of up to 8 incorrect bits. The FSMC driver reads 14 instead of 13 oob
bytes to accommodate for 16 bit device as well.
Unfortunately, the internal ecc state machine gets corrupted for 8 bit devices
reading 512 + 14 bytes of data resulting in error indices not getting reported.
Fix this by reading 14 bytes only for 16 bit devices
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This patch reimplements the passing of partition information through platform
data. This was unintentionally deleted in commit
0d04eda1430e9a796214bee644b7e05d99cfe613
"mtd: fsmc_nand.c: use mtd_device_parse_register"
Artem: fix gcc warning about passin 0 instead of NULL.
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Stefan Roese <sr@denx.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Cc: stable@kernel.org [3.2+]
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The last DMA command of ECC read page is used to disable the BCH module.
But the original code missed to set the pio[2] which is used to set the
GPMI_HW_GPMI_ECCCTRL register. fix it now.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Flash device drivers initialize 'ecc_strength' in struct mtd_info, which is the
maximum number of bit errors that can be corrected in one writesize region.
Drivers using the nand interface intitialize 'strength' in struct nand_ecc_ctrl,
which is the maximum number of bit errors that can be corrected in one ecc step.
Nand infrastructure code translates this to 'ecc_strength'.
Also for nand drivers, the nand infrastructure code sets ecc.strength for ecc
modes NAND_ECC_SOFT, NAND_ECC_SOFT_BCH, and NAND_ECC_NONE. It is set in the
driver for all other modes.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Adds power management code with fine granularity. Every flash control
command is enclosed by runtime_put()/get()s. To make sure that no
overhead is generated by too frequent power state switches, a quality of
service request is issued.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The first 3 arguments of 'mtd_device_parse_register()' are pointers,
but many callers pass '0' instead of 'NULL'. Fix this globally. Thanks
to coccinelle for making it easy to do with the following semantic patch:
@@
expression mtd, types, parser_data, parts, nr_parts;
@@
(
-mtd_device_parse_register(mtd, 0, parser_data, parts, nr_parts)
+mtd_device_parse_register(mtd, NULL, parser_data, parts, nr_parts)
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-mtd_device_parse_register(mtd, types, 0, parts, nr_parts)
+mtd_device_parse_register(mtd, types, NULL, parts, nr_parts)
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-mtd_device_parse_register(mtd, types, parser_data, 0, nr_parts)
+mtd_device_parse_register(mtd, types, parser_data, NULL, nr_parts)
)
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The current patch is required to support EVALSPEAR1340CPU
Revision 2 where a new (ONFI compliant) MT29F16G08 NAND
flash from Micron is present.
This NAND flash device defines a OOB area which is
224 bytes long (oobsize).
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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This patch improves the error correction routine for bch8
- Loop only up to number of errors detected
- Improve the error index calculation procedure
Additionally, it also renames the "correct" routine to indicate that it is bch8
specific
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Since change_bit() requires a (unsigned int *) as second arg,
the correct definition of err_idx[] array declared as
local variable of fsmc_correct_data() is the following:
u32 err_idx[8];
Signed-off-by: Armando Visconti <armando.visconti@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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ALE and CLE offsets can be different on different devices. Let devices
pass these offsets to the fsmc driver through platform data.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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ECC1 & ECC4 layout for NAND of different pages sizes for e.g. 512bytes,
2KiB, 4KiB and 8KiB are separated. Previously there existed one ECC4
layout for 2KiB & 4KiB page size due to which oob test module available
in drivers/mtd/nand/test was failing.
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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A newly erased page contains ff in data as well as spare area. While reading an
erased page, the read out ecc from spare area does not match the ecc generated
by fsmc ecc hardware accelerator. This is because ecc of data ff ff is not ff
ff. This leads to errors when file system erases and reads back the pages to
ensure consistency.
This patch adds a software workaround to ensure that the ecc check is not
performed for erased pages. This problem is solved by checking the number of
bits (in 512 byte data + 13 byte ecc) which are 0. If these number of bits are
less than 8, the page is considered erased and correction algorithm is not tried
on that page
Signed-off-by: Vipin Kumar <vipin.kumar@st.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Add a register used in new FLCTL hardware and a feature flag for it.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Instead of reading out the register, use a cached value. This will
make way for a proper runtime power management implementation.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Implements the command to seek and read in pages.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The nand base code wants to read out 8 bytes in the READID command.
Reflect this in the driver code.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Reorders the calls to make it a bit shorter and match the calling
procedure displayed in the datasheet.
Signed-off-by: Bastian Hecht <hechtb@gmail.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Some strange nand chip(such as Hynix H27UBG8T2A) can pass the `ONFI` signature
check. So the log can be printed out even it is not an ONFI nand indeed.
Change this log to the end of the function. Print out the log only when we
really detect an ONFI nand.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Florian Fainelli <ffainelli@freebox.fr>
Acked-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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[1] Background :
The GPMI does ECC read page operation with a DMA chain consist of three DMA
Command Structures. The middle one of the chain is used to enable the BCH,
and read out the NAND page.
The WAIT4END(wait for command end) is a comunication signal between
the GPMI and MXS-DMA.
[2] The current DMA code sets the WAIT4END bit at the last one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^
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set WAIT4END here
This chain works fine in the mx23/mx28.
[3] But in the new GPMI version (used in MX50/MX60), the WAIT4END bit should
be set not only at the last DMA Command Structure,
but also at the middle one, such as:
+-----+ +-----+ +-----+
| cmd | ------------> | cmd | ------------------> | cmd |
+-----+ +-----+ +-----+
^ ^
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set WAIT4END here too set WAIT4END here
If we do not set WAIT4END, the BCH maybe stalls in "ECC reading page" state.
In the next ECC write page operation, a DMA-timeout occurs.
This has been catched in the MX6Q board.
[4] In order to fix the bug, rewrite the last parameter of mxs_dma_prep_slave_sg(),
and use the dma_ctrl_flags:
---------------------------------------------------------
DMA_PREP_INTERRUPT : append a new DMA Command Structrue.
DMA_CTRL_ACK : set the WAIT4END bit for this DMA Command Structure.
---------------------------------------------------------
[5] changes to the relative drivers:
<1> For mxs-mmc driver, just use the new flags, do not change any logic.
<2> For gpmi-nand driver, and use the new flags to set the DMA
chain, especially for ecc read page.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Move the header to a more common place.
The mxs dma engine is not only used in mx23/mx28, but also used
in mx50/mx6q. It will also be used in the future chips.
Rename it to mxs-dma.h, and create a new folder include/linux/fsl/ to
store the Freescale's header files.
change mxs-dma driver, mxs-mmc driver, gpmi-nand driver, mxs-saif driver
to the new header file.
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Huang Shijie <b32955@freescale.com>
Acked-by: Vinod Koul <vinod.koul@linux.intel.com>
Acked-by: Chris Ball <cjb@laptop.org>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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The gpmi driver selects the MTD_CMDLINE_PARTS directly.
But we should not select a visible symbol.
Just remove the select.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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In many places in drivers we verify for the zero length, but this is very
inconsistent across drivers. This is obviously the right thing to do, though.
This patch moves the check to the MTD API functions instead and removes a lot
of duplication.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Reviewed-by: Shmulik Ladkani <shmulik.ladkani@gmail.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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We already verify that offset and length are within the MTD device size
in the MTD API functions. Let's remove the duplicated checks in drivers.
This patch only affects the following API's:
'mtd_erase()'
'mtd_point()'
'mtd_unpoint()'
'mtd_get_unmapped_area()'
'mtd_read()'
'mtd_write()'
'mtd_panic_write()'
'mtd_lock()'
'mtd_unlock()'
'mtd_is_locked()'
'mtd_block_isbad()'
'mtd_block_markbad()'
This patch adds a bit of noise by removing too sparse empty lines, but this is
not too bad.
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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Currently, the flash-based BBT implementation writes bad block data only
to its flash-based table and not to the OOB marker area. Then, as new bad
blocks are marked over time, the OOB markers become incomplete and the
flash-based table becomes the only source of current bad block
information. This becomes an obvious problem when, for example:
* bootloader cannot read the flash-based BBT format
* BBT is corrupted and the flash must be rescanned for bad
blocks; we want to remember bad blocks that were marked from Linux
So to keep the bad block markers in sync with the flash-based BBT, this
patch changes the default so that we write bad block markers to the proper
OOB area on each block in addition to flash-based BBT. Comments are
updated, expanded, and/or relocated as necessary.
The new flash-based BBT procedure for marking bad blocks:
(1) erase the affected block, to allow OOB marker to be written cleanly
(2) update in-memory BBT
(3) write bad block marker to OOB area of affected block
(4) update flash-based BBT
Note that we retain the first error encountered in (3) or (4), finish the
procedures, and dump the error in the end.
This should handle power cuts gracefully enough. (1) and (2) are mostly
harmless (note that (1) will not erase an already-recognized bad block).
The OOB and BBT may be "out of sync" if we experience power loss bewteen
(3) and (4), but we can reasonably expect that on next boot, subsequent
I/O operations will discover that the block should be marked bad again,
thus re-syncing the OOB and BBT.
Note that this is a change from the previous default flash-based BBT
behavior. If your system cannot support writing bad block markers to OOB,
use the new NAND_BBT_NO_OOB_BBM option (in combination with
NAND_BBT_USE_FLASH and NAND_BBT_NO_OOB).
Signed-off-by: Brian Norris <computersforpeace@gmail.com>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Signed-off-by: David Woodhouse <David.Woodhouse@intel.com>
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