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* Merge tag 'for-linus-20161008' of git://git.infradead.org/linux-mtdLinus Torvalds2016-10-1121-386/+853
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Brian Norris: "I've not been very active this cycle, so these are mostly from Boris, for the NAND flash subsystem. NAND: - Add the infrastructure to automate NAND timings configuration - Provide a generic DT property to maximize ECC strength - Some refactoring in the core bad block table handling, to help with improving some of the logic in error cases. - Minor cleanups and fixes MTD: - Add APIs for handling page pairing; this is necessary for reliably supporting MLC and TLC NAND flash, where paired-page disturbance affects reliability. Upper layers (e.g., UBI) should make use of these in the near future" * tag 'for-linus-20161008' of git://git.infradead.org/linux-mtd: (35 commits) mtd: nand: fix trivial spelling error mtdpart: Propagate _get/put_device() mtd: nand: Provide nand_cleanup() function to free NAND related resources mtd: Kill the OF_MTD Kconfig option mtd: nand: mxc: Test CONFIG_OF instead of CONFIG_OF_MTD mtd: nand: Fix nand_command_lp() for 8bits opcodes mtd: nand: sunxi: Support ECC maximization mtd: nand: Support maximizing ECC when using software BCH mtd: nand: Add an option to maximize the ECC strength mtd: nand: mxc: Add timing setup for v2 controllers mtd: nand: mxc: implement onfi get/set features mtd: nand: sunxi: switch from manual to automated timing config mtd: nand: automate NAND timings selection mtd: nand: Expose data interface for ONFI mode 0 mtd: nand: Add function to convert ONFI mode to data_interface mtd: nand: convert ONFI mode into data interface mtd: nand: Introduce nand_data_interface mtd: nand: Create a NAND reset function mtd: nand: remove unnecessary 'extern' from function declarations MAINTAINERS: Add maintainer entry for Ingenic JZ4780 NAND driver ...
| * mtd: nand: fix trivial spelling errorBrian Norris2016-10-031-1/+1
| | | | | | | | | | | | | | | | | | Introduced by commit fde85cfd2d07 ("mtd: nand: Fix nand_command_lp() for 8bits opcodes") and I didn't have the heart to have Boris rewrite his pull request just for that. Anyway, there's some value in having stable commit hashes. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * Merge tag 'for-4.9' of github.com:linux-nand/linuxBrian Norris2016-10-0321-386/+853
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | " Notable core changes: - add the infrastructure to automate NAND timings configuration - provide a generic DT property to maximize ECC strength The rest is just a bunch of minor drivers and core fixes/cleanup patches. " Also not noted: some refactoring in the core bad block table handling, to help with improving some of the logic in error cases. Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| | * mtd: nand: Provide nand_cleanup() function to free NAND related resourcesRichard Weinberger2016-09-231-7/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Provide a nand_cleanup() function to free all nand related resources without unregistering the mtd device. This should allow drivers to call mtd_device_unregister() and handle its return value and still being able to cleanup all nand related resources. Signed-off-by: Richard Weinberger <richard@nod.at> Signed-off-by: Daniel Walter <dwalter@sigma-star.at> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: mxc: Test CONFIG_OF instead of CONFIG_OF_MTDBoris Brezillon2016-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | We are about to drop the OF_MTD Kconfig option. Test CONFIG_OF activation instead of CONFIG_OF_MTD. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Fix nand_command_lp() for 8bits opcodesBoris Brezillon2016-09-231-1/+4
| | | | | | | | | | | | | | | | | | | | | 8 bits opcodes should be followed by a single address cycle. Make the 2nd address cycle dependent of !nand_opcode_8bits(command). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: sunxi: Support ECC maximizationBoris Brezillon2016-09-231-0/+29
| | | | | | | | | | | | | | | | | | Setup the maximum ECC config when NAND_ECC_MAXIMIZE is set. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Support maximizing ECC when using software BCHBoris Brezillon2016-09-231-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Add support for ECC maximization when software BCH with nand_ooblayout_lp_ops layout is used. Other cases should be handled by the NAND controller driver. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Add an option to maximize the ECC strengthBoris Brezillon2016-09-231-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The generic NAND DT bindings allows one to tweak the ECC strength and step size to their need. It can be used to lower the ECC strength to match a bootloader/firmware config, but might also be used to get a better reliability. In the latter case, the user might want to use the maximum ECC strength without having to explicitly calculate the exact value (this value not only depends on the OOB size, but also on the NAND controller, and can be tricky to extract). Add a generic 'nand-ecc-maximize' DT property and the associated NAND_ECC_MAXIMIZE flag, to let ECC controller drivers select the best ECC strength and step-size on their own. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Acked-by: Rob Herring <robh@kernel.org>
| | * mtd: nand: mxc: Add timing setup for v2 controllersSascha Hauer2016-09-231-2/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far we relied on reset default or the bootloader to configure a suitable clk rate for the Nand controller. This works but we can optimize the timing for better performance. This sets the clk rate for v2 controllers (i.MX25/35) based on the timing mode read from the ONFI parameter page. This may also enable the symmetric mode (aks EDO mode) if necessary which reads one word per clock cycle. Tested on an i.MX25 with a Micron MT29F4G08ABBDAHC attached. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: mxc: implement onfi get/set featuresSascha Hauer2016-09-231-0/+55
| | | | | | | | | | | | | | | | | | | | | | | | To be able to support different ONFI timing modes we have to implement the onfi_set_features and onfi_get_features. Tested on an i.MX25 SoC. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: sunxi: switch from manual to automated timing configSascha Hauer2016-09-231-62/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND framework is now able to select the best NAND timings for us. All we have to do is implement a ->setup_data_interface() function to apply those timings and remove the timing selection code from the sunxi driver. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: automate NAND timings selectionBoris Brezillon2016-09-231-0/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND framework provides several helpers to query timing modes supported by a NAND chip, but this implies that all NAND controller drivers have to implement the same timings selection dance. Also currently NAND devices can be resetted at arbitrary places which also resets the timing for ONFI chips to timing mode 0. Provide a common logic to select the best timings based on ONFI or ->onfi_timing_mode_default information. Hook this into nand_reset() to make sure the new timing is applied each time during a reset. NAND controller willing to support timings adjustment should just implement the ->setup_data_interface() method. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
| | * mtd: nand: Expose data interface for ONFI mode 0Sascha Hauer2016-09-231-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | The nand layer will need ONFI mode 0 to use it as timing mode before and right after reset. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Add function to convert ONFI mode to data_interfaceSascha Hauer2016-09-231-0/+29
| | | | | | | | | | | | | | | | | | | | | | | | onfi_init_data_interface() initializes a data interface with values from a given ONFI mode. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: convert ONFI mode into data interfaceSascha Hauer2016-09-231-206/+224
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | struct nand_data_interface is the designated type to pass to the NAND drivers to configure the timing. To simplify further patches convert the onfi_sdr_timings array from type struct nand_sdr_timings nand_data_interface. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Create a NAND reset functionSascha Hauer2016-09-231-5/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When NAND devices are resetted some initialization may have to be done, like for example they have to be configured for the timing mode that shall be used. To get a common place where this initialization can be implemented create a nand_reset() function. This currently only issues a NAND_CMD_RESET to the NAND device. The places issuing this command manually are replaced with a call to nand_reset(). Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Allow MTD_NAND_OMAP2 to be usable on Keystone devicesRoger Quadros2016-09-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some Keystone devices (e.g. K2G) include a OMAP NAND IP. Allow the NAND driver to be usable for both Keystone and OMAP devices. Signed-off-by: Roger Quadros <rogerq@ti.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: brcmnand: iProc big endian and ONFI supportRay Jui2016-09-233-15/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds big endian and ONFI support for various iProc based SoCs that use the core brcmstb NAND controller This patch was originally implemented by Prafulla Kota <prafulla.kota@broadcom.com> and fully tested on iProc based NS2 SVK Signed-off-by: Prafulla Kota <prafulla.kota@broadcom.com> Signed-off-by: Ray Jui <ray.jui@broadcom.com> Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com> Acked-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand_bbt: scan for next free bbt block if writing bbt failsKyle Roeschley2016-09-231-6/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If erasing or writing the BBT fails, we should mark the current BBT block as bad and use the BBT descriptor to scan for the next available unused block in the BBT. We should only return a failure if there isn't any space left. Signed-off-by: Kyle Roeschley <kyle.roeschley@ni.com> Suggested-by: Jeff Westfahl <jeff.westfahl@ni.com> Tested-by: Kyle Roeschley <kyle.roeschley@ni.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand_bbt: Move BBT block selection logic out of write_bbt()Boris Brezillon2016-09-231-36/+74
| | | | | | | | | | | | | | | | | | | | | | | | This clarifies the write_bbt() function by removing the write label and simplifying the error/exit path. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com> Tested-by: Kyle Roeschley <kyle.roeschley@ni.com>
| | * mtd: nand: timings: Reorder tRR_min def in mode 0Boris Brezillon2016-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | In the ONFI spec, the tRR_min entry is defined before the tRST_max one. Reoder the definition to make it easier to review. Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: timings: Fix tADL_min for ONFI 4.0 chipsBoris Brezillon2016-09-231-6/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | ONFI 4.0 spec defines different values for the tADL_min timing. Since we don't want to have different timings depending on the ONFI version, we just set tADL_min to the maximum value (the one specified in the ONFI 4.0 spec). Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: gpmi: get correct free oob spaceHan Xu2016-09-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | change the way to calculate pagesize to get correct free oob space for legacy_set_geometry function. Signed-off-by: Han Xu <han.xu@nxp.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: sh_flctl: handle dma_submit() errorsBrian Norris2016-09-231-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some build tools noticed that 'cookie' is being set but not used. Might as well catch the errors here and handle them the same way we handle other DMA prep steps. Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: s3c2410: Register cpufreq notifier only on S3C24xxKrzysztof Kozlowski2016-09-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver registered for CPU frequency transitions to recalculate its clock when ARM clock frequency changes (ratio between frequencies of ARM's parent clock (fclk) and clock for peripherals remains fixed). This is needed only on S3C24xx platform when cpufreq driver is enabled so limit the ifdef to respective cpufreq Kconfig. Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Get rid of needless 'goto'Andrey Smirnov2016-09-231-12/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Using "goto" and "switch" statement only makes it harder to follow control flow and doesn't bring any advantages. Rewrite the code to avoid using "goto". Signed-off-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: Error out if cmd_ctrl() is missingAndrey Smirnov2016-09-231-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no user specified chip->select_chip() function is provided, code in nand_base.c will automatically set this hook to nand_select_chip(), which in turn depends on chip->cmd_ctrl() hook being valid. Not providing both of those functions in NAND controller driver (for example by mistake) will result in a bit cryptic segfault. Same is true for chip->cmdfunc(). To avoid the above scenario add a check in nand_scan_dent and error out if cmd_ctrl() is not provided. Suggested-by: Boris Brezillon <boris.brezillon@free-electrons.com> Suggested-by: Brian Norris <computersforpeace@gmail.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * Kconfig: nand: Remove redundant dependency on MTD_NANDAndrey Smirnov2016-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Config MTD_NAND_FSL_IFC is already located inside 'if MTD_NAND' statment, so there's no need to explicitly specify it as a dependency. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * Kconfig: nand: Make MTD_NAND_FSL_ELBC depend on FSL_SOCAndrey Smirnov2016-09-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MTD_NAND_FSL_ELBC selects FSL_LBC that in turn depends on FSL_SOC, so depending on PPC instead of FSL_SOC leads to this message: warning: (MPC836x_RDK && MTD_NAND_FSL_ELBC && MTD_NAND_FSL_UPM) selects FSL_LBC which has unmet direct dependencies (FSL_SOC) when doing make ARCH=powerpc \ CROSS_COMPILE=powerpc-e500v2-linux-gnuspe- \ allmodconfig" Changing dependency to FSL_SOC fixes that. Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: import nand_hw_control_init()Marc Gonzalez2016-09-2313-26/+13
| | | | | | | | | | | | | | | | | | | | | | | | The code to initialize a struct nand_hw_control is duplicated across several drivers. Factorize it using an inline function. Signed-off-by: Marc Gonzalez <marc_gonzalez@sigmadesigns.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* | | Merge tag 'for-linus-20160928' of git://git.infradead.org/linux-mtdLinus Torvalds2016-09-282-1/+4
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull late MTD fixes from Brian Norris: "Another round of MTD fixes for v4.8 My apologies for sending this so late. I've been fairly absent as a maintainer this cycle, but I did queue these up weeks ago. In the meantime, Richard was able to handle some other fixes (thanks!) but didn't pick these up. On the bright side, these are very simple changes that should carry little risk. Summary: - Davinci NAND: fix a long-standing bug in how we clear/prep 4-bit ECC - OMAP NAND: an error-handling fix that made it into v4.8-rc1 caused error-handling cases in other configurations/code-paths; this fixes the fix" * tag 'for-linus-20160928' of git://git.infradead.org/linux-mtd: mtd: nand: davinci: Reinitialize the HW ECC engine in 4bit hwctl mtd: nand: omap2: Don't call dma_release_channel() if dma_request_chan() failed
| * | mtd: nand: davinci: Reinitialize the HW ECC engine in 4bit hwctlKarl Beldan2016-09-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This fixes subpage writes when using 4-bit HW ECC. There has been numerous reports about ECC errors with devices using this driver for a while. Also the 4-bit ECC has been reported as broken with subpages in [1] and with 16 bits NANDs in the driver and in mach* board files both in mainline and in the vendor BSPs. What I saw with 4-bit ECC on a 16bits NAND (on an LCDK) which got me to try reinitializing the ECC engine: - R/W on whole pages properly generates/checks RS code - try writing the 1st subpage only of a blank page, the subpage is well written and the RS code properly generated, re-reading the same page the HW detects some ECC error, reading the same page again no ECC error is detected Note that the ECC engine is already reinitialized in the 1-bit case. Tested on my LCDK with UBI+UBIFS using subpages. This could potentially get rid of the issue workarounded in [1]. [1] 28c015a9daab ("mtd: davinci-nand: disable subpage write for keystone-nand") Fixes: 6a4123e581b3 ("mtd: nand: davinci_nand, 4-bit ECC for smallpage") Cc: <stable@vger.kernel.org> Signed-off-by: Karl Beldan <kbeldan@baylibre.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * | mtd: nand: omap2: Don't call dma_release_channel() if dma_request_chan() failedRoger Quadros2016-08-291-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | dma_request_chan() can fail returning an error pointer. In this case prevent calling dma_release_channel() to prevent a ERR_PTR() dereference. As error path can be called even with no DMA configuration, info->dma can be NULL so don't call dma_release_channel() for that case either. Fixes: de3bfc4a1616: ("mtd: nand: omap2: fix return value check in omap_nand_probe()") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Roger Quadros <rogerq@ti.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
* | mtd: nand: mxc: fix obiwan error in mxc_nand_v[12]_ooblayout_free() functionsLothar Waßmann2016-09-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit a894cf6c5a82 ("mtd: nand: mxc: switch to mtd_ooblayout_ops") introduced a regression accessing the OOB area from the mxc_nand driver due to an Obiwan error in the mxc_nand_v[12]_ooblayout_free() functions. They report a bogus oobregion { 64, 7 } which leads to errors accessing bogus data when reading the oob area. Prior to the commit the mtd-oobtest module could be run without any errors. With the offending commit, this test fails with results like: |Running mtd-oobtest | |================================================= |mtd_oobtest: MTD device: 5 |mtd_oobtest: MTD device size 524288, eraseblock size 131072, page size 2048, count of eraseblocks 4, pages per eraseblock 64, OOB size 64 |mtd_test: scanning for bad eraseblocks |mtd_test: scanned 4 eraseblocks, 0 are bad |mtd_oobtest: test 1 of 5 |mtd_oobtest: writing OOBs of whole device |mtd_oobtest: written up to eraseblock 0 |mtd_oobtest: written 4 eraseblocks |mtd_oobtest: verifying all eraseblocks |mtd_oobtest: error @addr[0x0:0x19] 0x9a -> 0x78 diff 0xe2 |mtd_oobtest: error @addr[0x0:0x1a] 0xcc -> 0x0 diff 0xcc |mtd_oobtest: error @addr[0x0:0x1b] 0xe0 -> 0x85 diff 0x65 |mtd_oobtest: error @addr[0x0:0x1c] 0x60 -> 0x62 diff 0x2 |mtd_oobtest: error @addr[0x0:0x1d] 0x69 -> 0x45 diff 0x2c |mtd_oobtest: error @addr[0x0:0x1e] 0xcd -> 0xa0 diff 0x6d |mtd_oobtest: error @addr[0x0:0x1f] 0xf2 -> 0x60 diff 0x92 |mtd_oobtest: error: verify failed at 0x0 [...] Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de> Fixes: a894cf6c5a82 ("mtd: nand: mxc: switch to mtd_ooblayout_ops") Cc: <stable@vger.kernel.org> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* | mtd: nand: fix chances to create incomplete ECC data when writingRogerCC Lin2016-09-191-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | When mtk_nfc_do_write_page() comparing the sector number,because the sector number field is at the 12th-bit position of NFI_BYTELEN register,the masked register should be shifted 12 bits before being compared.The result of this bug may cause the second subpage has incomplete ECC parity bytes. Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com> Fixes: 1d6b1e464950 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* | mtd: nand: fix generating over-boundary ECC data when writingRogerCC Lin2016-09-191-4/+8
|/ | | | | | | | | | When mtk_ecc_encode() is writing the ECC parity data to the OOB region,because each register is 4 bytes in length,but the len's unit is in bytes,the operation in the for loop will cross the ECC's boundary. Signed-off-by: RogerCC Lin <rogercc.lin@mediatek.com> Fixes: 1d6b1e464950 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
* Merge tag 'for-linus-20160801' of git://git.infradead.org/linux-mtdLinus Torvalds2016-08-0213-126/+2810
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull MTD updates from Brian Norris: "NAND: Quoting Boris: 'This pull request contains only one notable change: - Addition of the MTK NAND controller driver And a bunch of specific NAND driver improvements/fixes. Here are the changes that are worth mentioning: - A few fixes/improvements for the xway NAND controller driver - A few fixes for the sunxi NAND controller driver - Support for DMA in the sunxi NAND driver - Support for the sunxi NAND controller IP embedded in A23/A33 SoCs - Addition for bitflips detection in erased pages to the brcmnand driver - Support for new brcmnand IPs - Update of the OMAP-GPMC binding to support DMA channel description' In addition, some small fixes around error handling, etc., as well as one long-standing corner case issue (2.6.20, I think?) with writing 1 byte less than a page. NOR: - rework some error handling on reads and writes, so we can better handle (for instance) SPI controllers which have limitations on their maximum transfer size - add new Cadence Quad SPI flash controller driver - add new Atmel QSPI flash controller driver - add new Hisilicon SPI flash controller driver - support a few new flash, and update supported features on others - fix the logic used for detecting a fully-unlocked flash And other miscellaneous small fixes" * tag 'for-linus-20160801' of git://git.infradead.org/linux-mtd: (60 commits) mtd: spi-nor: don't build Cadence QuadSPI on non-ARM mtd: mtk-nor: remove duplicated include from mtk-quadspi.c mtd: nand: fix bug writing 1 byte less than page size mtd: update description of MTD_BCM47XXSFLASH symbol mtd: spi-nor: Add driver for Cadence Quad SPI Flash Controller mtd: spi-nor: Bindings for Cadence Quad SPI Flash Controller driver mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmd mtd: pmcmsp-flash: Allocating too much in init_msp_flash() mtd: maps: sa1100-flash: potential NULL dereference mtd: atmel-quadspi: add driver for Atmel QSPI controller mtd: nand: omap2: fix return value check in omap_nand_probe() Documentation: atmel-quadspi: add binding file for Atmel QSPI driver mtd: spi-nor: add hisilicon spi-nor flash controller driver mtd: spi-nor: support dual, quad, and WP for Gigadevice mtd: spi-nor: Added support for n25q00a. memory: Update dependency of IFC for Layerscape mtd: nand: jz4780: Update MODULE_AUTHOR email address mtd: nand: sunxi: prevent a small memory leak mtd: nand: sunxi: add reset line support mtd: nand: sunxi: update DT bindings ...
| * mtd: nand: fix bug writing 1 byte less than page sizeHector Palacios2016-07-191-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_do_write_ops() determines if it is writing a partial page with the formula: part_pagewr = (column || writelen < (mtd->writesize - 1)) When 'writelen' is exactly 1 byte less than the NAND page size the formula equates to zero, so the code doesn't process it as a partial write, although it should. As a consequence the function remains in the while(1) loop with 'writelen' becoming 0xffffffff and iterating endlessly. The bug may not be easy to reproduce in Linux since user space tools usually force the padding or round-up the write size to a page-size multiple. This was discovered in U-Boot where the issue can be reproduced by writing any size that is 1 byte less than a page-size multiple. For example, on a NAND with 2K page (0x800): => nand erase.part <partition> => nand write $loadaddr <partition> 7ff [Editor's note: the bug was added in commit 29072b96078f, but moved around in commit 66507c7bc8895 ("mtd: nand: Add support to use nand_base poi databuf as bounce buffer")] Fixes: 29072b96078f ("[MTD] NAND: add subpage write support") Signed-off-by: Hector Palacios <hector.palacios@digi.com> Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com> Cc: <stable@vger.kernel.org> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: nand: brcmnand: Change BUG_ON in brcmnand_send_cmdFlorian Fainelli2016-07-171-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change the BUG_ON() condition in brcmnand_send_cmd() which checks for the interrupt status "controller ready" bit to a WARN_ON. There is no good reason to kill the system when this condition occur because we could have systems which listed the NAND controller as available (e.g: from Device Tree), but the NAND chip could be malfunctioning and not responding. Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Acked-by: Brian Norris <computersforpeace@gmail.com> Reviewed-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * mtd: nand: omap2: fix return value check in omap_nand_probe()Wei Yongjun2016-07-161-2/+2
| | | | | | | | | | | | | | | | | | | | | | In case of error, the function dma_request_chan() returns ERR_PTR() and never returns NULL. The NULL test in the return value check should be replaced with IS_ERR(). Fixes: aa7abd312c11 ('mtd: nand: omap2: Support parsing dma channel information from DT') Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Brian Norris <computersforpeace@gmail.com>
| * Merge tag 'nand/for-4.8' of github.com:linux-nand/linux into mtdBrian Norris2016-07-1612-121/+2805
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NAND changes from Boris Brezillon: """ This pull request contains only one notable change: * Addition of the MTK NAND controller driver And a bunch of specific NAND driver improvements/fixes. Here are the changes that are worth mentioning: * A few fixes/improvements for the xway NAND controller driver * A few fixes for the sunxi NAND controller driver * Support for DMA in the sunxi NAND driver * Support for the sunxi NAND controller IP embedded in A23/A33 SoCs * Addition for bitflips detection in erased pages to the brcmnand driver * Support for new brcmnand IPs * Update of the OMAP-GPMC binding to support DMA channel description """
| | * mtd: nand: jz4780: Update MODULE_AUTHOR email addressHarvey Hunt2016-07-112-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Emails will bounce from my imgtec address, so update it to a new one. Signed-off-by: Harvey Hunt <harvey.hunt@imgtec.com> Cc: Harvey Hunt <harveyhuntnexus@gmail.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: sunxi: prevent a small memory leakDan Carpenter2016-07-111-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | I moved the sanity check on ecc->size before the allocation so that we don't leak memory on error. Fixes: 05af074a4b73 ('mtd: nand: sunxi: check ecc->size values') Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: sunxi: add reset line supportIcenowy Zheng2016-07-111-2/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND controller on some sun8i chips needs its reset line to be deasserted before they can enter working state. Signed-off-by: Icenowy Zheng <icenowy@aosc.xyz> Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: xway: add nandaddr to own structHauke Mehrtens2016-07-111-16/+14
| | | | | | | | | | | | | | | | | | | | | | | | Instead of using IO_ADDR_W and IO_ADDR_R use an own pointer to the NAND controller memory area. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: xway: add missing write_buf and read_buf to nand driverHauke Mehrtens2016-07-111-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | This driver needs a special write_buf and read_buf function, because we have to read from a specific address to tell the controller this is a read from the nand controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: xway: extract read and write functionHauke Mehrtens2016-07-111-9/+19
| | | | | | | | | | | | | | | | | | | | | | | | Extract the functions to read and write to the register of the NAND flash controller. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: xway: fix nand lockingJohn Crispin2016-07-111-12/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The external Bus Unit (EBU) can control different flash devices, but these NAND flash commands have to be atomic and should not be interrupted in between. Lock the EBU from the beginning of the command till the end by moving the lock to the chip select. Signed-off-by: John Crispin <john@phrozen.org> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
| | * mtd: nand: xway: remove manual resetHauke Mehrtens2016-07-111-20/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nand_scan() already resets the NAND flash chip, this driver does not have to call it manually. The xway_reset_chip() functions does the same as the normal NAND reset function. The waiting for the NAND_WAIT_WR_C is done in xway_cmd_ctrl(). Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
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