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* Merge tag 'nand/for-5.5' into mtd/nextMiquel Raynal2019-11-178-60/+3072
|\ | | | | | | | | | | | | | | | | | | | | | | | | Raw NAND core * Useless extra checks dropped. * Updated the detection of the bad block markers position Raw NAND controller drivers: * Cadence : New driver * Brcmnand: Support for flash-dma v0 + fixes * Denali : Support for the legacy controller/chip DT representation dropped * Superfluous dev_err() calls removed
| * mtd: rawnand: remove unecessary checking if dmac is NULLPiotr Sroka2019-10-301-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove unecessary checking if dmac is NULL. If Cadence nand controller driver uses DMA engine then cdns_ctrl->dmac cannot be NULL. It is verified during driver initialization. If Cadence nand controller driver does not use DMA engine then CPU IO read/write are executed instead of slave DMA transfer. In that case cdns_ctrl->dmac is not used at all. Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Piotr Sroka <piotrs@cadence.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: cadence: Remove dev_err() on platform_get_irq() failureYueHaibing2019-10-291-3/+2
| | | | | | | | | | | | | | | | | | platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: mxic: Remove dev_err() on platform_get_irq() failureYueHaibing2019-10-291-3/+1
| | | | | | | | | | | | | | | | | | platform_get_irq() will call dev_err() itself on failure, so there is no need for the driver to also do this. This is detected by coccinelle. Signed-off-by: YueHaibing <yuehaibing@huawei.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: brcmnand: Fix NULL pointer assignmentFlorian Fainelli2019-10-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Sparse complained about the following: drivers/mtd/nand/raw/brcmnand/brcmnand.c:921:40: warning: Using plain integer as NULL pointer fix this issue by assigning the pointer to NULL. Fixes: c1ac2dc34b51 ("mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling") Signed-off-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: denali: remove the old unified controller/chip DT supportMasahiro Yamada2019-10-291-51/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Commit d8e8fd0ebf8b ("mtd: rawnand: denali: decouple controller and NAND chips") supported the new binding for the separate controller/chip representation, keeping the backward compatibility. All the device trees in upstream migrated to the new binding. Remove the support for the old binding. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Add new Cadence NAND driver to MTD subsystemPiotr Sroka2019-10-043-0/+3039
| | | | | | | | | | | | | | | | | | Add new Cadence NAND driver to MTD subsystem Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reported-by: kbuild test robot <lkp@intel.com> Reported-by: Julia Lawall <julia.lawall@lip6.fr> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: rawnand: Change calculating of position page containing BBMPiotr Sroka2019-10-042-3/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Change calculating of position page containing BBM If none of BBM flags are set then function nand_bbm_get_next_page reports EINVAL. It causes that BBM is not read at all during scanning factory bad blocks. The result is that the BBT table is build without checking factory BBM at all. For Micron flash memories none of these flags are set if page size is different than 2048 bytes. Address this regression by: - adding NAND_BBM_FIRSTPAGE chip flag without any condition. It solves issue only for Micron devices. - changing the nand_bbm_get_next_page_function. It will return 0 if no of BBM flag is set and page parameter is 0. After that modification way of discovering factory bad blocks will work similar as in kernel version 5.1. Cc: stable@vger.kernel.org Fixes: f90da7818b14 (mtd: rawnand: Support bad block markers in first, second or last page) Signed-off-by: Piotr Sroka <piotrs@cadence.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| * mtd: nand: brcmnand: Add support for flash-dma v0Kamal Dasu2019-10-041-2/+19
| | | | | | | | | | | | | | This change adds support for flash dma v0.0. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
* | Merge tag 'spi-nor/for-5.5' into mtd/nextMiquel Raynal2019-11-179-715/+993
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SPI NOR core changes: - introduce 'struct spi_nor_controller_ops', - clean the Register Operations methods, - use dev_dbg insted of dev_err for low level info, - fix retlen handling in sst_write(), - fix silent truncations in spi_nor_read and spi_nor_read_raw(), - fix the clearing of QE bit on lock()/unlock(), - rework the disabling of the block write protection, - rework the Quad Enable methods, - make sure nor->spimem and nor->controller_ops are mutually exclusive, - set default Quad Enable method for ISSI flashes, - add support for few flashes. SPI NOR controller drivers changes: - intel-spi: - support chips without software sequencer, - add support for Intel Cannon Lake and Intel Comet Lake-H flashes.
| * | mtd: spi-nor: Set default Quad Enable method for ISSI flashesSagar Shrikant Kadam2019-11-111-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the default Quad Enable method for ISSI flashes. Used for ISSI flashes (IS25WP256D-JMLE) that do not support SFDP tables and can not determine the Quad Enable method by parsing BFPT. Based on code originally written by Wesley Terpstra <wesley@sifive.com> and/or Palmer Dabbelt <palmer@sifive.com> https://github.com/riscv/riscv-linux/commit/c94e267766d62bc9a669611c3d0c8ed5ea26569b Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> [tudor.ambarus@microchip.com: - rebase, split and adapt for latest spi-nor/next, - use PMC CFI ID for ISSI. According to JEP106BA, "Programmable Micro Corp" changed its name to Integrated Silicon Solution (ISSI)] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Add support for is25wp256Sagar Shrikant Kadam2019-11-111-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the spi_nor_id table for is25wp256 (32MB) device from ISSI, present on HiFive Unleashed dev board (Rev: A00). Use the post bfpt fixup hook for the is25wp256 device, as done for the is25lp256 device to overwrite the wrong address width advertised by BFPT. Signed-off-by: Sagar Shrikant Kadam <sagar.kadam@sifive.com> [tudor.ambarus@microchip.com: rebase, split and adapt for latest spi-nor/next] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Add support for w25q256jwManivannan Sadhasivam2019-11-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add MTD support for w25q256jw SPI NOR chip from Winbond. This chip supports dual/quad I/O mode with 512 blocks of memory organized in 64KB sectors. In addition to this, there is also small 4KB sectors available for flexibility. The device has been validated using Thor96 board. Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: David Woodhouse <dwmw2@infradead.org> Cc: Brian Norris <computersforpeace@gmail.com> Cc: Miquel Raynal <miquel.raynal@bootlin.com> Cc: Richard Weinberger <richard@nod.at> Cc: Vignesh Raghavendra <vigneshr@ti.com> Cc: linux-mtd@lists.infradead.org Signed-off-by: Darshak Patel <darshak.patel@einfochips.com> [Mani: cleaned up for upstream] Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | mtd: spi-nor: Move condition to avoid a NULL checkTudor Ambarus2019-11-111-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the controller is not under the SPI-MEM interface it may implement the optional controller_ops->erase() method. nor->spimem and nor->controller_ops are mutually exclusive. Move the nor->controller_ops->erase != NULL check as an 'else if' case to nor->spimem, in order to avoid the nor->controller_ops != NULL check. Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Make sure nor->spimem and nor->controller_ops are mutually ↵Tudor Ambarus2019-11-111-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | exclusive Expand the spi_nor_check() to make sure that nor->spimem and nor->controller_ops are mutually exclusive. Fixes: b35b9a10362d ("mtd: spi-nor: Move m25p80 code in spi-nor.c") Reported-by: Dan Carpenter <dan.carpenter@oracle.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Rename Quad Enable methodsTudor Ambarus2019-11-111-13/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rename macronix_quad_enable() to a generic name: spi_nor_sr1_bit6_quad_enable(). Prepend "spi_nor_" to "sr2_bit7_quad_enable". All SPI NOR generic methods should be prepended by "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Merge spansion Quad Enable methodsTudor Ambarus2019-11-111-95/+66
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge spansion_no_read_cr_quad_enable() spansion_read_cr_quad_enable() into spi_nor_sr2_bit1_quad_enable(). Reduce code duplication by introducing spi_nor_write_16bit_cr_and_check(). The Configuration Register contains bits that can be updated in future: FREEZE, CMP. Provide a generic method that allows updating all bits of the Configuration Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Rename CR_QUAD_EN_SPAN to SR2_QUAD_EN_BIT1Tudor Ambarus2019-11-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | JEDEC Basic Flash Parameter Table, 15th DWORD, bits 22:20, refers to this bit as "bit 1 of the status register 2". Rename the macro accordingly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Extend the SR Read Back testTudor Ambarus2019-11-111-19/+39
| | | | | | | | | | | | | | | | | | | | | | | | Test that all the bits from Status Register 1 and Status Register 2 were written correctly. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Rework the disabling of block write protectionTudor Ambarus2019-11-111-90/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_unlock() unlocks blocks of memory or the entire flash memory array, if requested. clear_sr_bp() unlocks the entire flash memory array at boot time. This calls for some unification, clear_sr_bp() is just an optimization for the case when the unlock request covers the entire flash size. Get rid of clear_sr_bp() and introduce spi_nor_unlock_all(), which is just a call to spi_nor_unlock() for the entire flash memory array. This fixes a bug that was present in spi_nor_spansion_clear_sr_bp(). When the QE bit was zero, we used the Write Status (01h) command with one data byte, which might cleared the Status Register 2. We now always use the Write Status (01h) command with two data bytes when SNOR_F_HAS_16BIT_SR is set, to avoid clearing the Status Register 2. The SNOR_F_NO_READ_CR case is treated as well. When the flash doesn't support the CR Read command, we make an assumption about the value of the QE bit. In spi_nor_init(), call spi_nor_quad_enable() first, then spi_nor_unlock_all(), so that at the spi_nor_unlock_all() time we can be sure the QE bit has value one, because of the previous call to spi_nor_quad_enable(). Get rid of the MFR handling and implement specific manufacturer default_init() fixup hooks. Note that this changes a bit the logic for the SNOR_MFR_ATMEL, SNOR_MFR_INTEL and SNOR_MFR_SST cases. Before this patch, the Atmel, Intel and SST chips did not set the locking ops, but unlocked the entire flash at boot time, while now they are setting the locking ops to stm_locking_ops. This should work, since the disable of the block protection at the boot time used the same Status Register bits to unlock the flash, as in the stm_locking_ops case. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Fix clearing of QE bit on lock()/unlock()Tudor Ambarus2019-11-111-5/+115
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make sure that when doing a lock() or an unlock() operation we don't clear the QE bit from Status Register 2. JESD216 revB or later offers information about the *default* Status Register commands to use (see BFPT DWORDS[15], bits 22:20). In this standard, Status Register 1 refers to the first data byte transferred on a Read Status (05h) or Write Status (01h) command. Status register 2 refers to the byte read using instruction 35h. Status register 2 is the second byte transferred in a Write Status (01h) command. Industry naming and definitions of these Status Registers may differ. The definitions are described in JESD216B, BFPT DWORDS[15], bits 22:20. There are cases in which writing only one byte to the Status Register 1 has the side-effect of clearing Status Register 2 and implicitly the Quad Enable bit. This side-effect is hit just by the BFPT_DWORD15_QER_SR2_BIT1_BUGGY and BFPT_DWORD15_QER_SR2_BIT1 cases. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Print debug message when the read back test failsTudor Ambarus2019-11-071-1/+6
| | | | | | | | | | | | | | | | | | | | | Demystify where the EIO error occurs. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Check all the bits written, not just the BP onesTudor Ambarus2019-11-071-5/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Check that all the bits written in the write_sr_and_check() method match the status_new received value. Failing to write the other bits is dangerous too, extend the check. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Fix errno on Quad Enable methodsTudor Ambarus2019-11-071-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | When the Read-Modify-Write-Read-Back Quad Enable methods failed on the Read-Back, they returned -EINVAL. Since this is an I/O error, return -EIO. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Drop spansion_quad_enable()Tudor Ambarus2019-11-071-53/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Drop the default spansion_quad_enable() method and replace it with spansion_read_cr_quad_enable(). The function was buggy, it didn't care about the previous values of the Status and Configuration Registers. spansion_read_cr_quad_enable() is a Read-Modify-Write-Check function that keeps track of what were the previous values of the Status and Configuration Registers. In terms of instruction types sent to the flash, the only difference between the spansion_quad_enable() and spansion_read_cr_quad_enable() is that the later calls spi_nor_read_sr(). We can safely assume that all flashes support spi_nor_read_sr(), because all flashes call it in spi_nor_sr_ready(). The transition from spansion_quad_enable() to spansion_read_cr_quad_enable() will not affect anybody, drop the buggy code. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Describe all the Reg OpsTudor Ambarus2019-11-071-11/+127
| | | | | | | | | | | | | | | | | | | | | Document all the Register Operations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Merge spi_nor_write_sr() and spi_nor_write_sr_cr()Tudor Ambarus2019-11-071-51/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge static int spi_nor_write_sr(struct spi_nor *nor, u8 val) static int spi_nor_write_sr_cr(struct spi_nor *nor, const u8 *sr_cr) into static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len) The Status Register can be written with one or two bytes. Merge the two functions to avoid code duplication. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Move the WE and wait calls inside Write SR methodsTudor Ambarus2019-11-071-64/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid duplicating code by moving the calls to spi_nor_write_enable() and spi_nor_wait_till_ready() inside the Write Status Register methods. Move spi_nor_write_sr() to avoid forward declaration of spi_nor_wait_till_ready(). Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Void return type for spi_nor_clear_sr/fsr()Tudor Ambarus2019-11-071-6/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_clear_sr() and spi_nor_clear_fsr() are called just in case of errors. The callers didn't check their return value, make them of type void. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Rename label as it is no longer genericTudor Ambarus2019-11-071-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Rename 'sst_write_err' label to 'out' as it is no longer generic for all the errors in the sst_write() method, and may introduce confusion. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Check for errors after each Register OperationTudor Ambarus2019-11-071-21/+60
| | | | | | | | | | | | | | | | | | | | | Check for the return vales of each Register Operation. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Print debug info inside Reg Ops methodsTudor Ambarus2019-11-071-42/+127
| | | | | | | | | | | | | | | | | | | | | Spare the callers of printing debug messages by themselves. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: Use dev_dbg insted of dev_err for low level infoTudor Ambarus2019-11-071-21/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | What most users care about is "my dev is not working properly". All low level information should be discovered when activating the debug traces. Keep error messages just for the following cases: - when the SR/FSR report program or erase fails, or attempts of modifying a protected sector, - when the JEDEC ID is not recognized, - when the resume() call fails, - when the spi_nor_check() fails. Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com>
| * | mtd: spi-nor: fix silent truncation in spi_nor_read_raw()Sergei Shtylyov2019-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_read_raw() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: f384b352cbf0 ("mtd: spi-nor: parse Serial Flash Discoverable Parameters (SFDP) tables") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | mtd: spi-nor: fix silent truncation in spi_nor_read()Sergei Shtylyov2019-11-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_nor_read() assigns the result of 'ssize_t spi_nor_read_data()' to the 'int ret' variable, while 'ssize_t' is a 64-bit type and *int* is a 32-bit type on the 64-bit machines. This silent truncation isn't really valid, so fix up the variable's type. Fixes: 59451e1233bd ("mtd: spi-nor: change return value of read/write") Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | mtd: spi-nor: intel-spi: Add support for Intel Comet Lake-H SPI serial flashMika Westerberg2019-11-021-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Intel Comet Lake-H PCH has the same SPI serial flash controller as Comet Lake-LP. Add Comet Lake-H PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | mtd: spi-nor: Print device info in case of errorTudor Ambarus2019-11-021-2/+2
| | | | | | | | | | | | | | | | | | | | | Print identifying information about struct device. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Constify data to write to the Status RegisterTudor Ambarus2019-11-011-2/+2
| | | | | | | | | | | | | | | | | | | | | Constify the data to write to the Status Register. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Fix retlen handling in sst_write()Tudor Ambarus2019-11-011-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case the write of the first byte failed, retlen was incorrectly incremented to *retlen += actual; on the exit path. retlen should be incremented when actual data was written to the flash. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Drop redundant error reports in Reg Ops callersTudor Ambarus2019-11-011-40/+10
| | | | | | | | | | | | | | | | | | | | | | | | Drop the error messages from the callers, since the callees already print an error message in case of failure. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Pointer parameter for CR in spi_nor_read_cr()Tudor Ambarus2019-11-011-25/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Configuration Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_cr() with negative, spi_nor_read_cr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Pointer parameter for FSR in spi_nor_read_fsr()Tudor Ambarus2019-11-011-18/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Flag Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Caller stops compare the return value of spi_nor_read_fsr() with negative, spi_nor_read_fsr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Pointer parameter for SR in spi_nor_read_sr()Tudor Ambarus2019-11-011-53/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Let the callers pass the pointer to the DMA-able buffer where the value of the Status Register will be written. This way we avoid the casts between int and u8, which can be confusing. Callers stop compare the return value of spi_nor_read_sr() with negative, spi_nor_read_sr() returns 0 on success and -errno otherwise. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Don't overwrite errno from Reg OpsTudor Ambarus2019-11-011-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | Do not overwrite the error numbers received the Register Operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Drop explicit cast to int to already int valueTudor Ambarus2019-11-011-9/+6
| | | | | | | | | | | | | | | | | | | | | ret is already of type int. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Stop compare with negative in Reg Ops methodsTudor Ambarus2019-11-011-10/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | spi_mem_exec_op() nor->controller_ops->write_reg() nor->controller_ops->read_reg() spi_nor_wait_till_ready() Return 0 on success, -errno otherwise. Stop compare with negative and compare with zero in all the register operations methods. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Group all Reg Ops to avoid forward declarationsTudor Ambarus2019-11-011-213/+213
| | | | | | | | | | | | | | | | | | | | | | | | Group all register methods up in the file, to avoid forward declarations. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Drop duplicated new lineTudor Ambarus2019-11-011-1/+0
| | | | | | | | | | | | | | | | | | | | | Two new lines, one after another, drop one. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: Prepend spi_nor_ to all Reg Ops methodsTudor Ambarus2019-11-011-54/+56
| | | | | | | | | | | | | | | | | | | | | All the core functions should begin with "spi_nor_". Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
| * | mtd: spi-nor: cadence-quadspi: Fix cqspi_command_read() definitionTudor Ambarus2019-10-231-8/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | n_tx was never used, drop it. Replace 'const u8 *txbuf' with 'u8 opcode', to comply with the SPI NOR int (*read_reg)() method. The 'const' qualifier has no meaning for parameters passed by value, drop it. Going furher, the opcode was passed to cqspi_calc_rdreg() and never used, drop it. Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
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