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* docs: mtd: move it to the driver-api bookMauro Carvalho Chehab2019-07-151-1/+1
| | | | | | | | | | While I was tempted to move it to admin-guide, as some docs there are more userspace-faced, there are some very technical discussions about memory error correction code from the Kernel implementer's PoV. So, let's place it inside the driver-api book. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* docs: mtd: convert to ReSTMauro Carvalho Chehab2019-07-151-1/+1
| | | | | | | | | | | | | | | | Rename the mtd documentation files to ReST, add an index for them and adjust in order to produce a nice html output via the Sphinx build system. It should be noticed that Sphinx doesn't handle very well URLs with dots in the middle. Thankfully, internally, the '.' char is translated to %2E, so we can jus use %2E instead of dots, and this will work fine on both text and processed files. At its new index.rst, let's add a :orphan: while this is not linked to the main index.rst file, in order to avoid build warnings. Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
* Merge tag 'mtd/for-5.3' of ↵Linus Torvalds2019-07-1434-2427/+2334
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux Pull MTD updates from Miquel Raynal: "This contains the following changes for MTD: MTD core changes: - New Hyperbus framework - New _is_locked (concat) implementation - Various cleanups NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: - fix BCH ECC layout for large page NAND parts - fallback to detected ecc-strength, ecc-step-size - when oops in progress use pio and interrupt polling - code refactor code to introduce helper functions - add support for v7.3 controller - FSMC: - use nand_op_trace for operation tracing - GPMI: - move all driver code into single file - various cleanups (including dmaengine changes) - use runtime PM to manage clocks - implement exec_op - MTK: - correct low level time calculation of r/w cycle - improve data sampling timing for read cycle - add validity check for CE# pin setting - fix wrongly assigned OOB buffer pointer issue - re-license MTK NAND driver as Dual MIT/GPL - STM32: - manage the get_irq error case - increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control" * tag 'mtd/for-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux: (60 commits) mtd: concat: implement _is_locked mtd operation mtd: concat: refactor concat_lock/concat_unlock mtd: abi: do not use C++ style comments in uapi header mtd: afs: remove unneeded NULL check mtd: rawnand: stm32_fmc2: increase DMA completion timeouts mtd: rawnand: Use kzalloc() instead of kmalloc() and memset() mtd: hyperbus: Add driver for TI's HyperBus memory controller mtd: spinand: read returns badly if the last page has bitflips mtd: spinand: Add initial support for Paragon PN26G0xA mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPL mtd: rawnand: gpmi: remove double assignment to block_size dt-bindings: mtd: brcmnand: Add brcmnand, brcmnand-v7.3 support mtd: rawnand: brcmnand: Add support for v7.3 controller mtd: rawnand: brcmnand: Refactored code to introduce helper functions mtd: rawnand: brcmnand: When oops in progress use pio and interrupt polling mtd: Add flag to indicate panic_write mtd: rawnand: Add Macronix NAND read retry support mtd: onenand: Avoid fall-through warnings mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxG mtd: spinand: Add support for two-byte device IDs ...
| * Merge tag 'spi-nor/for-5.3-v2' of ↵Miquel Raynal2019-07-079-747/+60
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gitolite.kernel.org:pub/scm/linux/kernel/git/mtd/linux into mtd/next SPI-NOR core changes: - add support for the mt25ql02g and w25q16jv flashes - print error in case of jedec read id fails - is25lp256: add post BFPT fix to correct the addr_width SPI NOR controller drivers changes: - intel-spi: Add support for Intel Elkhart Lake SPI serial flash - smt32: remove the driver as the driver was replaced by spi-stm32-qspi.c - cadence-quadspi: add reset control
| | * mtd: spi-nor: cadence-quadspi: add reset controlDinh Nguyen2019-06-271-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Get the reset control properties for the QSPI controller and bring them out of reset. Most will have just one reset bit, but there is an additional OCP reset bit that is used ECC. The OCP reset bit will also need to get de-asserted as well. [1] The reason this patch is needed is in the case where a bootloader leaves the QSPI controller in a reset state, or a state where init cannot occur successfully, the patch will put the QSPI controller into a clean state. [1] https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html Suggested-by: Tien-Fong Chee <tien.fong.chee@intel.com> Signed-off-by: Dinh Nguyen <dinguyen@kernel.org> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> [tudor.ambarus@microchip.com: declare rstc and rstc_ocp on the same line] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: fix nor->addr_width when its value configured from SFDP does ↵Liu Xiang2019-06-271-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | not match the actual width IS25LP256 gets BFPT_DWORD1_ADDRESS_BYTES_3_ONLY from BFPT table for address width. But in actual fact the flash can support 4-byte address. Use a post bfpt fixup hook to overwrite the address width advertised by the BFPT. Signed-off-by: Liu Xiang <liu.xiang6@zte.com.cn> Reviewed-by: Vignesh Raghavendra <vigneshr@ti.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: intel-spi: Convert to use SPDX identifierMika Westerberg2019-06-224-16/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | This gets rid of the license boilerplate duplicated in each file. No functional changes intended. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: intel-spi: Add support for Intel Elkhart Lake SPI serial flashMika Westerberg2019-06-221-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | Intel Elkhart Lake has the same SPI serial flash controller as Ice Lake. Add Elkhart Lake PCI ID to the driver list of supported devices. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Spelling s/Writ/Write/Geert Uytterhoeven2019-06-221-1/+1
| | | | | | | | | | | | | | | Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Add Winbond w25q16jv supportRobert Marko2019-06-221-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Testing done on Mikrotik Routerboard RB450Gx4 board under 4.14.119 and 4.19.43 kernels. The test board does not support Dual or Quad modes. Datasheet at: https://www.winbond.com/resource-files/w25q16jv%20spi%20revg%2003222018%20plus.pdf Signed-off-by: Robert Marko <robimarko@gmail.com> [tudor.ambarus@microchip.com: w25q16jv-im/jm and w25q16jv-iq/jq have different jedec ids, fix flash name.] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: change "error reading JEDEC id" from dbg to errFlavio Suligoi2019-06-071-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of SPI error during the reading of the nor Id, the probe fails without any error message related to the JEDEC Id reading procedure. Signed-off-by: Flavio Suligoi <f.suligoi@asem.it> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: Add Micron MT25QL02 supportAndrey Smirnov2019-06-071-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an entry for Micron MT25QL02 which is a 3V variant of already supported MT25QU02. Testing was done on a ZII VF610 Dev Board (rev. B). Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com> Signed-off-by: Andrey Smirnov <andrew.smirnov@gmail.com> Cc: Chris Healy <cphealy@gmail.com> Cc: Marek Vasut <marek.vasut@gmail.com> Cc: Tudor Ambarus <tudor.ambarus@microchip.com> Cc: linux-mtd@lists.infradead.org Cc: linux-kernel@vger.kernel.org [tudor.ambarus@microchip.com: order entry alphabetically, wrap to 80 chars limit] Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| | * mtd: spi-nor: stm32: remove the driver as it was replaced by spi-stm32-qspi.cLudovic Barre2019-06-073-728/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There's a new driver using the SPI memory interface of the SPI framework at spi/spi-stm32-qspi.c, which can be used together with m25p80.c to replace the functionality of this SPI NOR driver. The "new" driver uses the same dt properties and not affects the legacy compatibility. Signed-off-by: Ludovic Barre <ludovic.barre@st.com> Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
| * | mtd: concat: implement _is_locked mtd operationChris Packham2019-07-071-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add an implementation of the _is_locked operation for concatenated mtd devices. This doesn't handle getting the lock status of a range that spans chips, which is consistent with cfi_ppb_is_locked and cfi_intelext_is_locked which only look at the first block in the range. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: concat: refactor concat_lock/concat_unlockChris Packham2019-07-071-32/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | concat_lock() and concat_unlock() only differed in terms of the mtd_xx operation they called. Refactor them to use a common helper function and pass a boolean flag to indicate whether lock or unlock is needed. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | mtd: afs: remove unneeded NULL checkDing Xiang2019-07-071-2/+1
| | | | | | | | | | | | | | | | | | | | | NULL check before kfree is unneeded, so remove it. Signed-off-by: Ding Xiang <dingxiang@cmss.chinamobile.com> Signed-off-by: Richard Weinberger <richard@nod.at>
| * | Merge tag 'nand/for-5.3' of ↵Richard Weinberger2019-07-06136-2685/+1928
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux into mtd/next NAND core changes: - use longest matching pattern in ->exec_op() default parser - export NAND operation tracer - add flag to indicate panic_write in MTD - use kzalloc() instead of kmalloc() and memset() Raw NAND controller drivers changes: - brcmnand: * fix BCH ECC layout for large page NAND parts * fallback to detected ecc-strength, ecc-step-size * when oops in progress use pio and interrupt polling * code refactor code to introduce helper functions * add support for v7.3 controller - FSMC: * use nand_op_trace for operation tracing - GPMI: * move all driver code into single file * various cleanups (including dmaengine changes) * use runtime PM to manage clocks * implement exec_op - MTK: * correct low level time calculation of r/w cycle * improve data sampling timing for read cycle * add validity check for CE# pin setting * fix wrongly assigned OOB buffer pointer issue * re-license MTK NAND driver as Dual MIT/GPL - STM32: * manage the get_irq error case * increase DMA completion timeouts Raw NAND chips drivers changes: - Macronix: add read-retry support Onenand driver changes: - add support for 8Gb datasize chips - avoid fall-through warnings SPI-NAND changes: - define macros for page-read ops with three-byte addresses - add support for two-byte device IDs and then for GigaDevice GD5F1GQ4UFxxG - add initial support for Paragon PN26G0xA - handle the case where the last page read has bitflips
| | * | mtd: rawnand: stm32_fmc2: increase DMA completion timeoutsAmelie Delaunay2019-06-281-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the system is overloaded, DMA data transfer completion occurs after 100ms. Increase the timeouts to let it the time to complete. Signed-off-by: Amelie Delaunay <amelie.delaunay@st.com> Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: Use kzalloc() instead of kmalloc() and memset()Fuqian Huang2019-06-281-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace kmalloc() by a memset() followed with a kzalloc(). There is a recommendation to use zeroing allocator rather than allocator followed by memset(0) in ./scripts/coccinelle/api/alloc/zalloc-simple.cocci Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spinand: read returns badly if the last page has bitflipsliaoweixiong2019-06-281-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of the last page containing bitflips (ret > 0), spinand_mtd_read() will return that number of bitflips for the last page while it should instead return max_bitflips like it does when the last page read returns with 0. Signed-off-by: Weixiong Liao <liaoweixiong@allwinnertech.com> Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Cc: stable@vger.kernel.org Fixes: 7529df465248 ("mtd: nand: Add core infrastructure to support SPI NANDs") Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spinand: Add initial support for Paragon PN26G0xAJeff Kletsky2019-06-273-1/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add initial support for Paragon Technology PN26G01Axxxxx and PN26G02Axxxxx SPI NAND Datasheets available at http://www.xtxtech.com/upfile/2016082517274590.pdf http://www.xtxtech.com/upfile/2016082517282329.pdf Signed-off-by: Jeff Kletsky <git-commits@allycomm.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: mtk: Re-license MTK NAND driver as Dual MIT/GPLXiaolei Li2019-06-273-7/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | It is wanted to use MTK NAND driver with GPL-2.0 or MIT license. But now it is only licensed as GPL-2.0, so re-license it as dual MIT/GPL. Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Acked-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org> Acked-by: Ryder Lee <ryder.lee@mediatek.com> Acked-by: Rafał Miłecki <rafal@milecki.pl> Acked-by: Miquel Raynal <miquel.raynal@bootlin.com> Acked-by: Boris Brezillon <boris.brezillon@collabora.com> Acked-by: Wen Yang <yellowriver2010@hotmail.com> Acked-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Acked-by: RogerCC Lin <rogercc.lin@mediatek.com> Reviewed-by: Matthias Brugger <matthias.bgg@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: remove double assignment to block_sizeColin Ian King2019-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The variable block_size is being assigned to itself and to geo->ecc_chunk_size. Clean up the double assignment by removing the assignment to itself. Addresses-Coverity: ("Evaluation order violation") Signed-off-by: Colin Ian King <colin.king@canonical.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: brcmnand: Add support for v7.3 controllerKamal Dasu2019-06-271-22/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change adds support for brcm NAND v7.3 controller. This controller uses a newer version of flash_dma engine and change mostly implements these differences. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: brcmnand: Refactored code to introduce helper functionsKamal Dasu2019-06-271-38/+62
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactored NAND ECC and CMD address configuration code to use helper functions. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: brcmnand: When oops in progress use pio and interrupt pollingKamal Dasu2019-06-271-3/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If mtd_oops is in progress, switch to polling during NAND command completion instead of relying on DMA/interrupts so that the mtd_oops buffer can be completely written in the assigned NAND partition. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: Add flag to indicate panic_writeKamal Dasu2019-06-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Added a flag to indicate a panic_write so that low level drivers can use it to take required action where applicable, to ensure oops data gets written to assigned mtd device. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: Add Macronix NAND read retry supportMason Yang2019-06-271-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Macronix NAND read retry. Macronix NANDs support specific read operation for data recovery, which can be enabled with a SET_FEATURE. Driver checks byte 167 of Vendor Blocks in ONFI parameter page table to see if this high-reliability function is supported. Signed-off-by: Mason Yang <masonccyang@mxic.com.tw> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: onenand: Avoid fall-through warningsGustavo A. R. Silva2019-06-271-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | NOTICE THAT: "...we don't know whether we need fallthroughs or breaks here and this is just a change to avoid having new warnings when switching to -Wimplicit-fallthrough but this change might be entirely wrong."[1] See the original thread of discussion here: https://lore.kernel.org/patchwork/patch/1036251/ So, in preparation to enabling -Wimplicit-fallthrough, this patch silences the following warnings: drivers/mtd/nand/onenand/onenand_base.c: In function ‘onenand_check_features’: drivers/mtd/nand/onenand/onenand_base.c:3264:6: warning: this statement may fall through [-Wimplicit-fallthrough=] if (ONENAND_IS_DDP(this)) ^ drivers/mtd/nand/onenand/onenand_base.c:3284:2: note: here case ONENAND_DEVICE_DENSITY_2Gb: ^~~~ drivers/mtd/nand/onenand/onenand_base.c:3288:17: warning: this statement may fall through [-Wimplicit-fallthrough=] this->options |= ONENAND_HAS_UNLOCK_ALL; drivers/mtd/nand/onenand/onenand_base.c:3290:2: note: here case ONENAND_DEVICE_DENSITY_1Gb: ^~~~ Warning level 3 was used: -Wimplicit-fallthrough=3 Also, notice that this patch doesn't change any functionality. See the most recent thread of discussion here: https://lore.kernel.org/patchwork/patch/1077395/ This patch is part of the ongoing efforts to enable -Wimplicit-fallthrough. [1] https://lore.kernel.org/lkml/20190509085318.34a9d4be@xps13/ Cc: Miquel Raynal <miquel.raynal@bootlin.com> Suggested-by: Boris Brezillon <boris.brezillon@collabora.com> Suggested-by: Kees Cook <keescook@chromium.org> Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com> Reviewed-by: Kees Cook <keescook@chromium.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spinand: Add support for GigaDevice GD5F1GQ4UFxxGJeff Kletsky2019-06-271-15/+64
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GigaDevice GD5F1GQ4UFxxG SPI NAND is in current production devices and, while it has the same logical layout as the E-series devices, it differs in the SPI interfacing in significant ways. This support is contingent on previous commits to: * Add support for two-byte device IDs * Define macros for page-read ops with three-byte addresses http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/ Signed-off-by: Jeff Kletsky <git-commits@allycomm.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: spinand: Add support for two-byte device IDsJeff Kletsky2019-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The GigaDevice GD5F1GQ4UFxxG SPI NAND utilizes two-byte device IDs. http://www.gigadevice.com/datasheet/gd5f1gq4xfxxg/ Signed-off-by: Jeff Kletsky <git-commits@allycomm.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: brcmnand: fallback to detected ecc-strength, ecc-step-sizeKamal Dasu2019-06-271-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change supports nand-ecc-step-size and nand-ecc-strength fields in brcmnand DT node to be optional. see: Documentation/devicetree/bindings/mtd/brcm,brcmnand.txt If both nand-ecc-strength and nand-ecc-step-size are not specified in device tree node for NAND, raw NAND layer does detect ECC information by reading ONFI extended parameter page for parts using ONFI >= 2.1. In case of non-ONFI NAND parts there could be a nand_id table entry with ECC information. If there is valid device tree entry for nand-ecc-strength and nand-ecc-step-size fields it still shall override the detected values. Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: Implement exec_opSascha Hauer2019-06-272-690/+440
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpmi driver performance suffers from NAND operations being split in multiple small DMA transfers. This has been forced by the NAND layer in the former days, but now with exec_op we can use the controller as intended. With this patch gpmi_nfc_exec_op becomes the main entry point to NAND operations. Here all instructions are collected and chained as separate DMA transfers. In the end whole chain is fired and waited to be finished. gpmi_nfc_exec_op only does the hardware operations, bad block marker swapping and buffer scrambling is done by the callers. It's worth noting that the nand_*_op functions always take the buffer lengths for the data that the NAND chip actually transfers. When doing BCH we have to calculate the net data size from the raw data size in some places. This patch has been tested with 2048/64 and 2048/128 byte NAND on i.MX6q. mtd_oobtest, mtd_subpagetest and mtd_speedtest run without errors. nandbiterrs, nandpagetest and nandsubpagetest userspace tests from mtdutils run without errors and UBIFS can successfully be mounted. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | dmaengine: mxs: rename custom flagSascha Hauer2019-06-271-6/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mxs dma driver uses the flags parameter in dmaengine_prep_slave_sg() for custom flags, but still uses the dmaengine specific names of the flags. Do a little bit better and at least give the flag a custom name. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | dmaengine: mxs: Add header file to be shared with gpmi nand driverSascha Hauer2019-06-271-22/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The mxs dma driver can do PIO transfers. A pointer to the PIO words to transfer is passed in the struct scatterlist * argument of dmaengine_prep_slave_sg(). It's quite ugly and non obvious to cast u32 * to struct scatterlist * each time when calling dmaengine_prep_slave_sg(), so add a static inline wrapper function to be called by the user along with a description what is going on. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Acked-by: Vinod Koul <vkoul@kernel.org> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: drop unnecessary flagSascha Hauer2019-06-271-9/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DMA_PREP_INTERRUPT flag is no longer needed by the mxs DMA driver, drop it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: use runtime PM to manage clocksSascha Hauer2019-06-271-25/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The gpmi driver aggressively en/disables the clocks between operations which has significant performance cost. Use runtime PM to get rid of this bottleneck. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: Drop unnecessary restoring of previous chipselectionSascha Hauer2019-06-271-14/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The i.MX23 specific option read code is called right after nand_scan. We can rely on the NAND core having disabled the chipselect, so there's no point in restoring the original chip select after NAND operations. Drop it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: remove unused parametersSascha Hauer2019-06-271-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | gpmi_ecc_read_page_data uses the page parameter only for a debug printf, so we can drop the parameter and the debug printf. Moving the oob delivery from gpmi_ecc_read_page_data to gpmi_ecc_read_page makes the oob_required parameter unnecessary aswell. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: read buf in nand_read_page_opSascha Hauer2019-06-271-8/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The driver calls nand_read_page_op without a buffer passed and then calls chip->legacy.read_buf to read the buffer afterwards which is the same as passing the buffer nand_read_page_op in the first place. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: Remove unnecessary variablesSascha Hauer2019-06-272-11/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | this->page_buffer_virt and this->payload_virt are always set to the same value, so drop the former and just use the latter. Same for this->page_buffer_virt and this->payload_virt. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: remove unused variableSascha Hauer2019-06-271-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The "private" member of struct gpmi_nand_data isn't used anywhere. Remove it. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: gpmi: move all driver code into single fileSascha Hauer2019-06-274-1106/+1058
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the whole driver into a single C file. The filename gpmi-lib implies that it implements library functions, but in fact there are several cases where functions in gpmi-lib.c call back into functions in gpmi-nand.c. With this one has to constantly jump between those two files, so moving it into a single file improves readability, even when the file gets quite large. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: fsmc: Use nand_op_trace for operation tracingSascha Hauer2019-06-271-17/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace the different operation tracing functions with a call to nand_op_trace. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: export NAND operation tracerSascha Hauer2019-06-271-29/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The NAND core has a NAND operation tracing function, but it can only be used by drivers using the generic option parser from the NAND core. Export the tracing function as a static inline function in rawnand.h so that drivers implementing exec_op directly do not have to write their own operation tracing. Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: mtk: Fix wrongly assigned OOB buffer pointer issueXiaolei Li2019-06-271-11/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | One main goal of the function mtk_nfc_update_ecc_stats is to check whether sectors are all empty. If they are empty, set these sectors's data buffer and OOB buffer as 0xff. But now, the sector OOB buffer pointer is wrongly assigned. We always do memset from sector 0. To fix this issue, pass start sector number to make OOB buffer pointer be properly assigned. Fixes: 1d6b1e464950 ("mtd: mediatek: driver for MTK Smart Device") Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: mtk: Add validity check for CE# pin settingXiaolei Li2019-06-271-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we only check how many CE# pins are set in device tree. But it should be necessary to check whether CE# pin setting is duplicated or if CE# pin index exceeds the maximum CE# number that controller supports. So, add validity check to avoid these invalid settings. Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: mtk: Improve data sampling timing for read cycleXiaolei Li2019-06-271-10/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, we expand RE# low level time by choosing the max value between RE# pulse width and RE# access time, and sample data at the rising edge of RE#. Then, if RE# access time is bigger than RE# pulse width, the real read cycle time may be more than NAND SPEC required. This makes read performance be worse than that expected. This patch improves data sampling timing by calculating RE# low level time according to RE# pulse width. If RE# access time is bigger than RE# pulse width, then delay sampling data timing. The result of contrast test base on MT2712 evaluat board is as follow. nand: Micron MT29F16G08ADBCAH4 nand: 2048 MiB, SLC, erase size: 256 KiB, page size: 4096, OOB size: 224 NFI 2x clock rate: 124800000 HZ. Read speed without this patch: mtd_speedtest: page read speed is 14012 KiB/s mtd_speedtest: 2 page read speed is 14860 KiB/s Read speed with this patch: mtd_speedtest: page read speed is 18724 KiB/s mtd_speedtest: 2 page read speed is 18713 KiB/s Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: mtk: Correct low level time calculation of r/w cycleXiaolei Li2019-06-271-3/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present, the flow of calculating AC timing of read/write cycle in SDR mode is that: At first, calculate high hold time which is valid for both read and write cycle using the max value between tREH_min and tWH_min. Secondly, calculate WE# pulse width using tWP_min. Thridly, calculate RE# pulse width using the bigger one between tREA_max and tRP_min. But NAND SPEC shows that Controller should also meet write/read cycle time. That is write cycle time should be more than tWC_min and read cycle should be more than tRC_min. Obviously, we do not achieve that now. This patch corrects the low level time calculation to meet minimum read/write cycle time required. After getting the high hold time, WE# low level time will be promised to meet tWP_min and tWC_min requirement, and RE# low level time will be promised to meet tREA_max, tRP_min and tRC_min requirement. Fixes: edfee3619c49 ("mtd: nand: mtk: add ->setup_data_interface() hook") Cc: stable@vger.kernel.org # v4.17+ Signed-off-by: Xiaolei Li <xiaolei.li@mediatek.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
| | * | mtd: rawnand: brcmnand: Fix BCH ECC layout for large page NAND partsKamal Dasu2019-06-271-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The way oobregion->offset is derived for large page NAND parts is wrong, fixes it. Fixes: ef5eeea6e911 ("mtd: nand: brcm: switch to mtd_ooblayout_ops") Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com> Reviewed-by: Florian Fainelli <f.fainelli@gmail.com> Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
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