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* NTB: Add IDT 89HPESxNTx PCIe-switches supportSerge Semin2017-07-066-0/+3895
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IDT 89HPESxNTx device series is PCIe-switches, which support Non-Transparent bridging between domains connected to the device ports. Since new NTB API exposes multi-port interface and messaging API, the IDT NT-functions can be now supported in the kernel. This driver adds the following functionality: 1) Multi-port NTB API to have information of possible NT-functions activated in compliance with available device ports. 2) Memory windows of direct and look up table based address translation with all possible combinations of BARs setup. 3) Traditional doorbell NTB API. 4) One-on-one messaging NTB API. There are some IDT PCIe-switch setups, which must be done before any of the NTB peers started. It can be performed either by system BIOS via IDT SMBus-slave interface or by pre-initialized IDT PCIe-switch EEPROM: 1) NT-functions of corresponding ports must be activated using SWPARTxCTL and SWPORTxCTL registers. 2) BAR0 must be configured to expose NT-function configuration registers map. 3) The rest of the BARs must have at least one memory window configured, otherwise the driver will just return an error. Temperature sensor of IDT PCIe-switches can be also optionally activated by BIOS or EEPROM. (See IDT documentations for details of how the pre-initialization can be done) Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb_hw_intel: Style fixes: open code macros that just obfuscate codeLogan Gunthorpe2017-07-062-100/+95
| | | | | | | | | | | As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should be cleaned up. This makes it more clear what's actually going on when reading the code. [1] http://www.spinics.net/lists/linux-pci/msg56904.html Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb_hw_amd: Style fixes: open code macros that just obfuscate codeLogan Gunthorpe2017-07-062-29/+29
| | | | | | | | | | | As per a comments in [1] by Greg Kroah-Hartman, the ndev_* macros should be cleaned up. This makes it more clear what's actually going on when reading the code. [1] http://www.spinics.net/lists/linux-pci/msg56904.html Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Alter Scratchpads API to support multi-ports devicesSerge Semin2017-07-062-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | Even though there is no any real NTB hardware, which would have both more than two ports and Scratchpad registers, it is logically correct to have Scratchpad API accepting a peer port index as well. Intel/AMD drivers utilize Primary and Secondary topology to split Scratchpad between connected root devices. Since port-index API introduced, Intel/AMD NTB hardware drivers can use device port to determine which Scratchpad registers actually belong to local and peer devices. The same approach can be used if some potential hardware in future will be multi-port and have some set of Scratchpads. Here are the brief of changes in the API: ntb_spad_count() - return number of Scratchpads per each port ntb_peer_spad_addr(pidx, sidx) - address of Scratchpad register of the peer device with pidx-index ntb_peer_spad_read(pidx, sidx) - read specified Scratchpad register of the peer with pidx-index ntb_peer_spad_write(pidx, sidx) - write data to Scratchpad register of the peer with pidx-index Since there is hardware which doesn't support Scratchpad registers, the corresponding API methods are now made optional. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Alter MW API to support multi-ports devicesSerge Semin2017-07-062-37/+121
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Multi-port NTB devices permit to share a memory between all accessible peers. Memory Windows API is altered to correspondingly initialize and map memory windows for such devices: ntb_mw_count(pidx); - number of inbound memory windows, which can be allocated for shared buffer with specified peer device. ntb_mw_get_align(pidx, widx); - get alignment and size restriction parameters to properly allocate inbound memory region. ntb_peer_mw_count(); - get number of outbound memory windows. ntb_peer_mw_get_addr(widx); - get mapping address of an outbound memory window If hardware supports inbound translation configured on the local ntb port: ntb_mw_set_trans(pidx, widx); - set translation address of allocated inbound memory window so a peer device could access it. ntb_mw_clear_trans(pidx, widx); - clear the translation address of an inbound memory window. If hardware supports outbound translation configured on the peer ntb port: ntb_peer_mw_set_trans(pidx, widx); - set translation address of a memory window retrieved from a peer device ntb_peer_mw_clear_trans(pidx, widx); - clear the translation address of an outbound memory window Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Alter link-state API to support multi-port devicesSerge Semin2017-07-062-2/+2
| | | | | | | | | | | Multi-port devices permit the NTB connections between multiple domains, so a local device can have NTB link being up with one peer and being down with another. NTB link-state API is appropriately altered to return a bitfield of the link-states between the local device and possible peers. Signed-off-by: Serge Semin <fancer.lancer@gmail.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: ntb_hw_intel: Skylake doorbells should be 32bits, not 64bitsDave Jiang2017-06-191-1/+1
| | | | | | | | | | | Fixing doorbell register length to 32bits per spec. On Skylake NTB, the doorbell registers are 32bit write only registers. The source for the doorbell is a 64bit register that shows the interrupt bits. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Fixes: 783dfa6cc41b ("ntb: Adding Skylake Xeon NTB support") Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: ntb_hw_intel: link_poll isn't clearing the pending status properlyDave Jiang2017-02-171-1/+23
| | | | | | | | | | On Skylake hardware, the link_poll isn't clearing the pending interrupt bit. Adding a new function for SKX that handles clearing of status bit the right way. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Fixes: 783dfa6c ("ntb: Adding Skylake Xeon NTB support") Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Fix 'request_irq()' and 'free_irq()' inconsistancyChristophe JAILLET2016-12-232-2/+2
| | | | | | | | 'request_irq()' and 'free_irq()' should have the same 'dev_id'. Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: fix SKX NTB config space size register offsetsDave Jiang2016-12-231-4/+4
| | | | | | | | | The offsets for the SZ registers are wrong. Updated. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Reported-by: Sandeep Mann <sandeep@purestorage.com> Tested-by: Zachary Ross <zacharyx.ross@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Register and offset values fix for memory windowShyam Sundar S K2016-12-231-10/+4
| | | | | | | | | | | | | Due to incorrect limit and translation register values, NTB link was going down when the memory window was setup. Made appropriate changes as per spec. Fix limit register values for BAR1, which was overlapping with the BAR23 address. Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: add support for hotplug featureXiangliang Yu2016-12-232-2/+12
| | | | | | | | | | | AMD NTB support hotplug under B2B mode. NTB will trigger link up/down interrupt event when doing plug add/remove, this patch implements the two interrupt event to support B2B hotplug function. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Shyam Sundar S K <Shyam-sundar.S-k@amd.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: Adding Skylake Xeon NTB supportDave Jiang2016-12-232-5/+703
| | | | | | | | | | The Skylake Xeon NTB hardware has made some changes to the register name, offset, and the way doorbells work. Adding driver support for the new hardware. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Allen Hubbe <Allen.Hubbe@dell.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* ntb: ntb_hw_intel: init peer_addr in struct intel_ntb_devDave Jiang2016-11-131-0/+3
| | | | | | | | | | The peer_addr member of intel_ntb_dev is not set, therefore when acquiring ntb_peer_db and ntb_peer_spad we only get the offset rather than the actual physical address. Adding fix to correct that. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: ntb_hw_intel: Fix typo in module parameter descriptionsWei Yongjun2016-11-131-6/+6
| | | | | | | | Fix typo in module parameter descriptions. Signed-off-by: Wei Yongjun <weiyj.lk@gmail.com> Acked-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: ntb_hw_intel: use local variable pdevAllen Hubbe2016-08-051-5/+5
| | | | | | | | | Clean up duplicated expression by replacing it with the equivalent local variable pdev. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: ntb_hw_intel: show BAR size in debugfs infoAllen Hubbe2016-08-051-1/+38
| | | | | | | | | It will be useful to know the hardware configured BAR size to diagnose issues with NTB memory windows. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Remove _addr functions from ntb_hw_amdAllen Hubbe2016-03-261-30/+0
| | | | | | | | | | | | | Kernel zero day testing warned about address space confusion. A virtual iomem address was used where a physical address is expected. The offending functions implement an optional part of the api, so they are removed. They can be added later, after testing. Fixes: a1b3695820aa490e58915d720a1438069813008b Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Acked-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Fix macro parameter conflict with field nameAllen Hubbe2016-01-221-2/+3
| | | | | | | | | | | | | | | | | | If the parameter given to the macro is replaced throughout the macro as it is evaluated. The intent is that the macro parameter should replace the only the first parameter to container_of(). However, the way the macro was written, it would also inadvertantly replace a structure field name. If a parameter of any other name is given to the macro, it will fail to compile, if the structure does not contain a field of the same name. At worst, it will compile, and hide improper access of an unintended field in the structure. Change the macro parameter name, so it does not conflict with the structure field name. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Acked-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Add support for AMD PCI-Express Non-Transparent BridgeXiangliang Yu2016-01-226-0/+1370
| | | | | | | | | | | | | This adds support for AMD's PCI-Express Non-Transparent Bridge (NTB) device on the Zeppelin platform. The driver connnects to the standard NTB sub-system interface, with modification to add hooks for power management in a separate patch. The AMD NTB device has 3 memory windows, 16 doorbell, 16 scratch-pad registers, and supports up to 16 PCIe lanes running a Gen3 speeds. Signed-off-by: Xiangliang Yu <Xiangliang.Yu@amd.com> Reviewed-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Clear property bits in BAR valueDave Jiang2016-01-112-2/+5
| | | | | | | | | | The lower bits read from a BAR register will contain property bits that we do not care about. Clear those so that we can use the BAR values for limit and xlat registers. Reported-by: Conrad Meyer <cem@freebsd.org> Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: unify translation addressesDave Jiang2015-11-082-18/+13
| | | | | | | | | | | There is no need for the upstream and downstream addresses to be different for the NTB configs. Go to using a single set of address. It is still possible to configure them differently using module parameter override however. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Acked and Tested-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Fix range check on memory window indexAllen Hubbe2015-09-071-1/+1
| | | | | | | The range check must exclude the upper bound. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Improve index handling in B2B MW workaroundAllen Hubbe2015-09-071-6/+16
| | | | | | | | | | | | | Check that b2b_mw_idx is in range of the number of memory windows when initializing the device. The workaround is considered to be in effect only if the device b2b_idx is exactly UINT_MAX, instead of any index past the last memory window. Only print B2B MW workaround information in debugfs if the workaround is in effect. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Add PCI Device IDs for Broadwell XeonDave Jiang2015-09-072-0/+18
| | | | | | | | Adding PCI Device IDs for B2B (back to back), RP (root port, primary), and TB (transparent bridge, secondary) devices. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Add split BAR output for debugfs statsDave Jiang2015-07-041-15/+68
| | | | | | | | When split BAR is enabled, the driver needs to dump out the split BAR registers rather than the original 64bit BAR registers. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Change WARN_ON_ONCE to pr_warn_once on unsafeDave Jiang2015-07-041-8/+16
| | | | | | | | The unsafe doorbell and scratchpad access should display reason when WARN is called. Otherwise we get a stack dump without any explanation. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Print driver name and version in module initDave Jiang2015-07-041-0/+4
| | | | | | | Printouts driver name and version to indicate what is being loaded. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Rename Intel code names to platform namesDave Jiang2015-07-042-455/+455
| | | | | | | | Instead of using the platform code names, use the correct platform names to identify the respective Intel NTB hardware. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Use NUMA memory in Intel driverAllen Hubbe2015-07-041-6/+12
| | | | | | | Allocate memory for the NUMA node of the NTB device. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Add parameters for Intel SNB B2B addressesAllen Hubbe2015-07-041-19/+58
| | | | | | | Add module parameters for the addresses to be used in B2B topology. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Check the device ID to set errata flagsDave Jiang2015-07-041-5/+44
| | | | | | | | Set errata flags for the specific device IDs to which they apply, instead of the whole Xeon hardware class. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Enable link for Intel root port mode in probeDave Jiang2015-07-041-0/+10
| | | | | | | | | | Link training should be enabled in the driver probe for root port mode. We should not have to wait for transport to be loaded for this to happen. Otherwise the ntb device will not show up on the transparent bridge side of the link. Signed-off-by: Dave Jiang <dave.jiang@intel.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Split ntb_hw_intel and ntb_transport driversAllen Hubbe2015-07-046-1751/+1939
| | | | | | | | | | Change ntb_hw_intel to use the new NTB hardware abstraction layer. Split ntb_transport into its own driver. Change it to use the new NTB hardware abstraction layer. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* NTB: Move files in preparation for NTB abstractionAllen Hubbe2015-07-022-0/+2279
This patch only moves files to their new locations, before applying the next two patches adding the NTB Abstraction layer. Splitting this patch from the next is intended make distinct which code is changed only due to moving the files, versus which are substantial code changes in adding the NTB Abstraction layer. Signed-off-by: Allen Hubbe <Allen.Hubbe@emc.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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