Commit message (Expand) | Author | Files | Lines | |
---|---|---|---|---|
2015-06-04 | clk: st: Use of_clk_get_parent_count() instead of open coding | Geert Uytterhoeven | 2 | -2/+2 |
2015-06-04 | clk: at91: Use of_clk_get_parent_count() instead of open coding | Geert Uytterhoeven | 6 | -7/+7 |
2015-06-04 | clk: pistachio: Add sanity checks on PLL configuration | Kevin Cernekee | 1 | -4/+79 |
2015-06-04 | clk: pistachio: Lock the PLL when enabled upon rate change | Ezequiel Garcia | 1 | -18/+10 |
2015-06-04 | clk: pistachio: Add a pll_lock() helper for clarity | Ezequiel Garcia | 1 | -4/+8 |
2015-06-04 | clk: mmp: add timer clock for pxa168/mmp2/pxa910 | Chao Xie | 6 | -0/+30 |
2015-06-04 | clk: mmp: Fix the wrong factor table for uart PLL | Chao Xie | 2 | -6/+2 |
2015-06-04 | clk: mmp: add fixed clock UBS_PLL for pxa910/pxa168 | Chao Xie | 4 | -0/+4 |
2015-06-04 | Add TI CDCE925 I2C controlled clock synthesizer driver | Mike Looijmans | 4 | -0/+809 |
2015-06-04 | clk: mvebu: add missing CESA gate clk | Boris Brezillon | 2 | -0/+2 |
2015-06-04 | clk: hi6220: Clock driver support for Hisilicon hi6220 SoC | Bintian Wang | 8 | -4/+496 |