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path: root/drivers/pci/host/pcie-iproc-bcma.c (follow)
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* PCI: Collect all native drivers under drivers/pci/controller/Shawn Lin2018-06-081-112/+0
| | | | | | | | | | | | | | | | | | Native PCI drivers for root complex devices were originally all in drivers/pci/host/. Some of these devices can also be operated in endpoint mode. Drivers for endpoint mode didn't seem to fit in the "host" directory, so we put both the root complex and endpoint drivers in per-device directories, e.g., drivers/pci/dwc/, drivers/pci/cadence/, etc. These per-device directories contain trivial Kconfig and Makefiles and clutter drivers/pci/. Make a new drivers/pci/controllers/ directory and collect all the device-specific drivers there. No functional change intended. Link: https://lkml.kernel.org/r/1520304202-232891-1-git-send-email-shawn.lin@rock-chips.com Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> [bhelgaas: changelog] Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: iproc: Remove dependency on ARM specific struct pci_sys_dataRob Herring2018-03-211-2/+1
| | | | | | | | | | The iproc driver is using ARM's struct pci_sys_data simply to store a private data pointer. This is completely unnecessary, so store the private data directly in bus->sysdata as is done on arm64. Signed-off-by: Rob Herring <robh@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Acked-by: Scott Branden <scott.branden@broadcom.com>
* PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateBjorn Helgaas2018-01-281-9/+1
| | | | | | | | | | | Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
* PCI: iproc: Convert PCI scan API to pci_scan_root_bus_bridge()Lorenzo Pieralisi2017-07-021-2/+5
| | | | | | | | | | | | | | | | | The introduction of pci_scan_root_bus_bridge() provides a PCI core API to scan a PCI root bus backed by an already initialized struct pci_host_bridge object, which simplifies the bus scan interface and makes the PCI scan root bus interface easier to generalize as members are added to the struct pci_host_bridge. Convert PCI iproc host code to pci_scan_root_bus_bridge() to improve the PCI root bus scanning interface. Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Scott Branden <sbranden@broadcom.com> Cc: Ray Jui <rjui@broadcom.com> Cc: Jon Mason <jonmason@broadcom.com>
* PCI: iproc: Save host bridge window resource in struct iproc_pcieBjorn Helgaas2017-03-091-12/+12
| | | | | | | | | | | | | | | | | | The host bridge memory window resource is inserted into the iomem_resource tree and cannot be deallocated until the host bridge itself is removed. Previously, the window was on the stack, which meant the iomem_resource entry pointed into the stack and was corrupted as soon as the probe function returned, which caused memory corruption and errors like this: pcie_iproc_bcma bcma0:8: resource collision: [mem 0x40000000-0x47ffffff] conflicts with PCIe MEM space [mem 0x40000000-0x47ffffff] Move the memory window resource from the stack into struct iproc_pcie so its lifetime matches that of the host bridge. Fixes: c3245a566400 ("PCI: iproc: Request host bridge window resources") Reported-and-tested-by: Rafał Miłecki <zajec5@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> CC: stable@vger.kernel.org # v4.8+
* PCI: iproc: Add BCMA typeRay Jui2016-11-141-0/+1
| | | | | | | | | | | | | | | The iProc PCIe driver is currently using type IPROC_PCIE_PAXB for the following SoCs: NS, NSP, Cygnus, NS2, and Pegasus. In fact, the BCMA-based NS uses a legacy PAXB controller that is slightly different from the PAXB controller used in the rest of SoCs, e.g., some registers are missing and it does not require software configuration of outbound/inbound address mapping. Add a new type, IPROC_PCIE_PAXB_BCMA, to allow us to properly support the BCMA-based NS along with other iProc-based SoCs going forward. Signed-off-by: Ray Jui <ray.jui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Scott Branden <scott.branden@broadcom.com>
* PCI: iproc: Validate CSR base in BCMA setup codeBjorn Helgaas2016-10-121-0/+5
| | | | | | | Validate iproc_pcie->base for BCMA devices just like we already do for platform devices in iproc_pcie_pltfm_probe(). No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: iproc: Set drvdata at end of probe functionBjorn Helgaas2016-10-121-1/+1
| | | | | | | | Set the drvdata pointer at the end of probe function for consistency with other drivers. We don't need the drvdata until after the probe completes, and we don't need it at all if the probe fails. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: iproc: Add local struct device pointersBjorn Helgaas2016-10-121-3/+4
| | | | | | Use a local "struct device *dev" for brevity and consistency with other drivers. No functional change intended. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: iproc: Add iProc PCIe MSI supportRay Jui2016-01-071-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add PCIe MSI support for both PAXB and PAXC interfaces on all iProc-based platforms. The iProc PCIe MSI support deploys an event queue-based implementation. Each event queue is serviced by a GIC interrupt and can support up to 64 MSI vectors. Host memory is allocated for the event queues, and each event queue consists of 64 word-sized entries. MSI data is written to the lower 16-bit of each entry, whereas the upper 16-bit of the entry is reserved for the controller for internal processing. Each event queue is tracked by a head pointer and tail pointer. Head pointer indicates the next entry in the event queue to be processed by the driver and is updated by the driver after processing is done. The controller uses the tail pointer as the next MSI data insertion point. The controller ensures MSI data is flushed to host memory before updating the tail pointer and then triggering the interrupt. MSI IRQ affinity is supported by evenly distributing the interrupts to each CPU core. MSI vector is moved from one GIC interrupt to another in order to steer to the target CPU. Therefore, the actual number of supported MSI vectors is: M * 64 / N where M denotes the number of GIC interrupts (event queues), and N denotes the number of CPU cores. This iProc event queue-based MSI support should not be used with newer platforms with integrated MSI support in the GIC (e.g., giv2m or gicv3-its). [bhelgaas: fold in Kconfig fixes from Arnd Bergmann <arnd@arndb.de>] Signed-off-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Anup Patel <anup.patel@broadcom.com> Reviewed-by: Vikram Prakash <vikramp@broadcom.com> Reviewed-by: Scott Branden <sbranden@broadcom.com> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
* PCI: iproc: Free resource list after registrationHauke Mehrtens2015-05-281-4/+4
| | | | | | | | | | | The resource list is only used in the setup process and was never freed. pci_add_resource() allocates a memory area to store the list item. Fix the memory leak. Tested-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ray Jui <rjui@broadcom.com>
* PCI: iproc: Directly add PCI resourcesHauke Mehrtens2015-05-281-3/+1
| | | | | | | | | | | The struct iproc_pcie.resources member was pointing to a stack variable and is invalid after the registration function returned. Remove this pointer and add a parameter to the function. Tested-by: Ray Jui <rjui@broadcom.com> Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Ray Jui <rjui@broadcom.com>
* PCI: iproc: Add BCMA PCIe driverHauke Mehrtens2015-05-201-0/+112
This driver adds support for the PCIe 2.0 controller found on the BCMA bus. This controller can be found on (mostly) all Broadcom BCM470X / BCM5301X ARM SoCs. The driver found in the Broadcom SDK does some more stuff, like setting up some DMA memory areas, chaining MPS and MRRS to 512 and also some PHY changes like "improving" the PCIe jitter and doing some special initialization for the 3rd PCIe port. This was tested on a bcm4708 board with 2 PCIe ports and wireless cards connected to them. PCI_DOMAINS is needed by this driver, because normally there is more than one PCIe controller and without PCI_DOMAINS only the first controller gets registered. This controller gets 6 IRQs; the last one is trigged by all IRQ events. [bhelgaas: fix "GPLv2" MODULE_LICENSE typo] Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Rafał Miłecki <zajec5@gmail.com> Acked-by: Ray Jui <rjui@broadcom.com.com>