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path: root/drivers/pci/pcie/portdrv_acpi.c (follow)
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* PCI/portdrv: Remove unused pcie_port_acpi_setup()Bjorn Helgaas2018-05-031-57/+0
| | | | | | | | | 02bfeb484230 ("PCI/portdrv: Simplify PCIe feature permission checking") removed the only call of pcie_port_acpi_setup() and removed portdrv_acpi.o from the Makefile, but I forgot to remove pcie_port_acpi_setup() itself. Remove pcie_port_acpi_setup() and the drivers/pci/pcie/portdrv_acpi.c file. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI/DPC: Do not enable DPC if AER control is not allowed by the BIOSMika Westerberg2018-03-311-2/+2
| | | | | | | | | | | | | | | | | Commit eed85ff4c0da ("PCI/DPC: Enable DPC only if AER is available") made DPC control dependent whether AER is enabled in the OS. However, it does not take into account situations where BIOS has not given OS control of AER: acpi PNP0A08:00: _OSC: OS supports [ExtendedConfig ASPM ClockPM Segments MSI] acpi PNP0A08:00: _OSC: platform does not support [AER] acpi PNP0A08:00: _OSC: OS now controls [PCIeHotplug PME PCIeCapability] I think here it is better not to enable DPC even if the capability is available because then it would be against what "Determination of DPC Control" note in PCIe 4.0 sec 6.1.10 recommends. Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
* PCI/portdrv: Remove unused PCIE_PORT_SERVICE_VCBjorn Helgaas2018-03-311-1/+1
| | | | | | | | | | | | | | | | | | | | No driver registers for PCIE_PORT_SERVICE_VC, so remove it. This removes the VC "service" files from /sys/bus/pci_express/devices, e.g., 0000:07:00.0:pcie108, 0000:08:04.0:pcie208 (all the files that contained "8" as the last digit of the "pcieXXX" part). The port driver created these files for PCIe port devices that have a VC Capability. Since this reduces PCIE_PORT_DEVICE_MAXSERVICES and moves DPC down into the spot where VC used to be, the DPC sysfs files will now be named "pcieXX8". I don't think there's anything useful userspace can do with those files, so I hope nobody cares about these filenames. There is no VC driver that calls pcie_port_service_register(), so there never was a /sys/bus/pci_express/drivers/vc directory. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
* PCI/portdrv: Merge pcieport_if.h into portdrv.hBjorn Helgaas2018-03-091-1/+0
| | | | | | | | | | | | | | pcieport_if.h contained the interfaces to register port service driver, e.g., pcie_port_service_register(). portdrv.h contained internal data structures of the port driver. I don't think it's worth keeping those files separate, since both headers and their users are all inside the PCI core. Merge pcieport_if.h directly in drivers/pci/pcie/portdrv.h and update the users to include that instead. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de>
* PCI/portdrv: Move pcieport_if.h to drivers/pci/pcie/Frederick Lawler2018-02-231-1/+1
| | | | | | | | | | Move pcieport_if.h from include/linux to drivers/pci/pcie/pcieport_if.h because the interfaces there are only used by the PCI core. Replace all uses of #include<linux/pcieport_if.h> with relative paths to the new file location, e.g., #include "../pcieport_if.h" Signed-off-by: Frederick Lawler <fred@fredlawl.com> Signed-off-by: Bjorn Helgaas <helgaas@kernel.org>
* PCI: Add SPDX GPL-2.0 to replace GPL v2 boilerplateBjorn Helgaas2018-01-281-4/+1
| | | | | | | | | | | Add SPDX GPL-2.0 to all PCI files that specified the GPL version 2 license. Remove the boilerplate GPL version 2 language, relying on the assertion in b24413180f56 ("License cleanup: add SPDX GPL-2.0 license identifier to files with no license") that the SPDX identifier may be used instead of the full boilerplate text. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
*-. Merge branches 'pci/dpc', 'pci/resource' and 'pci/thunderbolt' into nextBjorn Helgaas2016-05-031-1/+1
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/dpc: PCI: Add Downstream Port Containment driver PCI: Add Downstream Port Containment portdrv service type PCI: Widen portdrv service type from 4 bits to 8 bits * pci/resource: alpha/PCI: Call iomem_is_exclusive() for IORESOURCE_MEM, but not IORESOURCE_IO PCI: Supply CPU physical address (not bus address) to iomem_is_exclusive() * pci/thunderbolt: thunderbolt: Fix double free of drom buffer
| * | PCI: Add Downstream Port Containment portdrv service typeKeith Busch2016-05-031-1/+1
| |/ | | | | | | | | | | | | | | Add the Downstream Port Containment (PCIE_PORT_SERVICE_DPC) portdrv service type, available if the device has the DPC extended capability. [bhelgaas: split to separate patch, changelog] Signed-off-by: Keith Busch <keith.busch@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI: Remove return values from pcie_port_platform_notify() and relativesJon Derrick2016-04-081-6/+4
| | | | | | | | | | | | | | | | Now that pcie_port_acpi_setup() always returns 0, make it and its callers void functions and stop checking the return values. [bhelgaas: changelog] Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* | PCI/ACPI: Allow all PCIe services on non-ACPI host bridgesJon Derrick2016-04-081-2/+2
|/ | | | | | | | | | | | | | | | | | | | Host bridges we discover via ACPI, i.e., PNP0A03 and PNP0A08 devices, may have an _OSC method by which the OS can ask the platform for control of PCIe features like native hotplug, power management events, AER, etc. Previously, if we found a bridge without an ACPI device, we assumed we did not have permission to use any of these PCIe features. That seems unreasonably restrictive. If we find no ACPI device, assume we can take control of all PCIe features. The Intel Volume Management Device (VMD) is one such bridge with no ACPI device. Prior to this change, users had to boot with "pcie_ports=native" to get hotplug and other services to work below the VMD Root Port. [bhelgaas: changelog] Suggested-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Jon Derrick <jonathan.derrick@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI: Fix missing prototype for pcie_port_acpi_setup()Andy Shevchenko2013-04-121-0/+1
| | | | | | | | This fixes a "no previous prototype" warning for pcie_port_acpi_setup() found via "make W=1". [bhelgaas: changelog] Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* PCI/ACPI: Request _OSC control once for each root bridge (v3)Rafael J. Wysocki2011-01-141-19/+4
| | | | | | | | | | | | | | Move the evaluation of acpi_pci_osc_control_set() (to request control of PCI Express native features) into acpi_pci_root_add() to avoid calling it many times for the same root complex with the same arguments. Additionally, check if all of the requisite _OSC support bits are set before calling acpi_pci_osc_control_set() for a given root complex. References: https://bugzilla.kernel.org/show_bug.cgi?id=20232 Reported-by: Ozan Caglayan <ozan@pardus.org.tr> Tested-by: Ozan Caglayan <ozan@pardus.org.tr> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI/PCIe/AER: Disable native AER service if BIOS has precedenceRafael J. Wysocki2010-10-151-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There is a design issue related to PCIe AER and _OSC that the BIOS may be asked to grant control of the AER service even if some Hardware Error Source Table (HEST) entries contain information meaning that the BIOS really should control it. Namely, pcie_port_acpi_setup() calls pcie_aer_get_firmware_first() that determines whether or not the AER service should be controlled by the BIOS on the basis of the HEST information for the given PCIe port. The BIOS is asked to grant control of the AER service for a PCIe Root Complex if pcie_aer_get_firmware_first() returns 'false' for at least one root port in that complex, even if all of the other root ports' HEST entries have the FIRMWARE_FIRST flag set (and none of them has the GLOBAL flag set). However, if the AER service is controlled by the kernel, that may interfere with the BIOS' handling of the error sources having the FIRMWARE_FIRST flag. Moreover, there may be PCIe endpoints that have the FIRMWARE_FIRST flag set in HEST and are attached to the root ports in question, in which case it also may be unsafe to ask the BIOS for control of the AER service. For this reason, introduce a function checking if there's at least one PCIe-related HEST entry with the FIRMWARE_FIRST flag set and disable the native AER service altogether if this function returns 'true'. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: PCIe: Ask BIOS for control of all native services at onceRafael J. Wysocki2010-08-241-0/+77
After commit 852972acff8f10f3a15679be2059bb94916cba5d (ACPI: Disable ASPM if the platform won't provide _OSC control for PCIe) control of the PCIe Capability Structure is unconditionally requested by acpi_pci_root_add(), which in principle may cause problems to happen in two ways. First, the BIOS may refuse to give control of the PCIe Capability Structure if it is not asked for any of the _OSC features depending on it at the same time. Second, the BIOS may assume that control of the _OSC features depending on the PCIe Capability Structure will be requested in the future and may behave incorrectly if that doesn't happen. For this reason, control of the PCIe Capability Structure should always be requested along with control of any other _OSC features that may depend on it (ie. PCIe native PME, PCIe native hot-plug, PCIe AER). Rework the PCIe port driver so that (1) it checks which native PCIe port services can be enabled, according to the BIOS, and (2) it requests control of all these services simultaneously. In particular, this causes pcie_portdrv_probe() to fail if the BIOS refuses to grant control of the PCIe Capability Structure, which means that no native PCIe port services can be enabled for the PCIe Root Complex the given port belongs to. If that happens, ASPM is disabled to avoid problems with mishandling it by the part of the PCIe hierarchy for which control of the PCIe Capability Structure has not been received. Make it possible to override this behavior using 'pcie_ports=native' (use the PCIe native services regardless of the BIOS response to the control request), or 'pcie_ports=compat' (do not use the PCIe native services at all). Accordingly, rework the existing PCIe port service drivers so that they don't request control of the services directly. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>