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* PCI: Add Kconfig option to disable deprecated pci_find_* APIJeff Garzik2007-11-053-3/+23
| | | | | | Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI Hotplug: cpqhp_pushbutton_thread(): remove a pointless if() checkAdrian Bunk2007-11-051-9/+7
| | | | | | | | | | | | The Coverity checker spotted that we'd have already oops'ed if "ctrl" was NULL. Additionally, "func" had just been checked for not being NULL. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: make pci_match_device() staticAdrian Bunk2007-11-051-3/+2
| | | | | | | | pci_match_device() no longer has any other users. Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: Remove 3 incorrect MSI quirks.David Miller2007-11-051-3/+0
| | | | | | | | | | | | | | | | | | | | | Now that we have dealt with the real issue, in that some ATI SATA and USB controllers needed the INTX_DISABLE quirk, we can remove these AMD chipset global MSI disabling quirks. This reverts three changesets: 4be8f906435a6af241821ab5b94b2b12cb7d57d8 (PCI: disable MSI on RS690) aea6a433f50cd89b9cbd10850fd0b32f961f9883 (PCI: disable MSI on RD580) f122392f679ebed39db08074f935d770504623eb (PCI: disable MSI on RX790) This is based upon testing and feedback from Shane Huang <Shane.Huang@amd.com>. Cc: Shane Huang <Shane.Huang@amd.com> Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: Add MSI INTX_DISABLE quirks for ATI SB700/800 SATA and IXP SB400 USBDavid Miller2007-11-051-0/+20
| | | | | | | Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: Add quirk for devices which disable MSI when INTX_DISABLE is set.David Miller2007-11-052-6/+36
| | | | | | | | | | | | | | | | | | A reasonably common problem with some devices is that they will disable MSI generation when the INTX_DISABLE bit is set in the PCI_COMMAND register. Quirk this explicitly, guarding the pci_intx() calls in msi.c with this quirk indication. The first entries for this quirk are for 5714 and 5780 Tigon3 chips, and thus we can remove the workaround code from the tg3.c driver. Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Michael Chan <mchan@broadcom.com> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: Add MSI quirk for ServerWorks HT1000 PCIX bridge.David Miller2007-11-051-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This is the fix for the following problem: https://bugzilla.redhat.com/show_bug.cgi?id=227657 The bnx2 device 5706 complains about MSI not working behind a ServerWorks HT1000 PCIX bridge. An earlier commit to fix the problem: e3008dedff4bdc96a5f67224cd3d8d12237082a0: "PCI: disable MSI by default on systems with Serverworks HT1000 chips" was not entirely correct, and has been reverted. MSI does not work on the PCIX bus because the BIOS did not set the HT_MSI_FLAGS_ENABLE bit in the HyperTransport MSI capability on the bridge. We use the existing quirk_msi_ht_cap() to detect the problem and disable MSI in all buses behind it. Signed-off-by: Michael Chan <mchan@broadcom.com> Cc: Anantha Subramanyam <ananth@broadcom.com> Cc: Naren Sankar <nsankar@broadcom.com> Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* PCI: Revert "PCI: disable MSI by default on systems with Serverworks HT1000 ↵David Miller2007-11-051-1/+0
| | | | | | | | | | | | | | chips" This reverts commit e3008dedff4bdc96a5f67224cd3d8d12237082a0. The real bug was an INTX issue in the tg3 ethernet chip, and cured by commit c129d962a66c76964954a98b38586ada82cf9381 Signed-off-by: David S. Miller <davem@davemloft.net> Acked-by: Jeff Garzik <jgarzik@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
* intel-iommu: Fix array overflowTakashi Iwai2007-10-301-2/+2
| | | | | | | | | | | | | | | Fix possible array overflow: drivers/pci/intel-iommu.c: In function ¡dmar_get_fault_reason¢: drivers/pci/intel-iommu.c:753: warning: array subscript is above array bounds drivers/pci/intel-iommu.c: In function ¡iommu_page_fault¢: drivers/pci/intel-iommu.c:753: warning: array subscript is above array bounds Signed-off-by: Takashi Iwai <tiwai@suse.de> Cc: Mark Gross <mgross@linux.intel.com> Acked-by: "Keshavamurthy, Anil S" <anil.s.keshavamurthy@intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* x86 gart: rename iommu.h to gart.hJoerg Roedel2007-10-301-1/+1
| | | | | | | | | | | This patch renames the include file asm-x86/iommu.h to asm-x86/gart.h to make clear to which IOMMU implementation it belongs. The patch also adds "GART" to the Kconfig line. Signed-off-by: Joerg Roedel <joerg.roedel@amd.com> Acked-by: Muli Ben-Yehuda <muli@il.ibm.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* intel-iommu fixesAl Viro2007-10-292-5/+4
| | | | | | | | | | - off by one in dmar_get_fault_reason() (maximal index in array is ARRAY_SIZE()-1, not ARRAY_SIZE()) - NULL noise removal - __iomem annotation fix Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* jmicron: update quirk for JMB361/3/5/6Tejun Heo2007-10-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | Set bits 0, 4, 5 and 7 of PCI configuration register 0x40 in the quirk. This has the following effects and is recommended by the vendor. * Force enable of IDE channels (used to be left alone as BIOS configured) * Change initial phase behavior of PIO cycle such that the host pulls down the bus instead of tristating it. Vendor recommends this setting. The above settings are better for the current generation of controllers and needed for the upcoming next generation. Tested on JMB363. Signed-off-by: Tejun Heo <htejun@gmail.com> Cc: Ethan Hsiao <ethanhsiao@jmicron.com> Signed-off-by: Jeff Garzik <jeff@garzik.org>
* intel-iommu: fix sg_page()FUJITA Tomonori2007-10-231-2/+2
| | | | | Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Signed-off-by: Jens Axboe <jens.axboe@oracle.com>
* intel-iommu sg chaining supportFUJITA Tomonori2007-10-221-17/+17
| | | | | | | | | | | x86_64 defines ARCH_HAS_SG_CHAIN. So if IOMMU implementations don't support sg chaining, we will get data corruption. Signed-off-by: FUJITA Tomonori <fujita.tomonori@lab.ntt.co.jp> Acked-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Jens Axboe <jens.axboe@oracle.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* intel-iommu: fix for IOMMU early crashKeshavamurthy, Anil S2007-10-221-11/+11
| | | | | | | | | | | | | | | pci_dev's->sysdata is highly overloaded and currently IOMMU is broken due to IOMMU code depending on this field. This patch introduces new field in pci_dev's dev.archdata struct to hold IOMMU specific per device IOMMU private data. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Cc: Greg KH <greg@kroah.com> Cc: Jeff Garzik <jeff@garzik.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* intel-iommu: optimize sg map/unmap callsKeshavamurthy, Anil S2007-10-223-160/+231
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds PageSelectiveInvalidation support replacing existing DomainSelectiveInvalidation for intel_{map/unmap}_sg() calls and also enables to mapping one big contiguous DMA virtual address which is mapped to discontiguous physical address for SG map/unmap calls. "Doamin selective invalidations" wipes out the IOMMU address translation cache based on domain ID where as "Page selective invalidations" wipes out the IOMMU address translation cache for that address mask range which is more cache friendly when compared to Domain selective invalidations. Here is how it is done. 1) changes to iova.c alloc_iova() now takes a bool size_aligned argument, which when when set, returns the io virtual address that is naturally aligned to 2 ^ x, where x is the order of the size requested. Returning this io vitual address which is naturally aligned helps iommu to do the "page selective invalidations" which is IOMMU cache friendly over "domain selective invalidations". 2) Changes to driver/pci/intel-iommu.c Clean up intel_{map/unmap}_{single/sg} () calls so that s/g map/unamp calls is no more dependent on intel_{map/unmap}_single() intel_map_sg() now computes the total DMA virtual address required and allocates the size aligned total DMA virtual address and maps the discontiguous physical address to the allocated contiguous DMA virtual address. In the intel_unmap_sg() case since the DMA virtual address is contiguous and size_aligned, PageSelectiveInvalidation is used replacing earlier DomainSelectiveInvalidations. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Greg KH <greg@kroah.com> Cc: Ashok Raj <ashok.raj@intel.com> Cc: Suresh B <suresh.b.siddha@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Arjan van de Ven <arjan@infradead.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: Iommu floppy workaroundKeshavamurthy, Anil S2007-10-221-0/+27
| | | | | | | | | | | | | | | | | | | | | | | | This config option (DMAR_FLPY_WA) sets up 1:1 mapping for the floppy device so that the floppy device which does not use DMA api's will continue to work. Once the floppy driver starts using DMA api's this config option can be turn off or this patch can be yanked out of kernel at that time. [akpm@linux-foundation.org: cleanups, rename things, build fix] [jengelh@computergmbh.de: Kconfig fixes] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Jan Engelhardt <jengelh@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: Iommu Gfx workaroundKeshavamurthy, Anil S2007-10-222-0/+40
| | | | | | | | | | | | | | | | | | | | When we fix all the opensource gfx drivers to use the DMA api's, at that time we can yank this config options out. [jengelh@computergmbh.de: Kconfig fixes] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Jan Engelhardt <jengelh@gmx.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: DMAR fault handling supportKeshavamurthy, Anil S2007-10-221-0/+194
| | | | | | | | | | | | | | | | | | | | | MSI interrupt handler registrations and fault handling support for Intel-IOMMU hadrware. This patch enables the MSI interrupts for the DMA remapping units and in the interrupt handler read the fault cause and outputs the same on to the console. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: Intel iommu cmdline option - forcedacKeshavamurthy, Anil S2007-10-221-1/+6
| | | | | | | | | | | | | | | | | | | Introduce intel_iommu=forcedac commandline option. This option is helpful to verify the pci device capability of handling physical dma'able address greater than 4G. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: Avoid memory allocation failures in dma map api callsKeshavamurthy, Anil S2007-10-221-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Intel IOMMU driver needs memory during DMA map calls to setup its internal page tables and for other data structures. As we all know that these DMA map calls are mostly called in the interrupt context or with the spinlock held by the upper level drivers(network/storage drivers), so in order to avoid any memory allocation failure due to low memory issues, this patch makes memory allocation by temporarily setting PF_MEMALLOC flags for the current task before making memory allocation calls. We evaluated mempools as a backup when kmem_cache_alloc() fails and found that mempools are really not useful here because 1) We don't know for sure how much to reserve in advance 2) And mempools are not useful for GFP_ATOMIC case (as we call memory alloc functions with GFP_ATOMIC) (akpm: point 2 is wrong...) With PF_MEMALLOC flag set in the current->flags, the VM subsystem avoids any watermark checks before allocating memory thus guarantee'ing the memory till the last free page. Further, looking at the code in mm/page_alloc.c in __alloc_pages() function, looks like this flag is useful only in the non-interrupt context. If we are in the interrupt context and memory allocation in IOMMU driver fails for some reason, then the DMA map api's will return failure and it is up to the higher level drivers to retry. Suppose, if upper level driver programs the controller with the buggy DMA virtual address, the IOMMU will block that DMA transaction when that happens thus preventing any corruption to main memory. So far in our test scenario, we were unable to create any memory allocation failure inside dma map api calls. Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: Intel IOMMU driverKeshavamurthy, Anil S2007-10-223-1/+2276
| | | | | | | | | | | | | | | | | | | | | | | | | | Actual intel IOMMU driver. Hardware spec can be found at: http://www.intel.com/technology/virtualization This driver sets X86_64 'dma_ops', so hook into standard DMA APIs. In this way, PCI driver will get virtual DMA address. This change is transparent to PCI drivers. [akpm@linux-foundation.org: remove unneeded cast] [akpm@linux-foundation.org: build fix] [bunk@stusta.de: fix duplicate CONFIG_DMAR Makefile line] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Adrian Bunk <bunk@stusta.de> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: IOVA allocation and management routinesKeshavamurthy, Anil S2007-10-222-0/+419
| | | | | | | | | | | | | | | | | | | | | | | | | | | This code implements a generic IOVA allocation and management. As per Dave's suggestion we are now allocating IO virtual address from Higher DMA limit address rather than lower end address and this eliminated the need to preserve the IO virtual address for multiple devices sharing the same domain virtual address. Also this code uses red black trees to store the allocated and reserved iova nodes. This showed a good performance improvements over previous linear linked list. [akpm@linux-foundation.org: remove inlines] [akpm@linux-foundation.org: coding style fixes] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: PCI generic helper functionKeshavamurthy, Anil S2007-10-223-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | When devices are under a p2p bridge, upstream transactions get replaced by the device id of the bridge as it owns the PCIE transaction. Hence its necessary to setup translations on behalf of the bridge as well. Due to this limitation all devices under a p2p share the same domain in a DMAR. We just cache the type of device, if its a native PCIe device or not for later use. [akpm@linux-foundation.org: BUG_ON -> WARN_ON+recover] Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Intel IOMMU: DMAR detection and parsing logicKeshavamurthy, Anil S2007-10-222-0/+332
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch supports the upcomming Intel IOMMU hardware a.k.a. Intel(R) Virtualization Technology for Directed I/O Architecture and the hardware spec for the same can be found here http://www.intel.com/technology/virtualization/index.htm FAQ! (questions from akpm, answers from ak) > So... what's all this code for? > > I assume that the intent here is to speed things up under Xen, etc? Yes in some cases, but not this code. That would be the Xen version of this code that could potentially assign whole devices to guests. I expect this to be only useful in some special cases though because most hardware is not virtualizable and you typically want an own instance for each guest. Ok at some point KVM might implement this too; i likely would use this code for this. > Do we > have any benchmark results to help us to decide whether a merge would be > justified? The main advantage for doing it in the normal kernel is not performance, but more safety. Broken devices won't be able to corrupt memory by doing random DMA. Unfortunately that doesn't work for graphics yet, for that need user space interfaces for the X server are needed. There are some potential performance benefits too: - When you have a device that cannot address the complete address range an IOMMU can remap its memory instead of bounce buffering. Remapping is likely cheaper than copying. - The IOMMU can merge sg lists into a single virtual block. This could potentially speed up SG IO when the device is slow walking SG lists. [I long ago benchmarked 5% on some block benchmark with an old MPT Fusion; but it probably depends a lot on the HBA] And you get better driver debugging because unexpected memory accesses from the devices will cause a trappable event. > > Does it slow anything down? It adds more overhead to each IO so yes. This patch: Add support for early detection and parsing of DMAR's (DMA Remapping) reported to OS via ACPI tables. DMA remapping(DMAR) devices support enables independent address translations for Direct Memory Access(DMA) from Devices. These DMA remapping devices are reported via ACPI tables and includes pci device scope covered by these DMA remapping device. For detailed info on the specification of "Intel(R) Virtualization Technology for Directed I/O Architecture" please see http://www.intel.com/technology/virtualization/index.htm Signed-off-by: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com> Cc: Andi Kleen <ak@suse.de> Cc: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Muli Ben-Yehuda <muli@il.ibm.com> Cc: "Siddha, Suresh B" <suresh.b.siddha@intel.com> Cc: Arjan van de Ven <arjan@infradead.org> Cc: Ashok Raj <ashok.raj@intel.com> Cc: "David S. Miller" <davem@davemloft.net> Cc: Christoph Lameter <clameter@sgi.com> Cc: Greg KH <greg@kroah.com> Cc: Len Brown <lenb@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Get rid of unused variable warning in drivers/pci/hotplug/pci_hotplug_core.cLinus Torvalds2007-10-151-2/+0
| | | | | | | Commit 5a7ad7f044941316dc98eda2a087a12a7a50649d removed all uses of 'retval', but didn't remove the variable itself. Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* more trivial signedness fixes in driversAl Viro2007-10-141-1/+1
| | | | | Signed-off-by: Al Viro <viro@zeniv.linux.org.uk> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds2007-10-1317-352/+209
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * master.kernel.org:/pub/scm/linux/kernel/git/gregkh/pci-2.6: (37 commits) PCI: merge almost all of pci_32.h and pci_64.h together PCI: X86: Introduce and enable PCI domain support PCI: Add 'nodomains' boot option, and pci_domains_supported global PCI: modify PCI bridge control ISA flag for clarity PCI: use _CRS for PCI resource allocation PCI: avoid P2P prefetch window for expansion ROMs PCI: skip ISA ioresource alignment on some systems PCI: remove transparent bridge sizing pci: write file size to inode on proc bus file write pci: use size stored in proc_dir_entry for proc bus files pci: implement "pci=noaer" PCI: fix IDE legacy mode resources MSI: Use correct data offset for 32-bit MSI in read_msi_msg() PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID code PCI: i386: Compaq EVO N800c needs PCI bus renumbering PCI: Remove no longer correct documentation regarding MSI vector assignment PCI: re-enable onboard sound on "MSI K8T Neo2-FIR" PCI: quirk_vt82c586_acpi: Omit reading PCI revision ID PCI: quirk amd_8131_mmrbc: Omit reading pci revision ID cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for read ...
| * PCI: Add 'nodomains' boot option, and pci_domains_supported globalJeff Garzik2007-10-131-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | * Introduce pci_domains_supported global, hardcoded to zero if !CONFIG_PCI_DOMAINS. * Introduce 'nodomains' boot option, which clears pci_domains_supported on platforms that enable it by default (x86, x86-64, and others when they are converted to use this). Signed-off-by: Jeff Garzik <jgarzik@redhat.com> Cc: Andi Kleen <ak@suse.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: modify PCI bridge control ISA flag for clarityGary Hade2007-10-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modify PCI Bridge Control ISA flag for clarity This patch changes PCI_BRIDGE_CTL_NO_ISA to PCI_BRIDGE_CTL_ISA and modifies it's clarifying comment and locations where used. The change reduces the chance of future confusion since it makes the set/unset meaning of the bit the same in both the bridge control register and bridge_ctl field of the pci_bus struct. Signed-off-by: Gary Hade <garyhade@us.ibm.com> Acked-by: Linas Vepstas <linas@austin.ibm.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: avoid P2P prefetch window for expansion ROMsGary Hade2007-10-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Avoid creating P2P prefetch window for expansion ROMs Because of the future possibility that P2P prefetch windows will contain address ranges above 4GB some BIOSes are providing space in the P2P non-prefetch windows for expansion ROMs. This is due to expansion ROM BAR 32-bit limitation. When expansion ROM BARs without BIOS assigned address(es) are currently found behind a P2P bridge, the kernel attempts to create a P2P prefetch window for them even though space for them has already been provided in the non-prefetch window. _CRS on some systems with certain resource conservation conscious BIOSes may not provide the extra 1MB or more memory resource needed for the expansion ROM motivated prefetch window causing resource allocation errors. This change corrects the problem by removing IORESOURCE_PREFETCH from the expansion ROM flags initialization. It also removes IORESOURCE_CACHEABLE which seems inappropriate if only non-cacheable memory is available. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: skip ISA ioresource alignment on some systemsGary Hade2007-10-131-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Skip ISA ioresource alignment on some systems To conserve limited PCI i/o resource on some IBM multi-node systems, the BIOS allocates (via _CRS) and expects the kernel to use addresses in ranges currently excluded by pcibios_align_resource() [i386/pci/i386.c]. This change allows the kernel to use the currently excluded address ranges on the IBM x3800, x3850, and x3950. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: remove transparent bridge sizingGary Hade2007-10-131-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove transparent bridge sizing. Due to code in pci_read_bridge_bases() [drivers/pci/probe.c] the child bus of a transparent bridge already has access to the parent bus resources so transparent bridge sizing appears unnecessary. The bridge sizing includes alignment and granularity adjustments that can cause significantly more memory to be reserved from the parant bus than required by devices on the child bus and allotted by _CRS. Signed-off-by: Gary Hade <gary.hade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: write file size to inode on proc bus file writeDavid Rientjes2007-10-131-1/+2
| | | | | | | | | | | | | | | | | | | | | | When a /proc/bus/pci file is written to, the size of that PCI device's configuration space must be written to the inode. Otherwise, it is possible for the file to specify a size of 0 on stat if a task is holding the same file open. Signed-off-by: David Rientjes <rientjes@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: use size stored in proc_dir_entry for proc bus filesDavid Rientjes2007-10-131-2/+2
| | | | | | | | | | | | | | | | | | | | On pci_proc_attach_device(), the size of the PCI configuration space is stored in the proc_dir_entry as the size of the file. Thus, the procfs interface to PCI devices should use it instead of the device directly. Signed-off-by: David Rientjes <rientjes@google.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: implement "pci=noaer"Randy Dunlap2007-10-133-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | For cases in which CONFIG_PCIEAER=y (such as distro kernels), allow users to disable PCIE Advanced Error Reporting by using "pci=noaer" on the kernel command line. This can be used to work around hardware or (kernel) software problems. Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: fix IDE legacy mode resourcesYoichi Yuasa2007-10-131-12/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I got the following error on MIPS Cobalt. PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 0 (errno=-16) PCI: Unable to reserve I/O region #3:8@f0000170 for device 0000:00:09.1 pata_via 0000:00:09.1: failed to request/iomap BARs for port 1 (errno=-16) pata_via 0000:00:09.1: no available native port The legacy mode IDE resources set the following order. pci_setup_device() Legacy mode ATA controllers have fixed addresses. IDE resources: 0x1F0-0x1F7, 0x3F6, 0x170-0x177, 0x376 | V pcibios_fixup_bus() MIPS Cobalt PCI bus regions have the -0x10000000 offset from PCI resources. pcibios_fixup_bus() fix PCI bus regions. 0x1F0 - 0x10000000 = 0xF00001F0 | V ata_pci_init_one() PCI: Unable to reserve I/O region #1:8@f00001f0 for device 0000:00:09.1 In some architectures, PCI bus regions have the offset from PCI resources. For this reason, pci_setup_device() should set PCI bus regions to dev->resource[]. [akpm@linux-foundation.org: use struct initialiser] Signed-off-by: Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Cc: Greg KH <greg@kroah.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Ralf Baechle <ralf@linux-mips.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * MSI: Use correct data offset for 32-bit MSI in read_msi_msg()Roland Dreier2007-10-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | While reading the MSI code trying to find a reason why MSI wouldn't work for devices that have a 32-bit MSI address capability, I noticed that read_msi_msg() seems to read the message data from the wrong offset in this case. Signed-off-by: Roland Dreier <roland@digitalvampire.org> Acked-by: Eric W. Biederman <ebiederm@xmission.com> Cc: stable <stable@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Fix incorrect argument order to list_add_tail() in PCI dynamic ID codeMichael Ellerman2007-10-131-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code for dynamically assigning new ids to PCI drivers, store_new_id(), calls list_add_tail() with the list head and new node arguments in reversed order. The result is that every new id written essentially overwrites the previous list of ids. Caught with the help of Rusty's "horribly bad" list_node patch: http://lkml.org/lkml/2007/6/10/10 Signed-off-by: Michael Ellerman <michael@ellerman.id.au> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: re-enable onboard sound on "MSI K8T Neo2-FIR"Johannes Goecke2007-10-131-32/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On the "MSI K8T Neo2-FIR" board the BIOS disables the onboard soundcard, if a second PCI soundcard is present. This patch sets the korrect register bit to enable the onboard sound. Removed old code in /drivers/pci/quirks.c that only checks for the PCI-ID and fires on any Board with VIA 8237. New code in /arch/i386/pci/fixup.c checks the DMI-tables and only runs on the specific board. Signed-off-by: Johannes Goecke <goecke@upb.de> Acked-by: Jean Delvare <khali@linux-fr.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: quirk_vt82c586_acpi: Omit reading PCI revision IDAuke Kok2007-10-131-3/+1
| | | | | | | | | | | | Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: quirk amd_8131_mmrbc: Omit reading pci revision IDAuke Kok2007-10-131-5/+2
| | | | | | | | | | | | | | Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Peter Oruba <peter.oruba@amd.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * cpqphp: Use PCI_CLASS_REVISION instead of PCI_REVISION_ID for readAuke Kok2007-10-131-1/+1
| | | | | | | | | | | | | | | | | | | | | | While PCI_CLASS_REVISION and PCI_REVISION_ID are identical, the code here discards the revision content and is only interested in the class number. Signed-off-by: Auke Kok <auke-jan.h.kok@intel.com> Cc: Krosten Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: hotplug: cpqphp: convert to kthread infrastructureChristoph Hellwig2007-10-131-48/+21
| | | | | | | | | | | | | | Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pci: hotplug: ibmphp: convert to kthreadKristen Carlson Accardi2007-10-131-45/+12
| | | | | | | | | | | | | | | | | | | | Convert ibmphp to new kthread api Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Cc: Christoph Hellwig <hch@lst.de> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: is_power_of_2 in drivers/pci/pci.cvignesh babu2007-10-131-2/+3
| | | | | | | | | | | | | | | | Replacing n & (n - 1) for power of 2 check by is_power_of_2(n) Signed-off-by: vignesh babu <vignesh.babu@wipro.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: minor cleanups for pciehp_hpc.cKenji Kaneshige2007-10-131-21/+26
| | | | | | | | | | | | | | | | | | | | Minor cleanups for pciehp_hpc.c. The 80 column rules, removing unnecessary lines, and so on. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace form pciehp_pci.cKenji Kaneshige2007-10-131-3/+3
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_pci.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace from pciehp_ctrl.cKenji Kaneshige2007-10-131-10/+10
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_ctrl.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * pciehp: remove trailing whitespace from pciehp_core.cKenji Kaneshige2007-10-131-10/+10
| | | | | | | | | | | | | | | | | | Remove trailing whitespaces from pciehp_core.c. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
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