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* Merge branch 'acpica' of ↵Linus Torvalds2010-03-011-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6 * 'acpica' of git://git.kernel.org/pub/scm/linux/kernel/git/lenb/linux-acpi-2.6: ACPI: replace acpi_integer by u64 ACPICA: Update version to 20100121. ACPICA: Remove unused uint32_struct type ACPICA: Disassembler: Remove obsolete "Integer64" field in parse object ACPICA: Remove obsolete ACPI_INTEGER (acpi_integer) type ACPICA: Predefined name repair: fix NULL package elements ACPICA: AcpiGetDevices: Eliminate unnecessary _STA calls ACPICA: Update all ACPICA copyrights and signons to 2010 ACPICA: Update for new gcc-4 warning options
| * ACPI: replace acpi_integer by u64Lin Ming2010-01-281-1/+1
| | | | | | | | | | | | | | | | acpi_integer is now obsolete and removed from the ACPICA code base, replaced by u64. Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
* | pci: don't reassign to ROM res if it is not going to be enabledYinghai Lu2010-03-011-2/+10
| | | | | | | | | | | | | | | | | | A ROM resource that doesn't fit should not cause us to try to re-assign all the bus resources. Nobody generally cares, and re-assigning is going to just cause way more troubles than it tries to solve. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | Merge branch 'x86-pci-for-linus' of ↵Linus Torvalds2010-02-281-1/+24
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip * 'x86-pci-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: x86: Enable NMI on all cpus on UV vgaarb: Add user selectability of the number of GPUS in a system vgaarb: Fix VGA arbiter to accept PCI domains other than 0 x86, uv: Update UV arch to target Legacy VGA I/O correctly. pci: Update pci_set_vga_state() to call arch functions
| * | pci: Update pci_set_vga_state() to call arch functionsMike Travis2010-02-051-1/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update pci_set_vga_state to call arch dependent functions to enable Legacy VGA I/O transactions to be redirected to correct target. [akpm@linux-foundation.org: make pci_register_set_vga_state() __init] Signed-off-by: Mike Travis <travis@sgi.com> LKML-Reference: <201002022238.o12McE1J018723@imap1.linux-foundation.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Robin Holt <holt@sgi.com> Cc: Jack Steiner <steiner@sgi.com> Cc: Ingo Molnar <mingo@elte.hu> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Cc: David Airlie <airlied@linux.ie> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
* | | PM: Allow PCI devices to suspend/resume asynchronouslyRafael J. Wysocki2010-02-263-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set power.async_suspend for all PCI devices and PCIe port services, so that they can be suspended and resumed in parallel with other devices they don't depend on in a known way (i.e. devices which are not their parents or children). This only affects the "regular" suspend and resume stages, which means in particular that the restoration of the PCI devices' standard configuration registers during resume will still be carried out synchronously (at the "early" resume stage). Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl>
* | | PCI: augment bus resource table with a listBjorn Helgaas2010-02-232-4/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously we used a table of size PCI_BUS_NUM_RESOURCES (16) for resources forwarded to a bus by its upstream bridge. We've increased this size several times when the table overflowed. But there's no good limit on the number of resources because host bridges and subtractive decode bridges can forward any number of ranges to their secondary buses. This patch reduces the table to only PCI_BRIDGE_RESOURCE_NUM (4) entries, which corresponds to the number of windows a PCI-to-PCI (3) or CardBus (4) bridge can positively decode. Any additional resources, e.g., PCI host bridge windows or subtractively-decoded regions, are kept in a list. I'd prefer a single list rather than this split table/list approach, but that requires simultaneous changes to every architecture. This approach only requires immediate changes where we set up (a) host bridges with more than four windows and (b) subtractive-decode P2P bridges, and we can incrementally change other architectures to use the list. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: add pci_bus_for_each_resource(), remove direct bus->resource[] refsBjorn Helgaas2010-02-234-17/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change; this converts loops that iterate from 0 to PCI_BUS_NUM_RESOURCES through pci_bus resource[] table to use the pci_bus_for_each_resource() iterator instead. This doesn't change the way resources are stored; it merely removes dependencies on the fact that they're in a table. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: read bridge windows before filling in subtractive decode resourcesBjorn Helgaas2010-02-231-5/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change; this fills in the bus subtractive decode resources after reading the bridge window information rather than before. Also, print out the subtractive decode resources as we already do for the positive decode windows. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: split up pci_read_bridge_bases()Bjorn Helgaas2010-02-231-15/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | No functional change; this breaks up pci_read_bridge_bases() into separate pieces for the I/O, memory, and prefetchable memory windows, similar to how Yinghai recently split up pci_setup_bridge() in 68e84ff3bdc. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCIe PME: use pci_pcie_cap()Kenji Kaneshige2010-02-231-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use pci_pcie_cap() instead of pci_find_capability() to get PCIe capability offset. This reduces redundant search in PCI configuration space. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI PM: Run-time callbacks for PCI bus typeRafael J. Wysocki2010-02-233-33/+171
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce run-time PM callbacks for the PCI bus type. Make the new callbacks work in analogy with the existing system sleep PM callbacks, so that the drivers already converted to struct dev_pm_ops can use their suspend and resume routines for run-time PM without modifications. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCIe PME: use pci_is_pcie()Kenji Kaneshige2010-02-231-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | Use pci_is_pcie() instead of looking at obsolete is_pcie field in struct pci_dev. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI / ACPI / PM: Platform support for PCI PME wake-upRafael J. Wysocki2010-02-233-0/+285
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Although the majority of PCI devices can generate PMEs that in principle may be used to wake up devices suspended at run time, platform support is generally necessary to convert PMEs into wake-up events that can be delivered to the kernel. If ACPI is used for this purpose, PME signals generated by a PCI device will trigger the ACPI GPE associated with the device to generate an ACPI wake-up event that we can set up a handler for, provided that everything is configured correctly. Unfortunately, the subset of PCI devices that have GPEs associated with them is quite limited. The devices without dedicated GPEs have to rely on the GPEs associated with other devices (in the majority of cases their upstream bridges and, possibly, the root bridge) to generate ACPI wake-up events in response to PME signals from them. Add ACPI platform support for PCI PME wake-up: o Add a framework making is possible to use ACPI system notify handlers for run-time PM. o Add new PCI platform callback ->run_wake() to struct pci_platform_pm_ops allowing us to enable/disable the platform to generate wake-up events for given device. Implemet this callback for the ACPI platform. o Define ACPI wake-up handlers for PCI devices and PCI root buses and make the PCI-ACPI binding code register wake-up notifiers for all PCI devices present in the ACPI tables. o Add function pci_dev_run_wake() which can be used by PCI drivers to check if given device is capable of generating wake-up events at run time. Developed in cooperation with Matthew Garrett <mjg@redhat.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI PM: Make it possible to force using INTx for PCIe PME signalingRafael J. Wysocki2010-02-234-3/+67
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently, some machines may have problems with PCI run-time power management if MSIs are used for the native PCIe PME signaling. In particular, on the MSI Wind U-100 PCIe PME interrupts are not generated by a PCIe root port after a resume from suspend to RAM, if the system wake-up was triggered by a PME from the device attached to this port. [It doesn't help to free the interrupt on suspend and request it back on resume, even if that is done along with disabling the MSI and re-enabling it, respectively.] However, if INTx interrupts are used for this purpose on the same machine, everything works just fine. For this reason, add a kernel command line switch allowing one to request that MSIs be not used for the native PCIe PME signaling, introduce a DMI table allowing us to blacklist machines that need this switch to be set by default and put the MSI Wind U-100 into this table. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI PM: PCIe PME root port service driverRafael J. Wysocki2010-02-236-0/+589
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCIe native PME detection mechanism is based on interrupts generated by root ports or event collectors every time a PCIe device sends a PME message upstream. Once a PME message has been sent by an endpoint device and received by its root port (or event collector in the case of root complex integrated endpoints), the Requester ID from the message header is registered in the root port's Root Status register. At the same time, the PME Status bit of the Root Status register is set to indicate that there's a PME to handle. If PCIe PME interrupt is enabled for the root port, it generates an interrupt once the PME Status has been set. After receiving the interrupt, the kernel can identify the PCIe device that generated the PME using the Requester ID from the root port's Root Status register. [For details, see PCI Express Base Specification, Rev. 2.0.] Implement a driver for the PCIe PME root port service working in accordance with the above description. Based on a patch from Shaohua Li <shaohua.li@intel.com>. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI PM: Add function for checking PME status of devicesRafael J. Wysocki2010-02-232-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add function pci_check_pme_status() that will check the PME status bit of given device and clear it along with the PME enable bit. It will be necessary for PCI run-time power management. Based on a patch from Shaohua Li <shaohua.li@intel.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: set PCI_PREF_RANGE_TYPE_64 in pci_bridge_check_rangesYinghai Lu2010-02-231-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | Make pci_bridge_check_ranges() store the PCI_PREF_RANGE_TYPE_64 in addition to IORESOURCE_MEM_64. Just like pci_read_bridge_bases(). Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: pciehp: second try to get big range for pcie devicesYinghai Lu2010-02-231-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | Handle the case where the slot bridge that doesn't get a pre-allocated resource big enough to handle its child resources.. For example pcie devices need 256M, but the bridge only gets 2M preallocated. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: pciehp: cleanup flow in pciehp_configure_deviceYinghai Lu2010-02-231-6/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move bus_size_bridges and assign resources out of pciehp_add_bridge() and do them all together, one time, including slot bridge, to avoid to calling assign resources several times when there are several bridges under the slot bridge. Using pci_assign_unassigned_bridge_resources. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: introduce pci_assign_unassigned_bridge_resourcesYinghai Lu2010-02-231-27/+89
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For use by pciehp. pci_setup_bridge() will not check enabled for the slot bridge, otherwise update res is not updated to bridge BAR. That is, bridge is already enabled for port service. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: update bridge resources to get more big ranges in PCI assign unssignedYinghai Lu2010-02-231-2/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | BIOS separates IO ranges between several IOHs, and on some slots, BIOS assigns resources to a bridge, but stops assigning resources to the device under that bridge, because the device needs a big resource. So: 1. allocate resources and record the failed device resources 2. clear the BIOS assigned resources of the parent bridge of failing device 3. go back and call pci assign unassigned 4. if it still fails, go up the tree, clear more bridges. and try again Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: don't shrink bridge resourcesYinghai Lu2010-02-231-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When clearing leaf bridge resources, trying to get a big enough one, we could shrink the bridge if there is no resource under it. Confirm against the old resource side to make sure we're increasing the allocation. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: reject mmio ranges starting at 0 on pci_bridge readYinghai Lu2010-02-231-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | We already track unassigned resources in struct resource, and this prevents us from overwriting resource flags and info in the unassigned case. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: add failed_list to pci_bus_assign_resourcesYinghai Lu2010-02-231-4/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | This allows us to track failed allocations for later re-trying with reallocation. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: add pci_bridge_release_resources and pci_bus_release_bridge_resourcesYinghai Lu2010-02-231-0/+82
| | | | | | | | | | | | | | | | | | | | | | | | | | | We use this in later patches to free resrouce ranges for reassignment in an effort to support a wider variety of PCI topologies. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Reviewed-by: Alex Chiang <achiang@hp.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI hotplug: check ioremap() return value in ibmphp_ebda.cAndrew Morton2010-02-231-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | check ioremap() return value. Cc: <stable@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI hotplug: fix ibmphp build errorRandy Dunlap2010-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add header file to fix build error: drivers/pci/hotplug/ibmphp_hpc.c:135: error: implicit declaration of function 'init_MUTEX' drivers/pci/hotplug/ibmphp_hpc.c:136: error: implicit declaration of function 'init_MUTEX_LOCKED' drivers/pci/hotplug/ibmphp_hpc.c:797: error: implicit declaration of function 'down' drivers/pci/hotplug/ibmphp_hpc.c:807: error: implicit declaration of function 'up' Signed-off-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Make pci_scan_slot more robustMatthew Wilcox2010-02-231-4/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Yinghai pointed out that the new pci_scan_slot() crashes when called on an ARI-capable slot that is empty. Fix this by exiting early from pci_scan_slot if there is no device in the slot. Also make next_ari_func() robust against devices not existing in case the ARI capability is corrupt. ARI also requires that the devices be listed in order, so if we find a function listed that is out of order, stop scanning to prevent loops. Signed-off-by: Matthew Wilcox <matthew@wil.cx> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: hotplug/cpcihp, fix pci device refcountingJiri Slaby2010-02-231-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stanse found an ommitted pci_dev_put on one error path in cpcihp_generic_init. The path is taken on !dev, but also when dev->hdr_type != PCI_HEADER_TYPE_BRIDGE. However it omits to pci_dev_put on the latter. As it is fine to pass NULL to pci_dev_put, put it in there uncoditionally. Signed-off-by: Jiri Slaby <jslaby@suse.cz> Cc: Scott Murray <scott@spiteful.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: push deprecated pci_find_device() function to last userTilman Schmidt2010-02-233-48/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ISDN4Linux HiSax driver family contains the last remaining users of the deprecated pci_find_device() function. This patch creates a private copy of that function in HiSax, and removes the now unused global function together with its controlling configuration option, CONFIG_PCI_LEGACY. Signed-off-by: Tilman Schmidt <tilman@imap.cc> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: don't dump resource when bus resource flags indicates unusedYinghai Lu2010-02-231-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | Don't print out resources without flags to avoid cluttering up the debug output. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: separate pci_setup_bridge to small functionsYinghai Lu2010-02-231-16/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | This is a good cleanup in itself, and makes it easier to modify specific resource types in later code. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Acked-by: Linus Torvalds <torvalds@linux-foundation.org> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI hotplug: ibmphp: read the length of ebda and map entire ebda regionChandru2010-02-231-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ibmphp driver currently maps only 1KB of ebda memory area into kernel address space during driver initialization. This causes kernel oops when the driver is modprobe'd and it accesses memory beyond 1KB within ebda segment. The first byte of ebda segment actually stores the length of the ebda region in Kilobytes. Hence make use of the length parameter and map the entire ebda region. Signed-off-by: Chandru Siddalingappa <chandru@linux.vnet.ibm.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI hotplug: fix memory leaksJiri Slaby2010-02-232-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Stanse found a cut&pasted memory leak in pciehp_queue_pushbutton_work and shpchp_queue_pushbutton_work. info is not freed/assigned on all paths. Fix that. Reviewed-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jiri Slaby <jslaby@suse.cz> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | resource/PCI: mark struct resource as constDominik Brodowski2010-02-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now that we return the new resource start position, there is no need to update "struct resource" inside the align function. Therefore, mark the struct resource as const. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | resource/PCI: align functions now return start of resourceDominik Brodowski2010-02-231-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As suggested by Linus, align functions should return the start of a resource, not void. An update of "res->start" is no longer necessary. Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Dominik Brodowski <linux@dominikbrodowski.net> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Clean up build for CONFIG_PCI_QUIRKS unsetRafael J. Wysocki2010-02-234-14/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, drivers/pci/quirks.c is built unconditionally, but if CONFIG_PCI_QUIRKS is unset, the only things actually built in this file are definitions of global variables and empty functions (due to the #ifdef CONFIG_PCI_QUIRKS embracing all of the code inside the file). This is not particularly nice and if someone overlooks the #ifdef CONFIG_PCI_QUIRKS, build errors are introduced. To clean that up, move the definitions of the global variables in quirks.c that are always built to pci.c, move the definitions of the empty functions (compiled when CONFIG_PCI_QUIRKS is unset) to headers (additionally make these functions static inline) and modify drivers/pci/Makefile so that quirks.c is only built if CONFIG_PCI_QUIRKS is set. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI hotplug: remove obsolete usage of get_bus_speed from rpaphp hotplug opsJesse Barnes2010-02-231-1/+0
| | | | | | | | | | | | | | | | | | | | | No longer needed and causes build breakage. Reported-by: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Add support for reporting PCIe 3.0 speedsMatthew Wilcox2010-02-232-1/+2
| | | | | | | | | | | | | | | | | | | | | Add the 8.0 GT/s speed. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Add support for AGP in cur/max bus speedMatthew Wilcox2010-02-232-5/+50
| | | | | | | | | | | | | | | | | | | | | Take advantage of some gaps in the table to fit in support for AGP speeds. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Add support for detection of PCIe and PCI-X bus speedsMatthew Wilcox2010-02-231-0/+66
| | | | | | | | | | | | | | | | | | | | | | | | Both PCIe and PCI-X bridges report their secondary bus speed in their respective capabilities. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Make current and maximum bus speeds part of the PCI coreMatthew Wilcox2010-02-2315-485/+241
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Move the max_bus_speed and cur_bus_speed into the pci_bus. Expose the values through the PCI slot driver instead of the hotplug slot driver. Update all the hotplug drivers to use the pci_bus instead of their own data structures. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Unify pcie_link_speed and pci_bus_speedMatthew Wilcox2010-02-231-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | These enums must not overlap anyway, since we only have a single pci_bus_speed_strings array. Use a single enum, and move it to pci.h. Add 'SPEED' to the pcie names to make it clear what they are. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | | PCI: Rewrite pci_scan_slotMatthew Wilcox2010-02-231-9/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Alternate Routing-ID Interpretation capability allows a single device to have up to 256 functions. They can be populated sparsely, so the current technique of scanning every eighth function is not guaranteed to find them all. By introducing a 'next_fn' function pointer, we can use the linked list of functions in the ARI capability to scan all the functions which exist. We can then speed up the pci_scan_slot by skipping the scan of subsequent devfns for PCIe devices which are the direct children of Root Ports or Downstream Ports. These devices are only permitted to implement device 0, unless they are ARI devices, in which case they'll be scanned by the ARI code above. Signed-off-by: Matthew Wilcox <willy@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| | |
| \ \
*-. \ \ Merge branches 'bugzilla-14886', 'bugzilla-15000', 'bugzilla-15040', ↵Len Brown2010-02-181-6/+0
|\ \ \ \ | | |_|/ | |/| | | | | | 'bugzilla-15108', 'pdc', 'hotplug-null-ref' and 'thinkpad' into release
| | * | ACPI: acpi_bus_{scan,bus,add}: return -ENODEV if no device was foundThomas Renninger2010-02-011-6/+0
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Callers (acpi_memhotplug.c, dock.c and others) check for the return value of acpi_bus_add() and assume a valid device was returned in case zero was returned. Thus return -ENODEV if no device was found in acpi_bus_scan and propagate this through acpi_bus_add and acpi_bus_start. Also remove a confusing comment in acpiphp_glue.c, acpi_bus_scan will and cannot invoke if acpi_bus_add returns no valid device. Signed-off-by: Thomas Renninger <trenn@suse.de> Acked-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Len Brown <len.brown@intel.com>
* | | CS5536: apply pci quirk for BIOS SMBUS bugAndres Salomon2010-02-051-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new cs5535-* drivers use PCI header config info rather than MSRs to determine the memory region to use for things like GPIOs and MFGPTs. As anticipated, we've run into a buggy BIOS: [ 0.081818] pci 0000:00:14.0: reg 10: [io 0x6000-0x7fff] [ 0.081906] pci 0000:00:14.0: reg 14: [io 0x6100-0x61ff] [ 0.082015] pci 0000:00:14.0: reg 18: [io 0x6200-0x63ff] [ 0.082917] pci 0000:00:14.2: reg 20: [io 0xe000-0xe00f] [ 0.083551] pci 0000:00:15.0: reg 10: [mem 0xa0010000-0xa0010fff] [ 0.084436] pci 0000:00:15.1: reg 10: [mem 0xa0011000-0xa0011fff] [ 0.088816] PCI: pci_cache_line_size set to 32 bytes [ 0.088938] pci 0000:00:14.0: address space collision: [io 0x6100-0x61ff] already in use [ 0.089052] pci 0000:00:14.0: can't reserve [io 0x6100-0x61ff] This is a Soekris board, and its BIOS sets the size of the PCI ISA bridge device's BAR0 to 8k. In reality, it should be 8 bytes (BAR0 is used for SMBus stuff). This quirk checks for an incorrect size, and resets it accordingly. Signed-off-by: Andres Salomon <dilinger@collabora.co.uk> Tested-by: Leigh Porter <leigh@leighporter.org> Tested-by: Jens Rottmann <JRottmann@LiPPERTEmbedded.de> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | Merge branch 'merge' of ↵Linus Torvalds2010-02-011-2/+2
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc * 'merge' of git://git.kernel.org/pub/scm/linux/kernel/git/benh/powerpc: powerpc: TIF_ABI_PENDING bit removal powerpc/pseries: Fix xics build without CONFIG_SMP powerpc/4xx: Add pcix type 1 transactions powerpc/pci: Add missing call to header fixup powerpc/pci: Add missing hookup to pci_slot powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge() powerpc/40x: Update the PowerPC 40x board defconfigs powerpc/44x: Update PowerPC 44x board defconfigs
| * | powerpc/pci: Add calls to set_pcie_port_type() and set_pcie_hotplug_bridge()Benjamin Herrenschmidt2010-01-291-2/+2
| |/ | | | | | | | | | | | | | | We are missing these when building the pci_dev from scratch off the Open Firmware device-tree Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-27 07:07:11 +0100