summaryrefslogtreecommitdiffstats
path: root/drivers/pci (follow)
Commit message (Collapse)AuthorAgeFilesLines
* PCI: Don't print anything while decoding is disabledBjorn Helgaas2012-08-231-14/+17
| | | | | | | | If we try to print to the console device while its decoding is disabled, the system will hang. Reported-and-tested-by: Olof Johansson <olof@lixom.net> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Olof Johansson <olof@lixom.net>
* PCI/PM: Fix config reg access for D3cold and bridge suspendingHuang Ying2012-08-222-0/+51
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following bug: http://marc.info/?l=linux-pci&m=134338059022620&w=2 Where lspci does not work properly if a device and the corresponding parent bridge (such as PCIe port) is suspended. This is because the device configuration space registers will be not accessible if the corresponding parent bridge is suspended or the device is put into D3cold state. To solve the issue, the bridge/PCIe port connected to the device is put into active state before read/write configuration space registers. If the device is in D3cold state, it will be put into active state too. To avoid resume/suspend PCIe port for each configuration register read/write, a small delay is added before the PCIe port to go suspended. Reported-by: Bjorn Mork <bjorn@mork.no> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
* PCI/PM: Keep parent bridge active when probing deviceHuang Ying2012-08-221-0/+6
| | | | | | | | | | | | | | | | | | | | | | This patch fixes the following bug: http://marc.info/?l=linux-pci&m=134329923124234&w=2 The root cause of the bug is as follow. If a device is not bound with the corresponding driver, the device runtime PM will be disabled and the device will be put into suspended state. So that, the bridge/PCIe port connected to it may be put into suspended and low power state. When do probing for the device later, because the bridge/PCIe port connected to it is in low power state, the IO access to device may fail. To solve the issue, the bridge/PCIe port connected to the device is put into active state before probing. Reported-by: Bjorn Mork <bjorn@mork.no> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
* PCI/PM: Enable D3/D3cold by default for most devicesHuang Ying2012-08-222-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the following bug: http://marc.info/?l=linux-usb&m=134318961120825&w=2 Originally, device lower power states include D1, D2, D3. After that, D3 is further divided into D3hot and D3cold. To support both scenario safely, original D3 is mapped to D3cold. When adding D3cold support, because worry about some device may have broken D3cold support, D3cold is disabled by default. This disable D3 on original platform too. But some original platform may only have working D3, but no working D1, D2. The root cause of the above bug is it too. To deal with this, this patch enables D3/D3cold by default for most devices. This restores the original behavior. For some devices that suspected to have broken D3cold support, such as PCIe port, D3cold is disabled by default. Reported-by: Bjorn Mork <bjorn@mork.no> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl>
* PCI: EHCI: Fix crash during hibernation on ASUS computersRafael J. Wysocki2012-08-151-0/+7
| | | | | | | | | | | | | | | | Commit dbf0e4c (PCI: EHCI: fix crash during suspend on ASUS computers) added a workaround for an ASUS suspend issue related to USB EHCI and a bug in a number of ASUS BIOSes that attempt to shut down the EHCI controller during system suspend if its PCI command register doesn't contain 0 at that time. It turns out that the same workaround is necessary in the analogous hibernation code path, so add it. References: https://bugzilla.kernel.org/show_bug.cgi?id=45811 Reported-and-tested-by: Oleksij Rempel <bug-track@fisher-privat.net> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: stable@vger.kernel.org
* PCI / PM: Fix D3/D3cold/D4 messages printed by acpi_pci_set_power_state()Rafael J. Wysocki2012-08-151-2/+2
| | | | | | | | | | | | | | If a PCI device is put into D3_cold by acpi_bus_set_power(), the message printed by acpi_pci_set_power_state() says that its power state has been changed to D4, which doesn't make sense. In turn, if the device is put into D3_hot, the message simply says "D3" without specifying the variant of the D3 state. Fix this by using the pci_power_name() macro for printing the state name instead of building it from the numeric value corresponding to the given state directly. Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
* Merge tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pciLinus Torvalds2012-07-2535-632/+1064
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull PCI changes from Bjorn Helgaas: "Host bridge hotplug: - Add MMCONFIG support for hot-added host bridges (Jiang Liu) Device hotplug: - Move fixups from __init to __devinit (Sebastian Andrzej Siewior) - Call FINAL fixups for hot-added devices, too (Myron Stowe) - Factor out generic code for P2P bridge hot-add (Yinghai Lu) - Remove all functions in a slot, not just those with _EJx (Amos Kong) Dynamic resource management: - Track bus number allocation (struct resource tree per domain) (Yinghai Lu) - Make P2P bridge 1K I/O windows work with resource reassignment (Bjorn Helgaas, Yinghai Lu) - Disable decoding while updating 64-bit BARs (Bjorn Helgaas) Power management: - Add PCIe runtime D3cold support (Huang Ying) Virtualization: - Add VFIO infrastructure (ACS, DMA source ID quirks) (Alex Williamson) - Add quirks for devices with broken INTx masking (Jan Kiszka) Miscellaneous: - Fix some PCI Express capability version issues (Myron Stowe) - Factor out some arch code with a weak, generic, pcibios_setup() (Myron Stowe)" * tag 'for-3.6' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (122 commits) PCI: hotplug: ensure a consistent return value in error case PCI: fix undefined reference to 'pci_fixup_final_inited' PCI: build resource code for M68K architecture PCI: pciehp: remove unused pciehp_get_max_lnk_width(), pciehp_get_cur_lnk_width() PCI: reorder __pci_assign_resource() (no change) PCI: fix truncation of resource size to 32 bits PCI: acpiphp: merge acpiphp_debug and debug PCI: acpiphp: remove unused res_lock sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases() PCI: call final fixups hot-added devices PCI: move final fixups from __init to __devinit x86/PCI: move final fixups from __init to __devinit MIPS/PCI: move final fixups from __init to __devinit PCI: support sizing P2P bridge I/O windows with 1K granularity PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2) PCI: disable MEM decoding while updating 64-bit MEM BARs PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too PCI: never discard enable/suspend/resume_early/resume fixups PCI: release temporary reference in __nv_msi_ht_cap_quirk() PCI: restructure 'pci_do_fixups()' ...
| * Merge branch 'pci/yinghai-pciehp-unused' into nextBjorn Helgaas2012-07-182-105/+0
| |\ | | | | | | | | | | | | * pci/yinghai-pciehp-unused: PCI: pciehp: remove unused pciehp_get_max_lnk_width(), pciehp_get_cur_lnk_width()
| | * PCI: pciehp: remove unused pciehp_get_max_lnk_width(), ↵Yinghai Lu2012-07-122-105/+0
| | | | | | | | | | | | | | | | | | | | | pciehp_get_cur_lnk_width() Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Cc: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com>
| * | Merge branch 'pci/nikhil-big-bar-fixes' into nextBjorn Helgaas2012-07-181-53/+54
| |\ \ | | | | | | | | | | | | | | | | | | | | * pci/nikhil-big-bar-fixes: PCI: reorder __pci_assign_resource() (no change) PCI: fix truncation of resource size to 32 bits
| | * | PCI: reorder __pci_assign_resource() (no change)Bjorn Helgaas2012-07-121-52/+52
| | | | | | | | | | | | | | | | | | | | | | | | Reorder functions so __pci_assign_resource(), _pci_assign_resource(), and pci_assign_resource() are closer together. No code change. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: fix truncation of resource size to 32 bitsNikhil P Rao2012-07-121-1/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | _pci_assign_resource() took an int "size" argument, which meant that sizes larger than 4GB were truncated. Change type to resource_size_t. [bhelgaas: changelog] Signed-off-by: Nikhil P Rao <nikhil.rao@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/julia-return-values' into nextBjorn Helgaas2012-07-164-16/+40
| |\ \ | | | | | | | | | | | | | | | | * pci/julia-return-values: PCI: hotplug: ensure a consistent return value in error case
| | * | PCI: hotplug: ensure a consistent return value in error caseJulia Lawall2012-07-164-16/+40
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Typically, the return value desired for the failure of a function with an integer return value is a negative integer. In these cases, the return value is sometimes a negative integer and sometimes 0, due to a subsequent initialization of the return variable within the loop. A simplified version of the semantic match that finds this problem is: (http://coccinelle.lip6.fr/) //<smpl> @r exists@ identifier ret; position p; constant C; expression e1,e3,e4; statement S; @@ ret = -C ... when != ret = e3 when any if@p (...) S ... when any if (\(ret != 0\|ret < 0\|ret > 0\) || ...) { ... return ...; } ... when != ret = e3 when any *if@p (...) { ... when != ret = e4 return ret; } //</smpl> [bhelgaas: squashed into one patch] Signed-off-by: Julia Lawall <Julia.Lawall@lip6.fr> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/myron-final-fixups-v2' into nextBjorn Helgaas2012-07-162-19/+5
| |\ \ | | | | | | | | | | | | | | | | * pci/myron-final-fixups-v2: PCI: fix undefined reference to 'pci_fixup_final_inited'
| | * | PCI: fix undefined reference to 'pci_fixup_final_inited'Myron Stowe2012-07-162-19/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | My "PCI: Integrate 'pci_fixup_final' quirks into hot-plug paths" patch introduced an undefined reference to 'pci_fixup_final_inited' when CONFIG_PCI_QUIRKS is not enabled (on x86_64): drivers/built-in.o: In function `pci_bus_add_device': (.text+0x4f62): undefined reference to `pci_fixup_final_inited' This patch removes the external reference ending up with a result closer to what we ultimately want when the boot path issues described in the original patch are resolved. References: https://lkml.org/lkml/2012/7/9/542 Original, offending, patch https://lkml.org/lkml/2012/7/12/338 Randy's catch Reported-by: Randy Dunlap <rdunlap@xenotime.net> Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Randy Dunlap <rdunlap@xenotime.net>
| * | | Merge branch 'pci/greg-m68k' into nextBjorn Helgaas2012-07-131-0/+1
| |\ \ \ | | | | | | | | | | | | | | | | | | | | * pci/greg-m68k: PCI: build resource code for M68K architecture
| | * | | PCI: build resource code for M68K architectureGreg Ungerer2012-07-131-0/+1
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ColdFire M54xx family of CPU cores (supported by the m68k arch code) have PCI bus hardware. We want to be able to use this and will need the setup-bus.c and setup-irq.c helper functions. So when CONFIG_M68K is enabled add them to the objs build list. Signed-off-by: Greg Ungerer <gerg@uclinux.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'pci/yinghai-hotplug-cleanup' into nextBjorn Helgaas2012-07-113-11/+3
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * pci/yinghai-hotplug-cleanup: PCI: acpiphp: merge acpiphp_debug and debug PCI: acpiphp: remove unused res_lock
| | * | | PCI: acpiphp: merge acpiphp_debug and debugYinghai Lu2012-07-112-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Should not have two, just remove debug, and use module_param_named instead. Also change acpiphp_debug to bool. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: acpiphp: remove unused res_lockYinghai Lu2012-07-102-5/+0
| | |/ / | | | | | | | | | | | | | | | | | | | | res_lock is never used, so remove it. Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'pci/bjorn-p2p-bridge-windows' into nextBjorn Helgaas2012-07-103-60/+49
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/bjorn-p2p-bridge-windows: sparc/PCI: replace pci_cfg_fake_ranges() with pci_read_bridge_bases() PCI: support sizing P2P bridge I/O windows with 1K granularity PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2) PCI: allow P2P bridge windows starting at PCI bus address zero Conflicts: drivers/pci/probe.c include/linux/pci.h
| | * | | PCI: support sizing P2P bridge I/O windows with 1K granularityYinghai Lu2012-07-101-6/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some bridges support I/O windows with 1K alignment, not just the 4K alignment defined by the PCI spec. For example, see the IOBL_ADR register and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2). This patch adds support for sizing the window in 1K increments based on the requirements of downstream devices. [bhelgaas: changelog, comment] Signed-off-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: reimplement P2P bridge 1K I/O windows (Intel P64H2)Bjorn Helgaas2012-07-103-51/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 9d265124d051 and 15a260d53f7c added quirks for P2P bridges that support I/O windows that start/end at 1K boundaries, not just the 4K boundaries defined by the PCI spec. For details, see the IOBL_ADR register and the EN1K bit in the CNF register in the Intel 82870P2 (P64H2). These quirks complicate the code that reads P2P bridge windows (pci_read_bridge_io() and pci_cfg_fake_ranges()) because the bridge I/O resource is updated in the HEADER quirk, in pci_read_bridge_io(), in pci_setup_bridge(), and again in the FINAL quirk. This is confusing and makes it impossible to reassign the bridge windows after FINAL quirks are run. This patch adds support for 1K windows in the generic paths, so the HEADER quirk only has to enable this support. The FINAL quirk, which used to undo damage done by pci_setup_bridge(), is no longer needed. This removes "if (!res->start) res->start = ..." from pci_read_bridge_io(); that was part of 9d265124d051 to avoid overwriting the resource filled in by the quirk. Since pci_read_bridge_io() itself now knows about granularity, the quirk no longer updates the resource and this test is no longer needed. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: allow P2P bridge windows starting at PCI bus address zeroBjorn Helgaas2012-07-091-3/+3
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | cd81e1ea1a4c added checks that prevent us from using P2P bridge windows that start at PCI bus address zero. The reason was to "prevent us from overwriting resources that are unassigned." But generic code should allow address zero in both BARs and bridge windows, so I think that commit was a mistake. Windows at bus address zero are legal and likely to exist on machines with an offset between bus addresses and CPU addresses. For example, in the following hypothetical scenario, the bridge at 00:01.0 has a window at bus address zero and the device at 01:00.0 has a BAR at bus address zero, and I think both are perfectly valid: PCI host bridge to bus 0000:00 pci_bus 0000:00: root bus resource [mem 0x100000000-0x1ffffffff] (bus address [0x00000000-0xffffffff]) pci 0000:00:01.0: PCI bridge to [bus 01] pci 0000:00:01.0: bridge window [mem 0x100000000-0x100ffffff] pci 0000:01:00.0: reg 10: [mem 0x100000000-0x100ffffff] Acked-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'pci/bjorn-disable-decode' into nextBjorn Helgaas2012-07-102-3/+21
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | * pci/bjorn-disable-decode: PCI: disable MEM decoding while updating 64-bit MEM BARs PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, too
| | * | | PCI: disable MEM decoding while updating 64-bit MEM BARsBjorn Helgaas2012-07-101-0/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When we update 64-bit BARs, we have to perform two config writes. Between the writes, the half-written BAR value could match a MEM access intended for another device. This could result in corruption of this device (for writes) or an unexpected response machine check (for reads). To prevent this, disable MEM decoding while updating such BARs. This uses the same safety test as 253d2e5498, which disables both MEM and IO while sizing BARs, namely, we don't disable decoding for host bridge devices. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: leave MEM and IO decoding disabled during 64-bit BAR sizing, tooBjorn Helgaas2012-07-101-3/+3
| | |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After 253d2e5498, we disable MEM and IO decoding for most devices while we size 32-bit BARs. However, we restore the original COMMAND register before we size the upper 32 bits of 64-bit BARs, so we can still cause a conflict. This patch waits to restore the original COMMAND register until we're completely finished sizing the BAR. Reference: https://lkml.org/lkml/2007/8/25/154 Acked-by: Jacob Pan <jacob.jun.pan@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'pci/myron-final-fixups-v2' into nextBjorn Helgaas2012-07-102-32/+71
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/myron-final-fixups-v2: PCI: call final fixups hot-added devices PCI: move final fixups from __init to __devinit x86/PCI: move final fixups from __init to __devinit MIPS/PCI: move final fixups from __init to __devinit PCI: never discard enable/suspend/resume_early/resume fixups PCI: release temporary reference in __nv_msi_ht_cap_quirk() PCI: restructure 'pci_do_fixups()'
| | * | PCI: call final fixups hot-added devicesMyron Stowe2012-07-102-0/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Final fixups are currently applied only at boot-time by pci_apply_final_quirks(), which is an fs_initcall(). Hot-added devices don't get these fixups, so they may not be completely initialized. This patch makes us run final fixups for hot-added devices in pci_bus_add_device() just before the new device becomes eligible for driver binding. This patch keeps the fs_initcall() for devices present at boot because we do resource assignment between pci_bus_add_device and the fs_initcall(), and we don't want to break any fixups that depend on that assignment. This is a design issue that may be addressed in the future -- any resource assignment should be done *before* device_add(). [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: move final fixups from __init to __devinitMyron Stowe2012-07-101-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Final fixups are executed during device enumeration. If we support hotplug, this may be after boot, so final fixups cannot be __init. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: never discard enable/suspend/resume_early/resume fixupsMyron Stowe2012-07-101-14/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The enable/suspend/resume_early/resume fixups can be called at any time, so they can't be __init or __devinit. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: release temporary reference in __nv_msi_ht_cap_quirk()Myron Stowe2012-07-101-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | __nv_msi_ht_cap_quirk() acquires a temporary reference via 'pci_get_bus_and_slot()' that is never released. This patch releases the temporary reference. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: restructure 'pci_do_fixups()'Myron Stowe2012-07-101-16/+30
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | This patch restructures pci_do_fixups()'s quirk invocations in the style of initcall_debug_start() and initcall_debug_report(), so we have only one call site for the quirk. [bhelgaas: changelog] Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/rafael-pci_set_power_state-rebase' into nextBjorn Helgaas2012-07-063-7/+27
| |\ \ | | | | | | | | | | | | | | | | * pci/rafael-pci_set_power_state-rebase: PCI / PM: restore the original behavior of pci_set_power_state()
| | * | PCI / PM: restore the original behavior of pci_set_power_state()Rafael J. Wysocki2012-07-053-7/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit cc2893b6 (PCI: Ensure we re-enable devices on resume) addressed the problem with USB not being powered after resume on recent Lenovo machines, but it did that in a suboptimal way. Namely, it should have changed the relevant code paths only, which are pci_pm_resume_noirq() and pci_pm_restore_noirq() supposed to restore the device's power and standard configuration registers after system resume from suspend or hibernation. Instead, however, it modified pci_set_power_state() which is executed in several other situations too. That resulted in some undesirable effects, like attempting to change a device's power state in the same way multiple times in a row (up to as many as 4 times in a row in the snd_hda_intel driver). Fix the bug addressed by commit cc2893b6 in an alternative way, by forcibly powering up all devices in pci_pm_default_resume_early(), which is called by pci_pm_resume_noirq() and pci_pm_restore_noirq() to restore the device's power and standard configuration registers, and modifying pci_pm_runtime_resume() to avoid the forcible power-up if not necessary. Then, revert the changes made by commit cc2893b6 to make the confusion introduced by it go away. Acked-by: Matthew Garrett <mjg@redhat.com> Signed-off-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'pci/myron-pcibios_setup' into nextBjorn Helgaas2012-07-051-0/+12
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * pci/myron-pcibios_setup: xtensa/PCI: factor out pcibios_setup() x86/PCI: adjust section annotations for pcibios_setup() unicore32/PCI: adjust section annotations for pcibios_setup() tile/PCI: factor out pcibios_setup() sparc/PCI: factor out pcibios_setup() sh/PCI: adjust section annotations for pcibios_setup() sh/PCI: factor out pcibios_setup() powerpc/PCI: factor out pcibios_setup() parisc/PCI: factor out pcibios_setup() MIPS/PCI: adjust section annotations for pcibios_setup() MIPS/PCI: factor out pcibios_setup() microblaze/PCI: factor out pcibios_setup() ia64/PCI: factor out pcibios_setup() cris/PCI: factor out pcibios_setup() alpha/PCI: factor out pcibios_setup() PCI: pull pcibios_setup() up into core
| | * | | PCI: pull pcibios_setup() up into coreMyron Stowe2012-06-261-0/+12
| | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, all of the architectures implement their own pcibios_setup() routine. Most of the implementations do nothing so this patch introduces a generic (__weak) routine in the core that can be used by all architectures as a default. If necessary, it can be overridden by architecture-specific code. Signed-off-by: Myron Stowe <myron.stowe@redhat.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'topic/huang-d3cold-v7' into nextBjorn Helgaas2012-06-236-13/+233
| |\ \ \ | | | |/ | | |/| | | | | | | | | | | | | | | | | | | | | * topic/huang-d3cold-v7: PCI/PM: add PCIe runtime D3cold support PCI: do not call pci_set_power_state with PCI_D3cold PCI/PM: add runtime PM support to PCIe port ACPI/PM: specify lowest allowed state for device sleep state
| | * | PCI/PM: add PCIe runtime D3cold supportHuang Ying2012-06-236-18/+203
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime D3cold support and corresponding ACPI platform support. This patch only enables runtime D3cold support; it does not enable D3cold support during system suspend/hibernate. D3cold is the deepest power saving state for a PCIe device, where its main power is removed. While it is in D3cold, you can't access the device at all, not even its configuration space (which is still accessible in D3hot). Therefore the PCI PM registers can not be used to transition into/out of the D3cold state; that must be done by platform logic such as ACPI _PR3. To support wakeup from D3cold, a system may provide auxiliary power, which allows a device to request wakeup using a Beacon or the sideband WAKE# signal. WAKE# is usually connected to platform logic such as ACPI GPE. This is quite different from other power saving states, where devices request wakeup via a PME message on the PCIe link. Some devices, such as those in plug-in slots, have no direct platform logic. For example, there is usually no ACPI _PR3 for them. D3cold support for these devices can be done via the PCIe Downstream Port leading to the device. When the PCIe port is powered on/off, the device is powered on/off too. Wakeup events from the device will be notified to the corresponding PCIe port. For more information about PCIe D3cold and corresponding ACPI support, please refer to: - PCI Express Base Specification Revision 2.0 - Advanced Configuration and Power Interface Specification Revision 5.0 [bhelgaas: changelog] Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Originally-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI/PM: add runtime PM support to PCIe portZheng Yan2012-06-232-0/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds runtime PM support to PCIe port. This is needed by PCIe D3cold support, where PCIe device without ACPI node may be powered on/off by PCIe port. Because runtime suspend is broken for some chipsets, a black list is used to disable runtime PM support for these chipsets. Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Zheng Yan <zheng.z.yan@intel.com> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | ACPI/PM: specify lowest allowed state for device sleep stateHuang Ying2012-06-231-1/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Lower device sleep state can save more power, but has more exit latency too. Sometimes, to satisfy some power QoS and other requirement, we need to constrain the lowest device sleep state. In this patch, a parameter to specify lowest allowed state for acpi_pm_device_sleep_state is added. So that the caller can enforce the constraint via the parameter. This is needed by PCIe D3cold support, where the lowest power state allowed may be D3_HOT instead of default D3_COLD. CC: Len Brown <lenb@kernel.org> CC: linux-acpi@vger.kernel.org Reviewed-by: Rafael J. Wysocki <rjw@sisk.pl> Signed-off-by: Huang Ying <ying.huang@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'topic/jiang-mmconfig-v10' into nextBjorn Helgaas2012-06-221-0/+14
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * topic/jiang-mmconfig-v10: ACPI: mark acpi_sfi_table_parse() as __init x86/PCI: use pr_level() to replace printk(KERN_LEVEL) x86/PCI: refine __pci_mmcfg_init() for better code readability x86/PCI: get rid of redundant log messages x86/PCI: simplify pci_mmcfg_late_insert_resources() x86/PCI: update MMCONFIG information when hot-plugging PCI host bridges PCI/ACPI: provide MMCONFIG address for PCI host bridges x86/PCI: add pci_mmconfig_insert()/delete() for PCI root bridge hotplug x86/PCI: prepare pci_mmcfg_check_reserved() to be called at runtime x86/PCI: introduce pci_mmcfg_arch_map()/pci_mmcfg_arch_unmap() x86/PCI: use RCU list to protect mmconfig list x86/PCI: split out pci_mmconfig_alloc() for code reuse x86/PCI: split out pci_mmcfg_check_reserved() for code reuse
| | * | PCI/ACPI: provide MMCONFIG address for PCI host bridgesJiang Liu2012-06-221-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch provide MMCONFIG address for PCI host bridges, which will be used to support host bridge hotplug. It gets MMCONFIG address by evaluating _CBA method if available. Reviewed-by: Yinghai Lu <yinghai@kernel.org> Signed-off-by: Jiang Liu <liuj97@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | | Merge branch 'topic/bjorn-trivial' into nextBjorn Helgaas2012-06-226-25/+28
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * topic/bjorn-trivial: PCI: remove useless pcix_set_mmrbc() dev->bus check PCI: acpiphp: check whether _ADR evaluation succeeded PCI: shpchp: remove dead code PCI: fix P2P bridge I/O port window sign extension PCI: fix upstream P2P bridge checks when enabling OBFF and LTR PCI: use __weak consistently PCI: cleanup assign_requested_resources_sorted() kernel-doc warning sparc/PCI: remove unused pcibios_assign_resource() definition
| | * | | PCI: remove useless pcix_set_mmrbc() dev->bus checkBjorn Helgaas2012-06-211-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For a valid pci_dev, dev->bus != NULL always, so remove this unnecessary test. Found by Coverity (CID 101680). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: acpiphp: check whether _ADR evaluation succeededBjorn Helgaas2012-06-211-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check whether we evaluated _ADR successfully. Previously we ignored failure, so we would have used garbage data from the stack as the device and function number. We return AE_OK so that we ignore only this slot and continue looking for other slots. Found by Coverity (CID 113981). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: shpchp: remove dead codeBjorn Helgaas2012-06-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | "slots_not_empty" is initialized to zero and can't be set again before reaching this point, so this return statement is dead. Remove it. Found by Coverity (CID 114324). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: fix P2P bridge I/O port window sign extensionBjorn Helgaas2012-06-211-8/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On P2P bridges with 32-bit I/O decoding, we incorrectly sign-extended windows starting at 0x80000000 or above. In "base |= (io_base_hi << 16)", "io_base_hi" is promoted to a signed int before being extended to an unsigned long. This would cause a window starting at I/O address 0x80000000 to be treated as though it started at 0xffffffff80008000 instead, which should cause "no compatible bridge window" errors when we enumerate devices using that I/O space. The mmio and mmio_pref casts are not strictly necessary, but without them, correctness depends on the types of the PCI_MEMORY_RANGE_MASK and PCI_PREF_RANGE_MASK constants, which are not obvious from reading the local code. Found by Coverity (CID 138747 and CID 138748). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | | PCI: fix upstream P2P bridge checks when enabling OBFF and LTRBjorn Helgaas2012-06-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pci_enable_obff() and pci_enable_ltr() incorrectly check "dev->bus" instead of "dev->bus->self" to determine whether the upstream device is a P2P bridge or a host bridge. For devices on the root bus, the upstream device is a host bridge, "dev->bus != NULL" and "dev->bus->self == NULL", and we panic with a null pointer dereference. These functions should previously have panicked when called on devices supporting OBFF or LTR, so they should be regarded as untested. Found by Coverity (CID 143038 and CID 143039). Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-24 16:43:50 +0100