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* ACPI/PCI: another multiple _OSC memory leak fixKenji Kaneshige2008-05-131-1/+7
| | | | | | | | | | The acpi_query_osc() function can be called for the ACPI object that doesn't have _OSC method. In this case, acpi_get_osc_data() would allocate a useless memory region. To avoid this, we need to check the existence of _OSC before calling acpi_get_osc_data() in acpi_query_osc(). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: enable nv_msi_ht_cap_quirk for ALi bridgesBjörn Krombholz2008-05-131-0/+1
| | | | | | | | | | | | | | | | This applies the NVidia MSI enabled flag for HT capable devices quirk to ALi bridges as well. As described in more detail in http://bugzilla.kernel.org/show_bug.cgi?id=10667 this is required for my board which is using an nForce 3 250Gb chipset with an ALi M1695 northbridge. It fixes a regression introduced in 2.6.24 that made the internal NIC of the board unusable (MSI initialisation of the NIC but disabled MSI on the northbridge devices. Signed-off-by: Björn Krombholz <fox.box@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI: Make the intel-iommu_wait_op macro work when jiffies are not runningmark gross2008-05-131-3/+3
| | | | | | | | | | | The following patch changes the intel-iommu.c code to use the TSC instead of jiffies for detecting bad DMAR functionality. Some systems with bad bios's have been seen to hang in early boot spinning in the IOMMU_WAIT_IO macro. This patch will replace the infinite loop with a call to panic. Signed-off-by: Mark Gross <mgross@linux.intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* ACPI/PCI: handle multiple _OSCKenji Kaneshige2008-05-131-1/+7
| | | | | | | | | | | The pci_osc_control_set() function can be called for the ACPI object that doesn't have _OSC method. In this case, acpi_get_osc_data() would allocate a useless memory region. To avoid this, we need to check the existence of _OSC before calling acpi_get_osc_data(). Here is a patch to fix this problem in pci_osc_control_set. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* ACPI/PCI: handle multiple _OSCShaohua Li2008-05-131-29/+66
| | | | | | | | | | There is an IA64 system here which have two pci root bridges with _OSC. One _OSC disables SHPC control bit but the other not. Below patch makes _OSC data per-device instead of one global, otherwise linux takes both root bridges don't support SHPC. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* PCI ACPI: fix uninitialized variable in __pci_osc_support_setKenji Kaneshige2008-05-131-1/+1
| | | | | | | | | | | | | | | Fix uninitialized variable in __pci_osc_support_set(). If the ACPI namespace doesn't have any device object corresponding to the specified hid, 'retval' in __pci_osc_support_set() is not changed by the acpi_query_osc() callback. Since 'retval' is not initizlized in the current implementation, the contents of 'retval' is undefined in this case. This causes a mis-handling of ctrlset_buf[OSC_SUPPORT_TYPE] and will cause an unexpected result in the subsequent pci_osc_control_set() call as a result. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* x86/pci: remove flag in pci_cfg_space_size_extYinghai Lu2008-04-301-16/+17
| | | | | | | so let pci_cfg_space_size call it directly without flag. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* Merge branch 'for-linus' of ↵Linus Torvalds2008-04-298-447/+271
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6 * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/pci-2.6: (21 commits) pciehp: fix error message about getting hotplug control pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2 pci/irq: restore mask_bits in msi shutdown -v3 doc: replace yet another dev with pdev for consistency in DMA-mapping.txt PCI: don't expose struct pci_vpd to userspace doc: fix an incorrect suggestion to pass NULL for PCI like buses Consistently use pdev as the variable of type struct pci_dev *. pciehp: Fix command write shpchp: fix slot name make pciehp_acpi_get_hp_hw_control_from_firmware() pciehp: Clean up pcie_init() pciehp: Mask hotplug interrupt at controller release pciehp: Remove useless hotplug interrupt enabling pciehp: Fix wrong slot capability check pciehp: Fix wrong slot control register access pciehp: Add missing memory barrier pciehp: Fix interrupt event handlig pciehp: fix slot name Update MAINTAINERS with location of PCI tree PCI: Add Intel SCH PCI IDs ...
| * pciehp: fix error message about getting hotplug controlKenji Kaneshige2008-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | People are confused by the following error message that actually is not for indicating a error. Cannot get control of hotplug hardware for pci %s This patch changes this message to debug message. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
| * pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2Yinghai Lu2008-04-292-9/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [PATCH 2/2] pci/irq: let pci_device_shutdown to call pci_msi_shutdown v2 this change | commit 23a274c8a5adafc74a66f16988776fc7dd6f6e51 | Author: Prakash, Sathya <sathya.prakash@lsi.com> | Date: Fri Mar 7 15:53:21 2008 +0530 | | [SCSI] mpt fusion: Enable MSI by default for SAS controllers | | This patch modifies the driver to enable MSI by default for all SAS chips. | | Signed-off-by: Sathya Prakash <sathya.prakash@lsi.com> | Signed-off-by: James Bottomley <James.Bottomley@HansenPartnership.com> | Causes the kexec of a RHEL 5.1 kernel to fail. root casue: the rhel 5.1 kernel still uses INTx emulation. and mptscsih_shutdown doesn't call pci_disable_msi to reenable INTx on kexec path So call pci_msi_shutdown in the shutdown path to do the same thing to msix Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
| * pci/irq: restore mask_bits in msi shutdown -v3Yinghai Lu2008-04-291-7/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | [PATCH 1/2] pci/irq: restore mask_bits in msi shutdown -v3 Yinghai found that kexec'ing a RHEL 5.1 kernel with 2.6.25-rc3+ kernels prevents his NIC from working. He bisected to | commit 89d694b9dbe769ca1004e01db0ca43964806a611 | Author: Thomas Gleixner <tglx@linutronix.de> | Date: Mon Feb 18 18:25:17 2008 +0100 | | genirq: do not leave interupts enabled on free_irq | | The default_disable() function was changed in commit: | | 76d2160147f43f982dfe881404cfde9fd0a9da21 | genirq: do not mask interrupts by default | For MSI, default_shutdown will call mask_bit for msi device. All mask bits will left disabled after free_irq. Then in the kexec case, the next kernel can only use msi_enable bit, so all device's MSI can not be used. So lets to restore the mask bit to its pci reset defined value (enabled) when we disable the kernels use of msi to be a little friendlier to kexec'd kernels. Extend msi_set_mask_bit to msi_set_mask_bits to take mask, so we can fully restore that to 0x00 instead of 0xfe. Signed-off-by: Yinghai Lu <yhlu.kernel@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@hobbes.lan>
| * pciehp: Fix command writeKenji Kaneshige2008-04-251-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Current implementation of pciehp_write_cmd() always enables command completed interrupt. But pciehp_write_cmd() is also used for clearing command completed interrupt enable bit. In this case, we must not set the command completed interrupt enable bit. To fix this bug, this patch add the check to see if caller wants to change command complete interrupt enable bit. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * shpchp: fix slot nameKenji Kaneshige2008-04-251-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current shpchp uses the combination of bus number and slot number as a slot name. But it is not a good idea because bus number is not a physical identifier but a logical identifier. This is against the shpc specification. So remove the bus number from the physical identifier. However, there are some platforms with the problem that it provides the same slot number. For those platforms, this patch also introduces new module option 'shpchp_slot_with_bus'. If it is specified, shpchp uses the combination of bus number and slot number as a slot name. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * make pciehp_acpi_get_hp_hw_control_from_firmware()Adrian Bunk2008-04-251-1/+1
| | | | | | | | | | | | | | | | | | | | this_patch_makes_the_needlessly_global_pciehp_acpi_get_hp_hw_control_from_firmware_static ;) Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Clean up pcie_init()Kenji Kaneshige2008-04-251-110/+88
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up pciehp_ini(). This patch is trying to - Remove redundant capablity checks that were already done in PCIe port bus driver. - Separate the code only for debugging and make debug information easier to read. - Make the entire code easier to read and understand what it is doing. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Mask hotplug interrupt at controller releaseKenji Kaneshige2008-04-251-0/+4
| | | | | | | | | | | | | | | | | | | | We must disable hotplug interrupt at controller relase time, otherwise spurious interrupts might happen if any slot events occured (e.g. MRL change) after unloading pciehp driver. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Remove useless hotplug interrupt enablingKenji Kaneshige2008-04-251-46/+8
| | | | | | | | | | | | | | | | | | | | Hotplug interrupt is enabled at initialization and nobody clears it. So we need to setup it in each command. This patch removes redundant codes about this. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Fix wrong slot capability checkKenji Kaneshige2008-04-254-39/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Current pciehp saves only 8bits of Slot Capability registers in ctrl->ctrlcap. But it refers more than 8bit for checking EMI capability. It is clearly a bug and EMI would never work. To fix this problem, this patch saves full Slot Capability contens in ctrl->slot_cap. It also reduce the redundant reads of Slot Capability register. And this pach also cleans up the macros to check the slot capabilitys (e.g. MRL_SENS(), and so on). Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Fix wrong slot control register accessKenji Kaneshige2008-04-251-112/+38
| | | | | | | | | | | | | | | | | | | | | | Current pciehp implementaion clears hotplug events without waiting for command completion. Because of this, events might not be cleared properly. To prevent this problem, we must use pciehp_write_cmd() to write to Slot Control register. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Add missing memory barrierKenji Kaneshige2008-04-251-0/+2
| | | | | | | | | | | | | | | | | | Fix the possible race condition between pcie_isr() and pciehp_write_cmd() because of the lack of memory barrier. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: Fix interrupt event handligKenji Kaneshige2008-04-252-120/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current pciehp implementation disables and re-enables hotplug interrupts in its interrupt handler. This operation might be intend to guarantee that interrupts for the events newly occured during previous events are being handled will be successfully generated. But current implementaion has the following prolems. - Current interrupt service routin clears status changes without waiting command completion. Because of this, events might not be cleared properly. - Current interrupt service routine clears status changes caused by disabling or enabling hotplug interrupts itself. This will lose new events that occurs during previous interrupts are being handled. - Current implementation doesn't have any serialization mechanism between the code to wait for command completion and the interrupt handler that clears the command completion events caused by itself. There is clearly race conditions between them, and it may cause the problem that waiting for command completion doesn't work for example. To fix those problems, this patch stops disabling/re-enabling hotplug interrupts in interrupt service routine. Instead of this, this patch re-inspects Slot Status register after clearing what is presumed to be the last bending interrupt in order to guarantee that all interrupt events are serviced. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * pciehp: fix slot nameKenji Kaneshige2008-04-251-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current pciehp uses the combination of bus number and slot number as a slot name. But it is not a good idea because bus number is not a physical identifier but a logical identifier. This is against the PCIE specification. So remove the bus number from the physical identifier. However, there are some platforms with the problem that it provides the same slot number. For those platforms, this patch also introduces new module option 'pciehp_slot_with_bus'. If it is specified, pciehp uses the combination of bus number and slot number as a slot name. Signed-off-by: Kenji Kaneshige <kaneshige.kenji@jp.fujitsu.com> Signed-off-by: Kristen Carlson Accardi <kristen.c.accardi@intel.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
| * PCI Express ASPM support should default to 'No'Jesper Juhl2008-04-241-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Running 'make oldconfig' I just noticed that PCIEASPM defaults to 'y' in Kconfig even though the feature is both experimental and the help text recommends that if you are unsure you say 'n'. It seems to me that this really should default to 'n', not 'y' at the moment. The following patch makes that change. Please consider applying. Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
* | Merge branch 'for-linus' of ↵Linus Torvalds2008-04-291-2/+19
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci * 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/x86/linux-2.6-x86-bigbox-pci: x86: add pci=check_enable_amd_mmconf and dmi check x86: work around io allocation overlap of HT links acpi: get boot_cpu_id as early for k8_scan_nodes x86_64: don't need set default res if only have one root bus x86: double check the multi root bus with fam10h mmconf x86: multi pci root bus with different io resource range, on 64-bit x86: use bus conf in NB conf fun1 to get bus range on, on 64-bit x86: get mp_bus_to_node early x86 pci: remove checking type for mmconfig probe x86: remove unneeded check in mmconf reject driver core: try parent numa_node at first before using default x86: seperate mmconf for fam10h out from setup_64.c x86: if acpi=off, force setting the mmconf for fam10h x86_64: check MSR to get MMCONFIG for AMD Family 10h x86_64: check and enable MMCONFIG for AMD Family 10h x86_64: set cfg_size for AMD Family 10h in case MMCONFIG x86: mmconf enable mcfg early x86: clear pci_mmcfg_virt when mmcfg get rejected x86: validate against acpi motherboard resources Fixed up fairly trivial conflicts in arch/x86/pci/{init.c,pci.h} due to OLPC support manually.
| * | x86: multi pci root bus with different io resource range, on 64-bitYinghai Lu2008-04-261-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | scan AMD opteron io/mmio routing to make sure every pci root bus get correct resource range. Thus later pci scan could assign correct resource to device with unassigned resource. this can fix a system without _CRS for multi pci root bus. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
| * | driver core: try parent numa_node at first before using defaultYinghai Lu2008-04-261-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | in the device_add, we try to use use parent numa_node. need to make sure pci root bus's bridge device numa_node is set. then we could use device->numa_node direclty for all device. and don't need to call pcibus_to_node(). Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
| * | x86_64: set cfg_size for AMD Family 10h in case MMCONFIGYinghai Lu2008-04-261-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | reuse pci_cfg_space_size but skip check pci express and pci-x CAP ID. Signed-off-by: Yinghai Lu <yinghai.lu@sun.com> Cc: Andrew Morton <akpm@linux-foundation.org> Acked-by: Greg Kroah-Hartman <gregkh@suse.de> Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu> Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
* | | drivers: use non-racy method for proc entries creation (2)Denis V. Lunev2008-04-291-7/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use proc_create()/proc_create_data() to make sure that ->proc_fops and ->data be setup before gluing PDE to main tree. Signed-off-by: Denis V. Lunev <den@openvz.org> Cc: Greg Kroah-Hartman <gregkh@suse.de> Cc: Alexey Dobriyan <adobriyan@gmail.com> Cc: "Eric W. Biederman" <ebiederm@xmission.com> Cc: Peter Osterlund <petero2@telia.com> Cc: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com> Cc: Dmitry Torokhov <dtor@mail.ru> Cc: Neil Brown <neilb@suse.de> Cc: Mauro Carvalho Chehab <mchehab@infradead.org> Cc: Bjorn Helgaas <bjorn.helgaas@hp.com> Cc: Alessandro Zummo <a.zummo@towertech.it> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | proc: remove proc_busAlexey Dobriyan2008-04-291-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Remove proc_bus export and variable itself. Using pathnames works fine and is slightly more understandable and greppable. Signed-off-by: Alexey Dobriyan <adobriyan@gmail.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* | | drivers: fix integer as NULL pointer warningsHarvey Harrison2008-04-291-1/+1
|/ / | | | | | | | | Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* / intel-iommu.c: dma ops fixIngo Molnar2008-04-241-18/+17
|/ | | | | | | | | | | | | | | | Stephen Rothwell noticed that: Commit 2be621498d461b63ca6124f86e3b9582e1a8e722 ("x86: dma-ops on highmem fix") in Linus' tree introduced a new warning (noticed in the x86_64 allmodconfig build of linux-next): drivers/pci/intel-iommu.c:2240: warning: initialization from incompatible pointer type Which points at an instance of map_single that needs updating. Fix it to the new prototype. Signed-off-by: Ingo Molnar <mingo@elte.hu>
* Fix cardbus resource allocationLinus Torvalds2008-04-231-15/+15
| | | | | | | | | | | | | | | | | | | | | | | Commit 884525655d07fdee9245716b998ecdc45cdd8007 ("PCI: clean up resource alignment management") didn't set the alignment information for the cardbus window resources, causing their subsequent allocations to fail miserably with a message like yenta_cardbus 0000:15:00.0: device not available because of BAR 7 [100:1ff] collisions yenta_cardbus: probe of 0000:15:00.0 failed with error -16 or similar. This fixes it and clarifies the code a bit too (we used to have to use the insane PCI bridge alignment logic that put the alignment in the "start" field, this makes it use the slightly easier-to-understand size-based alignment, and allows us to set the resource start to zero until it gets allocated). Reported-and-tested-by: Jeff Chua <jeff.chua.linux@gmail.com> Cc: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Jesse Barnes <jbarnes@virtuousgeek.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
* Merge git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6Linus Torvalds2008-04-2257-826/+2049
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/pci-2.6: (42 commits) PCI: Change PCI subsystem MAINTAINER PCI: pci-iommu-iotlb-flushing-speedup PCI: pci_setup_bridge() mustn't be __devinit PCI: pci_bus_size_cardbus() mustn't be __devinit PCI: pci_scan_device() mustn't be __devinit PCI: pci_alloc_child_bus() mustn't be __devinit PCI: replace remaining __FUNCTION__ occurrences PCI: Hotplug: fakephp: Return success, not ENODEV, when bus rescan is triggered PCI: Hotplug: Fix leaks in IBM Hot Plug Controller Driver - ibmphp_init_devno() PCI: clean up resource alignment management PCI: aerdrv_acpi.c: remove unneeded NULL check PCI: Update VIA CX700 quirk PCI: Expose PCI VPD through sysfs PCI: iommu: iotlb flushing PCI: simplify quirk debug output PCI: iova RB tree setup tweak PCI: parisc: use generic pci_enable_resources() PCI: ppc: use generic pci_enable_resources() PCI: powerpc: use generic pci_enable_resources() PCI: ia64: use generic pci_enable_resources() ...
| * PCI: pci-iommu-iotlb-flushing-speedupmark gross2008-04-212-38/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch is an update to use an array instead of a list of IOVA's in the implementation of defered iotlb flushes. It takes inspiration from sba_iommu.c I like this implementation better as it encapsulates the batch process within intel-iommu.c, and no longer touches iova.h (which is shared) Performance data: Netperf 32byte UDP streaming 2.6.25-rc3-mm1: IOMMU-strict : 58Mps @ 62% cpu NO-IOMMU : 71Mbs @ 41% cpu List-based IOMMU-default-batched-IOTLB flush: 66Mbps @ 57% cpu with this patch: IOMMU-strict : 73Mps @ 75% cpu NO-IOMMU : 74Mbs @ 42% cpu Array-based IOMMU-default-batched-IOTLB flush: 72Mbps @ 62% cpu Signed-off-by: <mgross@linux.intel.com> Cc: Grant Grundler <grundler@parisc-linux.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: pci_setup_bridge() mustn't be __devinitAdrian Bunk2008-04-211-2/+1
| | | | | | | | | | | | | | | | | | WARNING: drivers/pci/built-in.o(.text+0x28ee9): Section mismatch in reference from the function pci_bus_assign_resources() to the function .devinit.text:pci_setup_bridge() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: pci_bus_size_cardbus() mustn't be __devinitAdrian Bunk2008-04-211-2/+1
| | | | | | | | | | | | | | | | | | WARNING: drivers/pci/built-in.o(.text+0x28e1f): Section mismatch in reference from the function pci_bus_size_bridges() to the function .devinit.text:pci_bus_size_cardbus() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: pci_scan_device() mustn't be __devinitAdrian Bunk2008-04-211-2/+1
| | | | | | | | | | | | | | | | | | WARNING: drivers/pci/built-in.o(.text+0x150f): Section mismatch in reference from the function pci_scan_single_device() to the function .devinit.text:pci_scan_device() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: pci_alloc_child_bus() mustn't be __devinitAdrian Bunk2008-04-211-2/+2
| | | | | | | | | | | | | | | | | | WARNING: drivers/pci/built-in.o(.text+0xc4c): Section mismatch in reference from the function pci_add_new_bus() to the function .devinit.text:pci_alloc_child_bus() Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: replace remaining __FUNCTION__ occurrencesHarvey Harrison2008-04-2139-487/+487
| | | | | | | | | | | | | | | | __FUNCTION__ is gcc-specific, use __func__ Signed-off-by: Harvey Harrison <harvey.harrison@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Hotplug: fakephp: Return success, not ENODEV, when bus rescan is triggeredTrent Piepho2008-04-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 'power' attribute of the fakephp driver originally only let one turn a slot off. If one tried to turn a slot on (echo 1 > .../power), it would return ENODEV, as fakephp did not support this function. An old (pre-git) patch changed this: 2004/11/11 16:33:31-08:00 jdittmer [PATCH] fakephp: add pci bus rescan ability http://article.gmane.org/gmane.linux.kernel/251183 Now writing "1" to the power attribute has the effect of triggering a bus rescan, but it still returns ENODEV, probably an oversight in the above patch. Using the BusyBox echo will not produce an error message, but will trigger *two* bus rescans (and return an exit code of 1): ~ # strace echo -n 1 > /sys/bus/pci/slots/0000:00:00.0/power ... write(1, "1", 1) = -1 ENODEV (No such device) write(1, "1", 1) = -1 ENODEV (No such device) exit(1) = ? Using cp gives a write error, even though the write did happen and a rescan was triggered: ~ # echo -n 1 > tmp ; cp tmp /sys/bus/pci/slots/0000:00:00.0/power cp: Write Error: No such device It seems much better to return success instead of failure. The actual status of the bus rescan is hard to return. It happens asynchronously in a work thread, so the sysfs store functions returns before any status is ready (the whole point of the work queue). And even if it didn't do this, the rescan doesn't have any clear status to return. Signed-off-by: Trent Piepho <tpiepho@freescale.com> CC: Jan Dittmer <jdittmer@ppp0.net> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Hotplug: Fix leaks in IBM Hot Plug Controller Driver - ibmphp_init_devno()Jesper Juhl2008-04-211-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In drivers/pci/hotplug/ibmphp_core.c::ibmphp_init_devno() we allocate space dynamically for a PCI irq routing table by calling pcibios_get_irq_routing_table(), but we never free the allocated space. This patch frees the allocated space at the function exit points. Spotted by the Coverity checker. Compile tested only. Please consider applying. Signed-off-by: Jesper Juhl <jesper.juhl@gmail.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: clean up resource alignment managementIvan Kokshaysky2008-04-213-21/+29
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Done per Linus' request and suggestions. Linus has explained that better than I'll be able to explain: On Thu, Mar 27, 2008 at 10:12:10AM -0700, Linus Torvalds wrote: > Actually, before we go any further, there might be a less intrusive > alternative: add just a couple of flags to the resource flags field (we > still have something like 8 unused bits on 32-bit), and use those to > implement a generic "resource_alignment()" routine. > > Two flags would do it: > > - IORESOURCE_SIZEALIGN: size indicates alignment (regular PCI device > resources) > > - IORESOURCE_STARTALIGN: start field is alignment (PCI bus resources > during probing) > > and then the case of both flags zero (or both bits set) would actually be > "invalid", and we would also clear the IORESOURCE_STARTALIGN flag when we > actually allocate the resource (so that we don't use the "start" field as > alignment incorrectly when it no longer indicates alignment). > > That wouldn't be totally generic, but it would have the nice property of > automatically at least add sanity checking for that whole "res->start has > the odd meaning of 'alignment' during probing" and remove the need for a > new field, and it would allow us to have a generic "resource_alignment()" > routine that just gets a resource pointer. Besides, I removed IORESOURCE_BUS_HAS_VGA flag which was unused for ages. Signed-off-by: Ivan Kokshaysky <ink@jurassic.park.msu.ru> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Gary Hade <garyhade@us.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: aerdrv_acpi.c: remove unneeded NULL checkAdrian Bunk2008-04-211-1/+1
| | | | | | | | | | | | | | | | | | There's no reason for checking pdev->bus for being NULL here (and we'd anyway Oops 3 lines below if it was). Signed-off-by: Adrian Bunk <bunk@kernel.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Update VIA CX700 quirkTim Yamin2008-04-211-1/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This follows up 53a9bf4267b8b1f958dbeb7c8c1ef21c82229b71. Some newer CX700 BIOSes from our vendor have PCI Bus Parking disabled but PCI Master read caching enabled. This creates problems such as system freezing when both the network controller and the USB controller are active and one of them is pretty busy (e.g. heavy network traffic). This patch separates the checks and both the bus parking and the read caching are disabled independently if either is enabled by the BIOS. Signed-off-by: Tim Yamin <tim.yamin@zonbu.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: Expose PCI VPD through sysfsBen Hutchings2008-04-214-14/+283
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Vital Product Data (VPD) may be exposed by PCI devices in several ways. It is generally unsafe to read this information through the existing interfaces to user-land because of stateful interfaces. This adds: - abstract operations for VPD access (struct pci_vpd_ops) - VPD state information in struct pci_dev (struct pci_vpd) - an implementation of the VPD access method specified in PCI 2.2 (in access.c) - a 'vpd' binary file in sysfs directories for PCI devices with VPD operations defined It adds a probe for PCI 2.2 VPD in pci_scan_device() and release of VPD state in pci_release_dev(). Signed-off-by: Ben Hutchings <bhutchings@solarflare.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: iommu: iotlb flushingmark gross2008-04-212-18/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is for batching up the flushing of the IOTLB for the DMAR implementation found in the Intel VT-d hardware. It works by building a list of to be flushed IOTLB entries and a bitmap list of which DMAR engine they are from. After either a high water mark (250 accessible via debugfs) or 10ms the list of iova's will be reclaimed and the DMAR engines associated are IOTLB-flushed. This approach recovers 15 to 20% of the performance lost when using the IOMMU for my netperf udp stream benchmark with small packets. It can be disabled with a kernel boot parameter "intel_iommu=strict". Its use does weaken the IOMMU protections a bit. Signed-off-by: Mark Gross <mgross@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: simplify quirk debug outputBjorn Helgaas2008-04-211-2/+2
| | | | | | | | | | | | | | | | | | | | print_fn_descriptor_symbol() prints the address if we don't have a symbol, so no need to print both. Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: iova RB tree setup tweakmark gross2008-04-211-14/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch merges two functions into one allowing for a 3% reduction in overhead in locating, allocating and inserting pages for use in IOMMU operations. Its a bit of a eye-crosser so I welcome any RB-tree / MM experts to take a look. It works by re-using some of the information gathered in the search for the pages to use in setting up the IOTLB's in the insertion of the iova structure into the RB tree. Signed-off-by: <mgross@linux.intel.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: add generic pci_enable_resources()Bjorn Helgaas2008-04-211-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Each architecture has its own pcibios_enable_resources() implementation. These differ in many minor ways that have nothing to do with actual architectural differences. Follow-on patches will make most arches use this generic version instead. This version is based on powerpc, which seemed most up-to-date. The only functional difference from the x86 version is that this uses "!r->parent" to check for resource collisions instead of "!r->start && r->end". Signed-off-by: Bjorn Helgaas <bjorn.helgaas@hp.com> Acked-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: David Howells <dhowells@redhat.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
| * PCI: add PCI Express ASPM supportShaohua Li2008-04-217-0/+852
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | PCI Express ASPM defines a protocol for PCI Express components in the D0 state to reduce Link power by placing their Links into a low power state and instructing the other end of the Link to do likewise. This capability allows hardware-autonomous, dynamic Link power reduction beyond what is achievable by software-only controlled power management. However, The device should be configured by software appropriately. Enabling ASPM will save power, but will introduce device latency. This patch adds ASPM support in Linux. It introduces a global policy for ASPM, a sysfs file /sys/module/pcie_aspm/parameters/policy can control it. The interface can be used as a boot option too. Currently we have below setting: -default, BIOS default setting -powersave, highest power saving mode, enable all available ASPM state and clock power management -performance, highest performance, disable ASPM and clock power management By default, the 'default' policy is used currently. In my test, power difference between powersave mode and performance mode is about 1.3w in a system with 3 PCIE links. Note: some devices might not work well with aspm, either because chipset issue or device issue. The patch provide API (pci_disable_link_state), driver can disable ASPM for specific device. Signed-off-by: Shaohua Li <shaohua.li@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@suse.de>
generated by cgit v1.2.3 (git 2.39.1) at 2024-12-20 23:08:18 +0100