summaryrefslogtreecommitdiffstats
path: root/drivers/pci (follow)
Commit message (Collapse)AuthorAgeFilesLines
* arm64: bcmbca: Make BCM4908 drivers depend on ARCH_BCMBCAWilliam Zhang2022-08-151-1/+1
| | | | | | | | | | | | | | With Broadcom Broadband arch ARCH_BCMBCA supported in the kernel, this patch series migrate the ARCH_BCM4908 symbol to ARCH_BCMBCA. Hence replace ARCH_BCM4908 with ARCH_BCMBCA in subsystem Kconfig files. Signed-off-by: William Zhang <william.zhang@broadcom.com> Acked-by: Guenter Roeck <linux@roeck-us.net> (for watchdog) Acked-by: Bjorn Helgaas <bhelgaas@google.com> (for drivers/pci) Acked-by: Wolfram Sang <wsa@kernel.org> (for i2c) Acked-by: Philipp Zabel <p.zabel@pengutronix.de> (for reset) Link: https://lore.kernel.org/r/20220803175455.47638-7-william.zhang@broadcom.com Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
* Merge tag 'ntb-5.20' of https://github.com/jonmason/ntbLinus Torvalds2022-08-134-1/+1464
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull NTB updates from Jon Mason: "Non-Transparent Bridge updates. Fix of heap data and clang warnings, support for a new Intel NTB device, and NTB EndPoint Function (EPF) support and the various fixes for that" * tag 'ntb-5.20' of https://github.com/jonmason/ntb: MAINTAINERS: add PCI Endpoint NTB drivers to NTB files NTB: EPF: Tidy up some bounds checks NTB: EPF: Fix error code in epf_ntb_bind() PCI: endpoint: pci-epf-vntb: reduce several globals to statics PCI: endpoint: pci-epf-vntb: fix error handle in epf_ntb_mw_bar_init() PCI: endpoint: Fix Kconfig dependency NTB: EPF: set pointer addr to null using NULL rather than 0 Documentation: PCI: extend subheading underline for "lspci output" section Documentation: PCI: Use code-block block for scratchpad registers diagram Documentation: PCI: Add specification for the PCI vNTB function device PCI: endpoint: Support NTB transfer between RC and EP NTB: epf: Allow more flexibility in the memory BAR map method PCI: designware-ep: Allow pci_epc_set_bar() update inbound map address ntb: intel: add GNR support for Intel PCIe gen5 NTB NTB: ntb_tool: uninitialized heap data in tool_fn_write() ntb: idt: fix clang -Wformat warnings
| * NTB: EPF: Tidy up some bounds checksDan Carpenter2022-08-091-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This sscanf() is reading from the filename which was set by the kernel so it should be trust worthy. Although the data is likely trust worthy there is some bounds checking but unfortunately, it is not complete or consistent. Additionally, the Smatch static checker marks everything that comes from sscanf() as tainted and so Smatch complains that this code can lead to an out of bounds issue. Let's clean things up and make Smatch happy. The first problem is that there is no bounds checking in the _show() functions. The _store() and _show() functions are very similar so make the bounds checking the same in both. The second issue is that if "win_no" is zero it leads to an array underflow so add an if (win_no <= 0) check for that. Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * NTB: EPF: Fix error code in epf_ntb_bind()Dan Carpenter2022-08-091-1/+2
| | | | | | | | | | | | | | | | | | | | Return an error code if pci_register_driver() fails. Don't return success. Fixes: da51fd247424 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com> Acked-by: Souptick Joarder (HPE) <jrdr.linux@gmail.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * PCI: endpoint: pci-epf-vntb: reduce several globals to staticsTom Rix2022-08-091-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sparse reports drivers/pci/endpoint/functions/pci-epf-vntb.c:975:5: warning: symbol 'pci_read' was not declared. Should it be static? drivers/pci/endpoint/functions/pci-epf-vntb.c:984:5: warning: symbol 'pci_write' was not declared. Should it be static? drivers/pci/endpoint/functions/pci-epf-vntb.c:989:16: warning: symbol 'vpci_ops' was not declared. Should it be static? These functions and variables are only used in pci-epf-vntb.c, so their storage class specifiers should be static. Fixes: ff32fac00d97 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Tom Rix <trix@redhat.com> Acked-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * PCI: endpoint: pci-epf-vntb: fix error handle in epf_ntb_mw_bar_init()Yang Yingliang2022-08-091-5/+15
| | | | | | | | | | | | | | | | | | | | | | | | In error case of epf_ntb_mw_bar_init(), memory window BARs should be cleared, so add 'num_mws' parameter in epf_ntb_mw_bar_clear() and calling it in error path to clear the BARs. Also add missing error code when pci_epc_mem_alloc_addr() fails. Fixes: ff32fac00d97 ("NTB: EPF: support NTB transfer between PCI RC and EP connection") Reported-by: Hulk Robot <hulkci@huawei.com> Signed-off-by: Yang Yingliang <yangyingliang@huawei.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * PCI: endpoint: Fix Kconfig dependencyRen Zhijie2022-08-091-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If CONFIG_NTB is not set and CONFIG_PCI_EPF_VNTB is y. make ARCH=x86_64 CROSS_COMPILE=x86_64-linux-gnu-, will be failed, like this: drivers/pci/endpoint/functions/pci-epf-vntb.o: In function `epf_ntb_cmd_handler': pci-epf-vntb.c:(.text+0x95e): undefined reference to `ntb_db_event' pci-epf-vntb.c:(.text+0xa1f): undefined reference to `ntb_link_event' pci-epf-vntb.c:(.text+0xa42): undefined reference to `ntb_link_event' drivers/pci/endpoint/functions/pci-epf-vntb.o: In function `pci_vntb_probe': pci-epf-vntb.c:(.text+0x1250): undefined reference to `ntb_register_device' The functions ntb_*() are defined in drivers/ntb/core.c, which need CONFIG_NTB setting y to be build-in. To fix this build error, add depends on NTB. Reported-by: Hulk Robot <hulkci@huawei.com> Fixes: ff32fac00d97("NTB: EPF: support NTB transfer between PCI RC and EP connection") Signed-off-by: Ren Zhijie <renzhijie2@huawei.com> Acked-by: Frank Li <frank.li@nxp.com> Acked-by: Randy Dunlap <rdunlap@infradead.org> Tested-by: Randy Dunlap <rdunlap@infradead.org> # build-tested Reported-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * NTB: EPF: set pointer addr to null using NULL rather than 0Colin Ian King2022-08-091-1/+1
| | | | | | | | | | | | | | | | | | | | The pointer addr is being set to null using 0. Use NULL instead. Cleans up sparse warning: warning: Using plain integer as NULL pointer Signed-off-by: Colin Ian King <colin.i.king@gmail.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * PCI: endpoint: Support NTB transfer between RC and EPFrank Li2022-08-093-0/+1436
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add NTB function driver and virtual PCI Bus and Virtual NTB driver to implement communication between PCIe Root Port and PCIe EP devices ┌────────────┐ ┌─────────────────────────────────────┐ │ │ │ │ ├────────────┤ │ ┌──────────────┤ │ NTB │ │ │ NTB │ │ NetDev │ │ │ NetDev │ ├────────────┤ │ ├──────────────┤ │ NTB │ │ │ NTB │ │ Transfer │ │ │ Transfer │ ├────────────┤ │ ├──────────────┤ │ │ │ │ │ │ PCI NTB │ │ │ │ │ EPF │ │ │ │ │ Driver │ │ │ PCI Virtual │ │ │ ├───────────────┐ │ NTB Driver │ │ │ │ PCI EP NTB │◄────►│ │ │ │ │ FN Driver │ │ │ ├────────────┤ ├───────────────┤ ├──────────────┤ │ │ │ │ │ │ │ PCI Bus │ ◄─────► │ PCI EP Bus │ │ Virtual PCI │ │ │ PCI │ │ │ Bus │ └────────────┘ └───────────────┴──────┴──────────────┘ PCIe Root Port PCI EP This driver includes 3 parts: 1 PCI EP NTB function driver 2 Virtual PCI bus 3 PCI virtual NTB driver, which is loaded only by above virtual PCI bus Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
| * PCI: designware-ep: Allow pci_epc_set_bar() update inbound map addressFrank Li2022-08-091-1/+9
| | | | | | | | | | | | | | | | | | | | | | | | ntb_mw_set_trans() will set memory map window after endpoint function driver bind. The inbound map address need be updated dynamically when using NTB by PCIe Root Port and PCIe Endpoint connection. Checking if iatu already assigned to the BAR, if yes, using assigned iatu number to update inbound address map and skip set BAR's register. Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
* | Merge tag 'cxl-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxlLinus Torvalds2022-08-104-1/+541
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Pull cxl updates from Dan Williams: "Compute Express Link (CXL) updates for 6.0: - Introduce a 'struct cxl_region' object with support for provisioning and assembling persistent memory regions. - Introduce alloc_free_mem_region() to accompany the existing request_free_mem_region() as a method to allocate physical memory capacity out of an existing resource. - Export insert_resource_expand_to_fit() for the CXL subsystem to late-publish CXL platform windows in iomem_resource. - Add a polled mode PCI DOE (Data Object Exchange) driver service and use it in cxl_pci to retrieve the CDAT (Coherent Device Attribute Table)" * tag 'cxl-for-6.0' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl/cxl: (74 commits) cxl/hdm: Fix skip allocations vs multiple pmem allocations cxl/region: Disallow region granularity != window granularity cxl/region: Fix x1 interleave to greater than x1 interleave routing cxl/region: Move HPA setup to cxl_region_attach() cxl/region: Fix decoder interleave programming Documentation: cxl: remove dangling kernel-doc reference cxl/region: describe targets and nr_targets members of cxl_region_params cxl/regions: add padding for cxl_rr_ep_add nested lists cxl/region: Fix IS_ERR() vs NULL check cxl/region: Fix region reference target accounting cxl/region: Fix region commit uninitialized variable warning cxl/region: Fix port setup uninitialized variable warnings cxl/region: Stop initializing interleave granularity cxl/hdm: Fix DPA reservation vs cxl_endpoint_decoder lifetime cxl/acpi: Minimize granularity for x1 interleaves cxl/region: Delete 'region' attribute from root decoders cxl/acpi: Autoload driver for 'cxl_acpi' test devices cxl/region: decrement ->nr_targets on error in cxl_region_attach() cxl/region: prevent underflow in ways_to_cxl() cxl/region: uninitialized variable in alloc_hpa() ...
| * | PCI/DOE: Add DOE mailbox support functionsJonathan Cameron2022-07-203-0/+540
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduced in a PCIe r6.0, sec 6.30, DOE provides a config space based mailbox with standard protocol discovery. Each mailbox is accessed through a DOE Extended Capability. Each DOE mailbox must support the DOE discovery protocol in addition to any number of additional protocols. Define core PCIe functionality to manage a single PCIe DOE mailbox at a defined config space offset. Functionality includes iterating, creating, query of supported protocol, and task submission. Destruction of the mailboxes is device managed. Cc: "Li, Ming" <ming4.li@intel.com> Cc: Bjorn Helgaas <helgaas@kernel.org> Cc: Matthew Wilcox <willy@infradead.org> Acked-by: Bjorn Helgaas <helgaas@kernel.org> Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Co-developed-by: Ira Weiny <ira.weiny@intel.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/20220719205249.566684-4-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
| * | PCI: Replace magic constant for PCI Sig Vendor IDIra Weiny2022-07-201-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | Replace the magic value in pci_bus_crs_vendor_id() with PCI_VENDOR_ID_PCI_SIG. Reviewed-by: Dan Williams <dan.j.williams@intel.com> Reviewed-by: Davidlohr Bueso <dave@stgolabs.net> Suggested-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Signed-off-by: Ira Weiny <ira.weiny@intel.com> Link: https://lore.kernel.org/r/20220719205249.566684-3-ira.weiny@intel.com Signed-off-by: Dan Williams <dan.j.williams@intel.com>
* | Merge tag 'dma-mapping-5.20-2022-08-06' of ↵Linus Torvalds2022-08-062-62/+36
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.infradead.org/users/hch/dma-mapping Pull dma-mapping updates from Christoph Hellwig: - convert arm32 to the common dma-direct code (Arnd Bergmann, Robin Murphy, Christoph Hellwig) - restructure the PCIe peer to peer mapping support (Logan Gunthorpe) - allow the IOMMU code to communicate an optional DMA mapping length and use that in scsi and libata (John Garry) - split the global swiotlb lock (Tianyu Lan) - various fixes and cleanup (Chao Gao, Dan Carpenter, Dongli Zhang, Lukas Bulwahn, Robin Murphy) * tag 'dma-mapping-5.20-2022-08-06' of git://git.infradead.org/users/hch/dma-mapping: (45 commits) swiotlb: fix passing local variable to debugfs_create_ulong() dma-mapping: reformat comment to suppress htmldoc warning PCI/P2PDMA: Remove pci_p2pdma_[un]map_sg() RDMA/rw: drop pci_p2pdma_[un]map_sg() RDMA/core: introduce ib_dma_pci_p2p_dma_supported() nvme-pci: convert to using dma_map_sgtable() nvme-pci: check DMA ops when indicating support for PCI P2PDMA iommu/dma: support PCI P2PDMA pages in dma-iommu map_sg iommu: Explicitly skip bus address marked segments in __iommu_map_sg() dma-mapping: add flags to dma_map_ops to indicate PCI P2PDMA support dma-direct: support PCI P2PDMA pages in dma-direct map_sg dma-mapping: allow EREMOTEIO return code for P2PDMA transfers PCI/P2PDMA: Introduce helpers for dma_map_sg implementations PCI/P2PDMA: Attempt to set map_type if it has not been set lib/scatterlist: add flag for indicating P2PDMA segments in an SGL swiotlb: clean up some coding style and minor issues dma-mapping: update comment after dmabounce removal scsi: sd: Add a comment about limiting max_sectors to shost optimal limit ata: libata-scsi: cap ata_device->max_sectors according to shost->max_sectors scsi: scsi_transport_sas: cap shost opt_sectors according to DMA optimal limit ...
| * | PCI/P2PDMA: Remove pci_p2pdma_[un]map_sg()Logan Gunthorpe2022-07-261-66/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This interface is superseded by support in dma_map_sg() which now supports heterogeneous scatterlists. There are no longer any users, so remove it. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Jason Gunthorpe <jgg@nvidia.com> Reviewed-by: Max Gurtovoy <mgurtovoy@nvidia.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Introduce helpers for dma_map_sg implementationsLogan Gunthorpe2022-07-261-7/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add pci_p2pdma_map_segment() as a helper for dma_map_sg() implementations. It takes an scatterlist segment that must point to a pci_p2pdma struct page and will map it if the mapping requires a bus address. The return value indicates whether the mapping required a bus address or whether the caller still needs to map the segment normally. If the segment should not be mapped, -EREMOTEIO is returned. This helper uses a state structure to track the changes to the pgmap across calls and avoid needing to lookup into the xarray for every page. The prototype for the helper is added to dma-map-ops.h as it is only useful to dma map implementations and don't need to pollute the public pci-p2pdma header. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Christoph Hellwig <hch@lst.de>
| * | PCI/P2PDMA: Attempt to set map_type if it has not been setLogan Gunthorpe2022-07-261-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Attempt to find the mapping type for P2PDMA pages on the first DMA map attempt if it has not been done ahead of time. Previously, the mapping type was expected to be calculated ahead of time, but if pages are to come from userspace then there's no way to ensure the path was checked ahead of time. This change will calculate the mapping type if it hasn't pre-calculated so it is no longer invalid to call pci_p2pdma_map_sg() before the mapping type is calculated, so drop the WARN_ON when that is the case. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Acked-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Chaitanya Kulkarni <kch@nvidia.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Christoph Hellwig <hch@lst.de>
| * | lib/scatterlist: add flag for indicating P2PDMA segments in an SGLLogan Gunthorpe2022-07-261-0/+5
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce a dma_flags field in struct scatterlist. These flags will be used by dma_[un]map_sg_p2pdma() to determine when a given SGL segments dma_address points to a PCI bus address. dma_unmap_sg_p2pdma() will need to perform different cleanup when a segment is marked as a bus address. The dma_flags field will fit in the existing padding on 64BIT systems (assuming CONFIG_NEED_SG_DMA_LENGTH is also set). The new bit will only be used when CONFIG_PCI_P2PDMA is set; this means PCI P2PDMA will require CONFIG_64BIT. This should be acceptable as the majority of P2PDMA use cases are restricted to newer root complexes and roughly require the extra address space for memory BARs used in the transactions. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Signed-off-by: Christoph Hellwig <hch@lst.de>
* | Merge tag 'pci-v5.20-changes' of ↵Linus Torvalds2022-08-0557-1735/+2721
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci Pull pci updates from Bjorn Helgaas: "Enumeration: - Consolidate duplicated 'next function' scanning and extend to allow 'isolated functions' on s390, similar to existing hypervisors (Niklas Schnelle) Resource management: - Implement pci_iobar_pfn() for sparc, which allows us to remove the sparc-specific pci_mmap_page_range() and pci_mmap_resource_range(). This removes the ability to map the entire PCI I/O space using /proc/bus/pci, but we believe that's already been broken since v2.6.28 (Arnd Bergmann) - Move common PCI definitions to asm-generic/pci.h and rework others to be be more specific and more encapsulated in arches that need them (Stafford Horne) Power management: - Convert drivers to new *_PM_OPS macros to avoid need for '#ifdef CONFIG_PM_SLEEP' or '__maybe_unused' (Bjorn Helgaas) Virtualization: - Add ACS quirk for Broadcom BCM5750x multifunction NICs that isolate the functions but don't advertise an ACS capability (Pavan Chebbi) Error handling: - Clear PCI Status register during enumeration in case firmware left errors logged (Kai-Heng Feng) - When we have native control of AER, enable error reporting for all devices that support AER. Previously only a few drivers enabled this (Stefan Roese) - Keep AER error reporting enabled for switches. Previously we enabled this during enumeration but immediately disabled it (Stefan Roese) - Iterate over error counters instead of error strings to avoid printing junk in AER sysfs counters (Mohamed Khalfella) ASPM: - Remove pcie_aspm_pm_state_change() so ASPM config changes, e.g., via sysfs, are not lost across power state changes (Kai-Heng Feng) Endpoint framework: - Don't stop an EPC when unbinding an EPF from it (Shunsuke Mie) Endpoint embedded DMA controller driver: - Simplify and clean up support for the DesignWare embedded DMA (eDMA) controller (Frank Li, Serge Semin) Broadcom STB PCIe controller driver: - Avoid config space accesses when link is down because we can't recover from the CPU aborts these cause (Jim Quinlan) - Look for power regulators described under Root Ports in DT and enable them before scanning the secondary bus (Jim Quinlan) - Disable/enable regulators in suspend/resume (Jim Quinlan) Freescale i.MX6 PCIe controller driver: - Simplify and clean up clock and PHY management (Richard Zhu) - Disable/enable regulators in suspend/resume (Richard Zhu) - Set PCIE_DBI_RO_WR_EN before writing DBI registers (Richard Zhu) - Allow speeds faster than Gen2 (Richard Zhu) - Make link being down a non-fatal error so controller probe doesn't fail if there are no Endpoints connected (Richard Zhu) Loongson PCIe controller driver: - Add ACPI and MCFG support for Loongson LS7A (Huacai Chen) - Avoid config reads to non-existent LS2K/LS7A devices because a hardware defect causes machine hangs (Huacai Chen) - Work around LS7A integrated devices that report incorrect Interrupt Pin values (Jianmin Lv) Marvell Aardvark PCIe controller driver: - Add support for AER and Slot capability on emulated bridge (Pali Rohár) MediaTek PCIe controller driver: - Add Airoha EN7532 to DT binding (John Crispin) - Allow building of driver for ARCH_AIROHA (Felix Fietkau) MediaTek PCIe Gen3 controller driver: - Print decoded LTSSM state when the link doesn't come up (Jianjun Wang) NVIDIA Tegra194 PCIe controller driver: - Convert DT binding to json-schema (Vidya Sagar) - Add DT bindings and driver support for Tegra234 Root Port and Endpoint mode (Vidya Sagar) - Fix some Root Port interrupt handling issues (Vidya Sagar) - Set default Max Payload Size to 256 bytes (Vidya Sagar) - Fix Data Link Feature capability programming (Vidya Sagar) - Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar) Qualcomm PCIe controller driver: - Rework clock, reset, PHY power-on ordering to avoid hangs and improve consistency (Robert Marko, Christian Marangi) - Move pipe_clk handling to PHY drivers (Dmitry Baryshkov) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) - Add support for more than 32 MSI interrupts (Dmitry Baryshkov) Renesas R-Car PCIe controller driver: - Convert DT binding to json-schema (Herve Codina) - Add Renesas RZ/N1D (R9A06G032) to rcar-gen2 DT binding and driver (Herve Codina) Samsung Exynos PCIe controller driver: - Fix phy-exynos-pcie driver so it follows the 'phy_init() before phy_power_on()' PHY programming model (Marek Szyprowski) Synopsys DesignWare PCIe controller driver: - Simplify and clean up the DWC core extensively (Serge Semin) - Fix an issue with programming the ATU for regions that cross a 4GB boundary (Serge Semin) - Enable the CDM check if 'snps,enable-cdm-check' exists; previously we skipped it if 'num-lanes' was absent (Serge Semin) - Allocate a 32-bit DMA-able page to be MSI target instead of using a driver data structure that may not be addressable with 32-bit address (Will McVicker) - Add DWC core support for more than 32 MSI interrupts (Dmitry Baryshkov) Xilinx Versal CPM PCIe controller driver: - Add DT binding and driver support for Versal CPM5 Gen5 Root Port (Bharat Kumar Gogada)" * tag 'pci-v5.20-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (150 commits) PCI: imx6: Support more than Gen2 speed link mode PCI: imx6: Set PCIE_DBI_RO_WR_EN before writing DBI registers PCI: imx6: Reformat suspend callback to keep symmetric with resume PCI: imx6: Move the imx6_pcie_ltssm_disable() earlier PCI: imx6: Disable clocks in reverse order of enable PCI: imx6: Do not hide PHY driver callbacks and refine the error handling PCI: imx6: Reduce resume time by only starting link if it was up before suspend PCI: imx6: Mark the link down as non-fatal error PCI: imx6: Move regulator enable out of imx6_pcie_deassert_core_reset() PCI: imx6: Turn off regulator when system is in suspend mode PCI: imx6: Call host init function directly in resume PCI: imx6: Disable i.MX6QDL clock when disabling ref clocks PCI: imx6: Propagate .host_init() errors to caller PCI: imx6: Collect clock enables in imx6_pcie_clk_enable() PCI: imx6: Factor out ref clock disable to match enable PCI: imx6: Move imx6_pcie_clk_disable() earlier PCI: imx6: Move imx6_pcie_enable_ref_clk() earlier PCI: imx6: Move PHY management functions together PCI: imx6: Move imx6_pcie_grp_offset(), imx6_pcie_configure_type() earlier PCI: imx6: Convert to NOIRQ_SYSTEM_SLEEP_PM_OPS() ...
| * \ Merge branch 'pci/header-cleanup-immutable'Bjorn Helgaas2022-08-042-1/+5
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Remove pci_get_legacy_ide_irq(); use ATA_PRIMARY_IRQ() and ATA_SECONDARY_IRQ() instead (Stafford Horne) - Remove isa_dma_bridge_buggy, except for x86_32, the only place it's used (Stafford Horne) - Define ARCH_GENERIC_PCI_MMAP_RESOURCE for csky (Stafford Horne) - Move common PCI definitions that arches sometimes override to asm-generic/pci.h (Stafford Horne) - Include <linux/isa-dma.h> for 'isa_dma_bridge_buggy' when needed (bisection hole here) (Randy Dunlap) * pci/header-cleanup-immutable: PCI: Stub __pci_ioport_map() for arches that don't support it at all x86/cyrix: include header linux/isa-dma.h asm-generic: Add new pci.h and use it csky: PCI: Define ARCH_GENERIC_PCI_MMAP_RESOURCE PCI: Move isa_dma_bridge_buggy out of asm/dma.h PCI: Remove pci_get_legacy_ide_irq() and asm-generic/pci.h
| | * | PCI: Move isa_dma_bridge_buggy out of asm/dma.hStafford Horne2022-07-232-1/+5
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The isa_dma_bridge_buggy symbol is only used for x86_32, and only x86_32 platforms or quirks ever set it. Add a new linux/isa-dma.h header that #defines isa_dma_bridge_buggy to 0 except on x86_32, where we keep it as a variable, and remove all the arch- specific definitions. [bhelgaas: commit log] Suggested-by: Arnd Bergmann <arnd@arndb.de> Suggested-by: Christoph Hellwig <hch@infradead.org> Link: https://lore.kernel.org/r/20220722214944.831438-3-shorne@gmail.com Signed-off-by: Stafford Horne <shorne@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Christoph Hellwig <hch@lst.de> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org>
| * | Merge branch 'pci/misc'Bjorn Helgaas2022-08-045-6/+7
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Drop of_match_ptr() to avoid unused variables when CONFIG_OF is unset (Bjorn Helgaas) - Fix ARM pci_remap_iospace() when CONFIG_MMU unset to avoid build errors (Pali Rohár) * pci/misc: PCI/ACPI: Update link to PCI firmware specification PCI: Drop of_match_ptr() to avoid unused variables
| | * | PCI/ACPI: Update link to PCI firmware specificationMario Limonciello2022-07-221-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The previous link to the PCI firmware specification in the comments for drivers/pci/pci-acpi.c no longer works. Update the comment to a current link to this specification. Link: https://lore.kernel.org/r/20220722174754.27921-1-mario.limonciello@amd.com Signed-off-by: Mario Limonciello <mario.limonciello@amd.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: Drop of_match_ptr() to avoid unused variablesBjorn Helgaas2022-07-064-4/+4
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have stubs for most OF interfaces even when CONFIG_OF is not set, so we allow building of most controller drivers in that case for compile testing. When CONFIG_OF is not set, "of_match_ptr(<match_table>)" compiles to NULL, which leaves <match_table> unused, resulting in errors like this: $ make W=1 drivers/pci/controller/pci-xgene.c:636:34: error: ‘xgene_pcie_match_table’ defined but not used [-Werror=unused-const-variable=] Drop of_match_ptr() to avoid the unused variable warning. Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/ctrl/pm-ops'Bjorn Helgaas2022-08-0410-42/+35
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Convert to new *_PM_OPS macros to avoid need for "#ifdef CONFIG_PM_SLEEP" or "__maybe_unused" (Bjorn Helgaas) * pci/ctrl/pm-ops: PCI: Convert to new *_PM_OPS macros
| | * | PCI: Convert to new *_PM_OPS macrosBjorn Helgaas2022-07-2710-42/+35
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Replace SET_*_PM_OPS with *_PM_OPS, which which have the advantage that the compiler always sees the PM callbacks as referenced, so they don't need to be wrapped with "#ifdef CONFIG_PM_SLEEP" or tagged with "__maybe_unused" to avoid "defined but not used" warnings. See 1a3c7bb08826 ("PM: core: Add new *_PM_OPS macros, deprecate old ones"). Link: https://lore.kernel.org/r/20220719215108.1583108-1-helgaas@kernel.org Tested-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Pali Rohár <pali@kernel.org> # pci-mvebu.c Reviewed-by: Arnd Bergmann <arnd@arndb.de>
| * | Merge branch 'pci/ctrl/xilinx-cpm'Bjorn Helgaas2022-08-041-2/+58
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add DT binding and driver support for Versal CPM5 Gen5 Root Port (Bharat Kumar Gogada) * pci/ctrl/xilinx-cpm: MAINTAINERS: Add Xilinx Versal CPM Root Port maintainers PCI: xilinx-cpm: Add support for Versal CPM5 Root Port dt-bindings: PCI: xilinx-cpm: Add Versal CPM5 Root Port
| | * | PCI: xilinx-cpm: Add support for Versal CPM5 Root PortBharat Kumar Gogada2022-07-221-2/+58
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Xilinx Versal Premium series has CPM5 block which supports Root Port functioning at Gen5 speed. Xilinx Versal CPM5 has a few changes from the existing CPM block: - CPM5 has dedicated register space for control and status registers. - CPM5 legacy interrupt handling needs additional register bit to enable and handle legacy interrupts. Add support for the new CPM5 features. [bhelgaas: compare variant->version with CPM5 explicitly] Link: https://lore.kernel.org/r/20220705105646.16980-3-bharat.kumar.gogada@xilinx.com Signed-off-by: Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| * | Merge branch 'pci/ctrl/vmd'Bjorn Helgaas2022-08-041-3/+10
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Use devm_kasprintf() instead of simple kasprintf() (Subramanian Mohan) - Add [8086:7D0B] and [8086:AD0B] devices to VMD driver (Francisco Munoz) * pci/ctrl/vmd: PCI: vmd: Add DID 8086:7D0B and 8086:AD0B for Intel MTL SKUs PCI: vmd: Use devm_kasprintf() instead of simple kasprintf()
| | * | PCI: vmd: Add DID 8086:7D0B and 8086:AD0B for Intel MTL SKUsFrancisco Munoz2022-06-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for VMD devices in MTL-H/P/U/S/M with bus restriction mode and vector 0 disabled for MSI-X remapping. Link: https://lore.kernel.org/r/20220628221023.190547-1-francisco.munoz.ruiz@linux.intel.com Signed-off-by: Francisco Munoz <francisco.munoz.ruiz@linux.intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Nirmal Patel <nirmal.patel@linux.intel.com>
| | * | PCI: vmd: Use devm_kasprintf() instead of simple kasprintf()Subramanian Mohan2022-06-101-3/+2
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use devm_kasprintf() instead of simple kasprintf() to free allocated memory automatically when the device is freed. Suggested-by: Srikanth Thokala <srikanth.thokala@intel.com> Link: https://lore.kernel.org/r/20220531132617.20517-1-subramanian.mohan@intel.com Signed-off-by: Subramanian Mohan <subramanian.mohan@intel.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Nirmal Patel <nirmal.patel@linux.intel.com>
| * | Merge branch 'pci/ctrl/tegra194'Bjorn Helgaas2022-08-043-238/+468
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix tegra_pcie_config_ep() power management in error path (Miaoqian Lin) - Convert DT binding to json-schema (Vidya Sagar) - Add DT bindings and driver support for Tegra234 Root Port and Endpoint mode (Vidya Sagar) - Disable MSI for Tegra234 Root Ports so they use INTx for all events (PCIe doesn't allow mixing INTx and MSI/MSI-X) (Vidya Sagar) - Search for Vendor-Specific RAS-DEC capability instead of hard-coding offset (Vidya Sagar) - Fix unintentional APPL_INTR_STATUS_L0 value overwrite in Root Port interrupt handling (Vidya Sagar) - Clear Bandwidth Management interrupt status bit to avoid interrupt storm (Vidya Sagar) - Set default Max Payload Size to 256 bytes (Vidya Sagar) - Fix offset when clearing bit in Data Link Feature capability (Vidya Sagar) - Extend Endpoint mode support to devices beyond Controller-5 (Vidya Sagar) * pci/ctrl/tegra194: PCI: tegra194: Add Tegra234 PCIe support PCI: tegra194: Extend Endpoint mode support PCI: tegra194: Fix link up retry sequence PCI: tegra194: Clean up the exit path for Endpoint mode PCI: tegra194: Enable support for 256 Byte payload PCI: tegra194: Clear bandwidth management status PCI: tegra194: Fix Root Port interrupt handling PCI: tegra194: Find RAS DES PCIe capability offset Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie" PCI: Disable MSI for Tegra234 Root Ports dt-bindings: PCI: tegra234: Add schema for tegra234 Endpoint mode dt-bindings: PCI: tegra234: Add schema for tegra234 Root Port mode dt-bindings: PCI: tegra194: Convert to json-schema PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep() # Conflicts: # drivers/pci/controller/dwc/pcie-designware.h # drivers/pci/controller/dwc/pcie-tegra194.c
| | * | PCI: tegra194: Add Tegra234 PCIe supportVidya Sagar2022-07-231-59/+225
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add support for Synopsys DesignWare core IP based PCIe host controllers present in the Tegra234 SoC. Link: https://lore.kernel.org/r/20220721142052.25971-17-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Extend Endpoint mode supportVidya Sagar2022-07-231-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since only Controller-5 can be used in the Endpoint mode in P2972-0000 platform, support is available only for Controller-5. Extend that support by enabling the Endpoint mode capable controller during initialization which otherwise is not required if it is only Controller-5. Link: https://lore.kernel.org/r/20220721142052.25971-16-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Fix link up retry sequenceVidya Sagar2022-07-231-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add the missing DLF capability offset while clearing DL_FEATURE_EXCHANGE_EN bit during link up retry. Link: https://lore.kernel.org/r/20220721142052.25971-15-vidyas@nvidia.com Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Clean up the exit path for Endpoint modeVidya Sagar2022-07-231-14/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Clean up the exit path during .remove() and .shutdown() calls when in Endpoint mode. Link: https://lore.kernel.org/r/20220721142052.25971-14-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Enable support for 256 Byte payloadVidya Sagar2022-07-231-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set 256 byte payload as the default in the Device Control Register to allow the PCIe subsystem to enable 256 byte Max Payload Size when a capable link partner is connected. Link: https://lore.kernel.org/r/20220721142052.25971-13-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Clear bandwidth management statusVidya Sagar2022-07-231-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the event of a bandwidth management interrupt, clear the bandwidth management status in the configuration space also along with clearing corresponding status in the application logic register to avoid slew of interrupts. Link: https://lore.kernel.org/r/20220721142052.25971-12-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Fix Root Port interrupt handlingVidya Sagar2022-07-231-24/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As part of Root Port interrupt handling, level-0 register is read first and based on the bits set in that, corresponding level-1 registers are read for further interrupt processing. Since both these values are currently read into the same 'val' variable, checking level-0 bits the second time around is happening on the 'val' variable value of level-1 register contents instead of freshly reading the level-0 value again. Fix by using different variables to store level-0 and level-1 registers contents. Link: https://lore.kernel.org/r/20220721142052.25971-11-vidyas@nvidia.com Fixes: 56e15a238d92 ("PCI: tegra: Add Tegra194 PCIe support") Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Find RAS DES PCIe capability offsetVidya Sagar2022-07-232-37/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Find RAS DES PCIe capability offset instead of hardcoding the offset for each controller. Link: https://lore.kernel.org/r/20220721142052.25971-10-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | Revert "PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie"Vidya Sagar2022-07-231-111/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit b572569183993b68dec0e990b33641e6f77744ba. Revert b57256918399 ("PCI: tegra194: Rename tegra_pcie_dw to tegra194_pcie") to keep the names of data structures generic and not contain any one particular chip name. This is a preparatory change for the upcoming changes that add support for Tegra234. This has no functional impact. Link: https://lore.kernel.org/r/20220721142052.25971-9-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: Disable MSI for Tegra234 Root PortsVidya Sagar2022-07-231-4/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Tegra234 PCIe Root Ports don't generate MSI interrupts for PME and AER events. Since PCIe spec (r6.0 sec 6.1.4.3) doesn't support using a mix of INTx and MSI/MSI-X, MSI needs to be disabled to avoid Root Port service drivers registering their respective ISRs with MSI interrupt and to let only INTx be used for all events. Link: https://lore.kernel.org/r/20220721142052.25971-8-vidyas@nvidia.com Signed-off-by: Vidya Sagar <vidyas@nvidia.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
| | * | PCI: tegra194: Fix PM error handling in tegra_pcie_config_ep()Miaoqian Lin2022-06-081-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | pm_runtime_enable() will increase power disable depth. If dw_pcie_ep_init() fails, we should use pm_runtime_disable() to balance it with pm_runtime_enable(). Add missing pm_runtime_disable() for tegra_pcie_config_ep(). Fixes: c57247f940e8 ("PCI: tegra: Add support for PCIe endpoint mode in Tegra194") Link: https://lore.kernel.org/r/20220602031910.55859-1-linmq006@gmail.com Signed-off-by: Miaoqian Lin <linmq006@gmail.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Vidya Sagar <vidyas@nvidia.com>
| * | Merge branch 'pci/ctrl/switchtec'Bjorn Helgaas2022-08-041-4/+3
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Prefer ida_alloc()/free() over ida_simple_get()/remove() (Ke Liu) * pci/ctrl/switchtec: PCI: switchtec: Prefer ida_alloc()/free() over ida_simple_get()/remove()
| | * | PCI: switchtec: Prefer ida_alloc()/free() over ida_simple_get()/remove()Ke Liu2022-06-091-4/+3
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | Use ida_alloc() and ida_free() instead of deprecated ida_simple_get() and ida_simple_remove(). Link: https://lore.kernel.org/r/20220602071115.3833935-1-liuke94@huawei.com Signed-off-by: Ke Liu <liuke94@huawei.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Acked-by: Logan Gunthorpe <logang@deltatee.com>
| * | Merge branch 'pci/ctrl/rcar-gen2'Bjorn Helgaas2022-08-041-0/+1
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Convert DT binding to json-schema (Herve Codina) - Add Renesas RZ/N1D (R9A06G032) to rcar-gen2 DT binding (Herve Codina) - Add Renesas RZ/N1D compatible string ("renesas,pci-rzn1") to rcar-gen2 driver (Herve Codina) * pci/ctrl/rcar-gen2: PCI: rcar-gen2: Add RZ/N1 SOC family compatible string dt-bindings: PCI: renesas,pci-rcar-gen2: Add device tree support for R9A06G032 dt-bindings: PCI: pci-rcar-gen2: Convert bindings to json-schema
| | * | PCI: rcar-gen2: Add RZ/N1 SOC family compatible stringHerve Codina2022-06-241-0/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Renesas RZ/N1 SOC family support to the Renesas R-Car Gen2 PCI bridge driver. The Renesas RZ/N1 SOC internal PCI bridge is compatible with the one in the R-Car Gen2 family. Tested with the RZ/N1D (R9A06G032) SOC. Link: https://lore.kernel.org/r/20220520094155.313784-4-herve.codina@bootlin.com Signed-off-by: Herve Codina <herve.codina@bootlin.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Rob Herring <robh@kernel.org>
| * | Merge branch 'pci/ctrl/qcom'Bjorn Helgaas2022-08-043-164/+276
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Add PHY clock source implementation (Dmitry Baryshkov) - Use new clk_regmap_phy_mux_ops for gcc-sm8450 and gcc-sc7280 PCIe pipe clocks (Dmitry Baryshkov) - Set up rev 2.1.0 PARF_PHY before enabling clocks (Christian Marangi) - Power on PHY before accessing IPQ8074 DBI registers to avoid boot hangs (Robert Marko) - Power on PHY before accessing DBI registers on all variants for consistency (Robert Marko) - Remove unnecessary pipe_clk handling since this is done in PHY drivers (Dmitry Baryshkov) - Drop manual pipe_clk_src handling (Dmitry Baryshkov) - Move GEN3_RELATED DBI definitions to common dwc header (Baruch Siach) - Define slot capabilities using generic PCI_EXP_SLTCAP_* macros (Baruch Siach) - Add IPQ60xx support (Selvam Sathappan Periakaruppan) - Fix DT description typo (Baruch Siach) - Fix DT "compatibles" typo (Johan Hovold) - Allow ASPM L1 and substates for 2.7.0 (Krishna chaitanya chundru) * pci/ctrl/qcom: PCI: qcom: Allow ASPM L1 and substates for 2.7.0 dt-bindings: PCI: qcom: Fix reset conditional dt-bindings: PCI: qcom: Fix description typo PCI: qcom: Add IPQ60xx support PCI: qcom: Define slot capabilities using PCI_EXP_SLTCAP_* PCI: dwc: Move GEN3_RELATED DBI definitions to common header PCI: qcom: Drop manual pipe_clk_src handling PCI: qcom: Remove unnecessary pipe_clk handling PCI: qcom: Power on PHY before DBI register accesses PCI: qcom: Power on PHY before IPQ8074 DBI register accesses PCI: qcom: Set up rev 2.1.0 PARF_PHY before enabling clocks clk: qcom: gcc-sc7280: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: gcc-sm8450: use new clk_regmap_phy_mux_ops for PCIe pipe clocks clk: qcom: regmap: add PHY clock source implementation
| | * | PCI: qcom: Allow ASPM L1 and substates for 2.7.0Krishna chaitanya chundru2022-07-291-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Allow ASPM L1 and its substates. By default this is disabled in the qcom specific hardware. Enable it explicitly only for controllers belonging to 2_7_0. This does not affect any link capability registers; it will allow the link transitions to L1 and its substates only if they are already supported. Link: https://lore.kernel.org/r/1657886366-32685-1-git-send-email-quic_krichai@quicinc.com Signed-off-by: Krishna chaitanya chundru <quic_krichai@quicinc.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
| | * | PCI: qcom: Add IPQ60xx supportSelvam Sathappan Periakaruppan2022-07-152-0/+131
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | IPQ60xx series of SoCs have one port of PCIe gen 3. Add support for that platform. The code is based on downstream[1] Codeaurora kernel v5.4 (branch win.linuxopenwrt.2.0). Split out the DBI registers access part from .init into .post_init. DBI registers are only accessible after phy_power_on(). [1] https://source.codeaurora.org/quic/qsdk/oss/kernel/linux-ipq-5.4/ Link: https://lore.kernel.org/r/f7f848653c99abbf9a0f877949a44e52329543ae.1655799816.git.baruch@tkos.co.il Tested-by: Robert Marko <robert.marko@sartura.hr> Signed-off-by: Selvam Sathappan Periakaruppan <quic_speriaka@quicinc.com> Signed-off-by: Baruch Siach <baruch.siach@siklu.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Acked-by: Stanimir Varbanov <svarbanov@mm-sol.com>
generated by cgit v1.2.3 (git 2.39.1) at 2025-01-29 18:13:31 +0100